From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC3FFC7EE24 for ; Tue, 6 Jun 2023 11:58:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237283AbjFFL6n (ORCPT ); Tue, 6 Jun 2023 07:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237295AbjFFL6i (ORCPT ); Tue, 6 Jun 2023 07:58:38 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0247910DA for ; Tue, 6 Jun 2023 04:58:33 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1b025d26f4fso52731055ad.1 for ; Tue, 06 Jun 2023 04:58:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686052713; x=1688644713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zml7/O0Lnj0GvJyK92oFTeXRGRkWuEBPtxfKvEIaajI=; b=F6U9ovca0MySfgOFXNjUiOvOBBhVdVyMtZ6fJiR23Xn//ED4/OwnPtVbJM9LXqy/VA 6uv3tDhGAousYkD6jHrKo07rbbo+f4JHqSWyxxl5tiBcitp+I9NyW5TJtipQWJlnCRfc UFuCz4HD8H6Cqr+pe5rtrJIZ+zJg3iW1jyvc5rWg2lErYyy0AsROuPP8NUrHnE8c6FeP FJQCWsDQR7MJEoaZsUkJderZv2Lv5vCJlG+Lek1H6iUnDBPICPqyLdj/DWGsnWxDWdGo iB9rH8GaYqLZcjHhLla1Eh2VJ8y55LJKcHrzpuBP/5LnmdK+cpDeMhESpnQ35chFMYXg H/Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686052713; x=1688644713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zml7/O0Lnj0GvJyK92oFTeXRGRkWuEBPtxfKvEIaajI=; b=YM80wcMJXny9TrwRytQTUBZ2gFV6nZa0QcThtydcHcjtwPcKA8rNyT2AVQ0yHp19jT vN6pZpmrIEbd2yyvAU81521uXN+uidzeVK2hLYxm0t/Pbe7+ZJFkcAy4sLbonhICIBre UrB6HddnySNGJaakuYHgrGIux11i+1lKEekI5z6ZZYdjLngTdyyhKB8blH1Nk+z2Ed9V /iFz+ayiTLJW2DilyhRf+4VJfX8KKtvURxYFolX6D+dHXx42PPN97XZrhhDxAVFaav47 K07NULvHTqLzeVkSeaPek+8SP3DoYvfNoj2djOmKH7pXDNyLCjNnUykm6U1bVWBgJutB SNAA== X-Gm-Message-State: AC+VfDzV2b5SLxNjsK22bIbggTZWLGqVKn2dFI6+Pms9qPY2oLzF21NH dymZ2TsQ27PkKHjPGN/wbelD X-Google-Smtp-Source: ACHHUZ7jjbioYny5tpMpiu7QQ7ABSf6+m+LQWYVPIWH0hARAsPRMUdjK+4sj/xrWRk0U8NAAofa00g== X-Received: by 2002:a17:902:f54d:b0:1b0:2390:3674 with SMTP id h13-20020a170902f54d00b001b023903674mr2301432plf.65.1686052713046; Tue, 06 Jun 2023 04:58:33 -0700 (PDT) Received: from localhost.localdomain ([117.202.186.178]) by smtp.gmail.com with ESMTPSA id b5-20020a170903228500b001acaf7e22bdsm8419226plh.14.2023.06.06.04.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 04:58:32 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/7] PCI: qcom-ep: Pass alignment restriction to the EPF core Date: Tue, 6 Jun 2023 17:28:08 +0530 Message-Id: <20230606115814.53319-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> References: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom PCIe EP controllers have 4K alignment restriction for the outbound window address. Hence, pass this info to the EPF core so that the EPF drivers can make use of this info. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 1435f516d3f7..cd378ce58b22 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -706,6 +706,7 @@ static const struct pci_epc_features qcom_pcie_epc_feat= ures =3D { .core_init_notifier =3D true, .msi_capable =3D true, .msix_capable =3D false, + .align =3D SZ_4K, }; =20 static const struct pci_epc_features * --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0551AC7EE24 for ; Tue, 6 Jun 2023 11:58:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237370AbjFFL6u (ORCPT ); Tue, 6 Jun 2023 07:58:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237299AbjFFL6m (ORCPT ); Tue, 6 Jun 2023 07:58:42 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AFEC10CB for ; Tue, 6 Jun 2023 04:58:37 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1b00ecabdf2so55986425ad.2 for ; Tue, 06 Jun 2023 04:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686052717; x=1688644717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2vScY3E4RObHEz5P1xKAaD36hA/8YhvR3M5FwIPwlZU=; b=UyKHjYlFKGEv7V+UmkB+tBQTolnof2AaJHHca835LpFsLOW2aW9K2eR9g9sF3od/o1 PMMZmdydHq1chF4Zbbv3hyGMlxdIDRQoHvtRKsKMsMWcf120seebbf0Rz3OKSxqffgdZ AthdX5S3+HQmu/wfmgRVyeGmRxDhjCMjbh4tFALeHnQOZnY/mVFnPWu9S7h1+xw7iHOx zDaUvNbOS+ESsiUDnt5aPLvszk2a2jcCjQOG4PYMI2610sG6oCOXc531+B6R1uWRRkXZ eFaIaRoSnH7PKNHGj0XFjfOI1VATCqaIqOiiDmrKVTT1rfzJlgVefIu59fXo4pdTqaB6 91EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686052717; x=1688644717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2vScY3E4RObHEz5P1xKAaD36hA/8YhvR3M5FwIPwlZU=; b=guaIkBX3blhBX0aD3y2fp0dk5VCbUDBthRBubvqW0dx2GP6DQasbP/Grd+ZHD8VgXY M/itAamB6NcufUKba43wjhIApGKe8BOLNMdEOBD5PTRVJg7t7+9k/LllBMSIDCLyy06N +pLv9kyR31DG47tvLRd1baC0rEEAbeRfBWXmh07MhEOEC6vvDaUdiF+DqtcJoC0tqZ4p YuoD86svIOTB8TCsJHSTcEhIv/2T9w15VjoVM/PkLjY8yPld8iFsr3nOdM8sgvXVTJaF 6CQfHv2ws6H4aw+jYiOQgCRC68bVAF42+TQC5YLKGYnoHvh0jnbRki8RB9CYTsSINhdH 6aJg== X-Gm-Message-State: AC+VfDzL8vOwg8PtRdmqnoWObZQPRPIbEPkd8EE8zKTF+9gBYqE12IfJ ql+VUDee2C3dI4EjbbIrZNwRtHypXwgjTzyR+A== X-Google-Smtp-Source: ACHHUZ6JtzIp1MckXBk9Sidb8LFAo1Mrx14hi0OzRicqigbH0obqArdcceesM0LmEw09UeMHl+eUtg== X-Received: by 2002:a17:902:ecc2:b0:1b0:42d1:ecd0 with SMTP id a2-20020a170902ecc200b001b042d1ecd0mr2424521plh.66.1686052716914; Tue, 06 Jun 2023 04:58:36 -0700 (PDT) Received: from localhost.localdomain ([117.202.186.178]) by smtp.gmail.com with ESMTPSA id b5-20020a170903228500b001acaf7e22bdsm8419226plh.14.2023.06.06.04.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 04:58:36 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/7] PCI: epf-mhi: Make use of the alignment restriction from EPF core Date: Tue, 6 Jun 2023 17:28:09 +0530 Message-Id: <20230606115814.53319-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> References: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Instead of hardcoding the alignment restriction in the EPF_MHI driver, make use of the info available from the EPF core that reflects the alignment restriction of the endpoint controller. For this purpose, let's introduce the get_align_offset() static function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 1227f059ea12..cef866f7d204 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -102,6 +102,11 @@ struct pci_epf_mhi { int irq; }; =20 +static size_t get_align_offset(struct pci_epc *epc, u64 addr) +{ + return addr % epc->mem->window.page_size; +} + static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci= _addr, phys_addr_t *paddr, void __iomem **vaddr, size_t offset, size_t size) @@ -134,7 +139,7 @@ static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *m= hi_cntrl, u64 pci_addr, { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct pci_epc *epc =3D epf_mhi->epf->epc; - size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + size_t offset =3D get_align_offset(epc, pci_addr); =20 return __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr, offset, size); @@ -161,7 +166,7 @@ static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl = *mhi_cntrl, u64 pci_addr, struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct pci_epf *epf =3D epf_mhi->epf; struct pci_epc *epc =3D epf->epc; - size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + size_t offset =3D get_align_offset(epc, pci_addr); =20 __pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset, size); @@ -185,7 +190,8 @@ static int pci_epf_mhi_read_from_host(struct mhi_ep_cnt= rl *mhi_cntrl, u64 from, void *to, size_t size) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); - size_t offset =3D from % SZ_4K; + struct pci_epc *epc =3D epf_mhi->epf->epc; + size_t offset =3D get_align_offset(epc, from); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; @@ -213,7 +219,8 @@ static int pci_epf_mhi_write_to_host(struct mhi_ep_cntr= l *mhi_cntrl, void *from, u64 to, size_t size) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); - size_t offset =3D to % SZ_4K; + struct pci_epc *epc =3D epf_mhi->epf->epc; + size_t offset =3D get_align_offset(epc, to); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 803B4C77B7A for ; Tue, 6 Jun 2023 11:59:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237334AbjFFL7A (ORCPT ); Tue, 6 Jun 2023 07:59:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237119AbjFFL6s (ORCPT ); Tue, 6 Jun 2023 07:58:48 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EC6410FF for ; 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charset="utf-8" Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between PCIe bus and memory. Let's add the support for it by enabling the eDMA IRQ in the driver. Rest of the functionality will be handled by the eDMA DMA Engine driver. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index cd378ce58b22..ea350bb2660d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -74,6 +74,7 @@ #define PARF_INT_ALL_PLS_ERR BIT(15) #define PARF_INT_ALL_PME_LEGACY BIT(16) #define PARF_INT_ALL_PLS_PME BIT(17) +#define PARF_INT_ALL_EDMA BIT(22) =20 /* PARF_BDF_TO_SID_CFG register fields */ #define PARF_BDF_TO_SID_BYPASS BIT(0) @@ -395,7 +396,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); val =3D PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | - PARF_INT_ALL_LINK_UP; + PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); =20 ret =3D dw_pcie_ep_init_complete(&pcie_ep->pci.ep); @@ -744,6 +745,7 @@ static int qcom_pcie_ep_probe(struct platform_device *p= dev) pcie_ep->pci.dev =3D dev; pcie_ep->pci.ops =3D &pci_ops; pcie_ep->pci.ep.ops =3D &pci_ep_ops; + pcie_ep->pci.edma.nr_irqs =3D 1; platform_set_drvdata(pdev, pcie_ep); =20 ret =3D qcom_pcie_ep_get_resources(pdev, pcie_ep); --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2584BC77B73 for ; Tue, 6 Jun 2023 11:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237353AbjFFL7F (ORCPT ); Tue, 6 Jun 2023 07:59:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237323AbjFFL65 (ORCPT ); Tue, 6 Jun 2023 07:58:57 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AD5910E7 for ; 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charset="utf-8" Add support for Embedded DMA (eDMA) available in the Designware PCIe IP to transfer the MHI buffers between host and the endpoint. Use of eDMA helps in achieving greater throughput as the transfers are offloaded from CPUs. For differentiating the iATU and eDMA APIs, the pci_epf_mhi_{read/write} APIs are renamed to pci_epf_mhi_iatu_{read/write} and separate eDMA specific APIs pci_epf_mhi_edma_{read/write} are introduced. Platforms that require eDMA support can pass the MHI_EPF_USE_DMA flag through pci_epf_mhi_ep_info. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 237 ++++++++++++++++++- 1 file changed, 231 insertions(+), 6 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index cef866f7d204..9c93a26ce337 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -6,8 +6,10 @@ * Author: Manivannan Sadhasivam */ =20 +#include #include #include +#include #include #include #include @@ -16,6 +18,9 @@ =20 #define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl) =20 +/* Platform specific flags */ +#define MHI_EPF_USE_DMA BIT(0) + struct pci_epf_mhi_ep_info { const struct mhi_ep_cntrl_config *config; struct pci_epf_header *epf_header; @@ -23,6 +28,7 @@ struct pci_epf_mhi_ep_info { u32 epf_flags; u32 msi_count; u32 mru; + u32 flags; }; =20 #define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \ @@ -98,6 +104,8 @@ struct pci_epf_mhi { struct mutex lock; void __iomem *mmio; resource_size_t mmio_phys; + struct dma_chan *dma_chan_tx; + struct dma_chan *dma_chan_rx; u32 mmio_size; int irq; }; @@ -186,8 +194,8 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *= mhi_cntrl, u32 vector) vector + 1); } =20 -static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 = from, - void *to, size_t size) +static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, + void *to, size_t size) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct pci_epc *epc =3D epf_mhi->epf->epc; @@ -215,8 +223,8 @@ static int pci_epf_mhi_read_from_host(struct mhi_ep_cnt= rl *mhi_cntrl, u64 from, return 0; } =20 -static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, - void *from, u64 to, size_t size) +static int pci_epf_mhi_iatu_write(struct mhi_ep_cntrl *mhi_cntrl, + void *from, u64 to, size_t size) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct pci_epc *epc =3D epf_mhi->epf->epc; @@ -244,6 +252,200 @@ static int pci_epf_mhi_write_to_host(struct mhi_ep_cn= trl *mhi_cntrl, return 0; } =20 +static void pci_epf_mhi_dma_callback(void *param) +{ + complete(param); +} + +static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, + void *to, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan =3D epf_mhi->dma_chan_rx; + struct device *dev =3D &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + dma_cookie_t cookie; + dma_addr_t dst_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction =3D DMA_DEV_TO_MEM; + config.src_addr =3D from; + + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + dst_addr =3D dma_map_single(dma_dev, to, size, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(dma_dev, dst_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc =3D dmaengine_prep_slave_single(chan, dst_addr, size, DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + desc->callback =3D pci_epf_mhi_dma_callback; + desc->callback_param =3D &complete; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret =3D -ETIMEDOUT; + } + +err_unmap: + dma_unmap_single(dma_dev, dst_addr, size, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + +static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, void *fr= om, + u64 to, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan =3D epf_mhi->dma_chan_tx; + struct device *dev =3D &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + dma_cookie_t cookie; + dma_addr_t src_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction =3D DMA_MEM_TO_DEV; + config.dst_addr =3D to; + + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + src_addr =3D dma_map_single(dma_dev, from, size, DMA_TO_DEVICE); + ret =3D dma_mapping_error(dma_dev, src_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc =3D dmaengine_prep_slave_single(chan, src_addr, size, DMA_MEM_TO_DEV, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + desc->callback =3D pci_epf_mhi_dma_callback; + desc->callback_param =3D &complete; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + ret =3D wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret =3D -ETIMEDOUT; + } + +err_unmap: + dma_unmap_single(dma_dev, src_addr, size, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + +struct epf_dma_filter { + struct device *dev; + u32 dma_mask; +}; + +static bool pci_epf_mhi_filter(struct dma_chan *chan, void *node) +{ + struct epf_dma_filter *filter =3D node; + struct dma_slave_caps caps; + + memset(&caps, 0, sizeof(caps)); + dma_get_slave_caps(chan, &caps); + + return chan->device->dev =3D=3D filter->dev && filter->dma_mask & + caps.directions; +} + +static int pci_epf_mhi_dma_init(struct pci_epf_mhi *epf_mhi) +{ + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct device *dev =3D &epf_mhi->epf->dev; + struct epf_dma_filter filter; + dma_cap_mask_t mask; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + filter.dev =3D dma_dev; + filter.dma_mask =3D BIT(DMA_MEM_TO_DEV); + epf_mhi->dma_chan_tx =3D dma_request_channel(mask, pci_epf_mhi_filter, + &filter); + if (IS_ERR_OR_NULL(epf_mhi->dma_chan_tx)) { + dev_err(dev, "Failed to request tx channel\n"); + return -ENODEV; + } + + filter.dma_mask =3D BIT(DMA_DEV_TO_MEM); + epf_mhi->dma_chan_rx =3D dma_request_channel(mask, pci_epf_mhi_filter, + &filter); + if (IS_ERR_OR_NULL(epf_mhi->dma_chan_rx)) { + dev_err(dev, "Failed to request rx channel\n"); + dma_release_channel(epf_mhi->dma_chan_tx); + epf_mhi->dma_chan_tx =3D NULL; + return -ENODEV; + } + + return 0; +} + +static void pci_epf_mhi_dma_deinit(struct pci_epf_mhi *epf_mhi) +{ + dma_release_channel(epf_mhi->dma_chan_tx); + dma_release_channel(epf_mhi->dma_chan_rx); + epf_mhi->dma_chan_tx =3D NULL; + epf_mhi->dma_chan_rx =3D NULL; +} + static int pci_epf_mhi_core_init(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); @@ -289,6 +491,14 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) struct device *dev =3D &epf->dev; int ret; =20 + if (info->flags & MHI_EPF_USE_DMA) { + ret =3D pci_epf_mhi_dma_init(epf_mhi); + if (ret) { + dev_err(dev, "Failed to initialize DMA: %d\n", ret); + return ret; + } + } + mhi_cntrl->mmio =3D epf_mhi->mmio; mhi_cntrl->irq =3D epf_mhi->irq; mhi_cntrl->mru =3D info->mru; @@ -298,13 +508,20 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->raise_irq =3D pci_epf_mhi_raise_irq; mhi_cntrl->alloc_map =3D pci_epf_mhi_alloc_map; mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; - mhi_cntrl->read_from_host =3D pci_epf_mhi_read_from_host; - mhi_cntrl->write_to_host =3D pci_epf_mhi_write_to_host; + if (info->flags & MHI_EPF_USE_DMA) { + mhi_cntrl->read_from_host =3D pci_epf_mhi_edma_read; + mhi_cntrl->write_to_host =3D pci_epf_mhi_edma_write; + } else { + mhi_cntrl->read_from_host =3D pci_epf_mhi_iatu_read; + mhi_cntrl->write_to_host =3D pci_epf_mhi_iatu_write; + } =20 /* Register the MHI EP controller */ ret =3D mhi_ep_register_controller(mhi_cntrl, info->config); if (ret) { dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); return ret; } =20 @@ -314,10 +531,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) static int pci_epf_mhi_link_down(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; =20 if (mhi_cntrl->mhi_dev) { mhi_ep_power_down(mhi_cntrl); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } =20 @@ -327,6 +547,7 @@ static int pci_epf_mhi_link_down(struct pci_epf *epf) static int pci_epf_mhi_bme(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; struct device *dev =3D &epf->dev; int ret; @@ -339,6 +560,8 @@ static int pci_epf_mhi_bme(struct pci_epf *epf) ret =3D mhi_ep_power_up(mhi_cntrl); if (ret) { dev_err(dev, "Failed to power up MHI EP: %d\n", ret); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } } @@ -391,6 +614,8 @@ static void pci_epf_mhi_unbind(struct pci_epf *epf) */ if (mhi_cntrl->mhi_dev) { mhi_ep_power_down(mhi_cntrl); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } =20 --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C12BC7EE2F for ; Tue, 6 Jun 2023 11:59:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237445AbjFFL7L (ORCPT ); Tue, 6 Jun 2023 07:59:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237301AbjFFL7B (ORCPT ); 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Tue, 06 Jun 2023 04:58:47 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/7] PCI: epf-mhi: Add support for SM8450 Date: Tue, 6 Jun 2023 17:28:12 +0530 Message-Id: <20230606115814.53319-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> References: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for Qualcomm Snapdragon SM8450 SoC to the EPF driver. SM8450 has the dedicated PID (0x0306) and supports eDMA. Currently, it has no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 22 +++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 9c93a26ce337..f4d1d60bde56 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -97,6 +97,23 @@ static const struct pci_epf_mhi_ep_info sdx55_info =3D { .mru =3D 0x8000, }; =20 +static struct pci_epf_header sm8450_header =3D { + .vendorid =3D PCI_VENDOR_ID_QCOM, + .deviceid =3D 0x0306, + .baseclass_code =3D PCI_CLASS_OTHERS, + .interrupt_pin =3D PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sm8450_info =3D { + .config =3D &mhi_v1_config, + .epf_header =3D &sm8450_header, + .bar_num =3D BAR_0, + .epf_flags =3D PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count =3D 32, + .mru =3D 0x8000, + .flags =3D MHI_EPF_USE_DMA, +}; + struct pci_epf_mhi { const struct pci_epf_mhi_ep_info *info; struct mhi_ep_cntrl mhi_cntrl; @@ -656,9 +673,8 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, } =20 static const struct pci_epf_device_id pci_epf_mhi_ids[] =3D { - { - .name =3D "sdx55", .driver_data =3D (kernel_ulong_t)&sdx55_info, - }, + { .name =3D "sdx55", .driver_data =3D (kernel_ulong_t)&sdx55_info }, + { .name =3D "sm8450", .driver_data =3D (kernel_ulong_t)&sm8450_info }, {}, }; =20 --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D79FC77B73 for ; Tue, 6 Jun 2023 11:59:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237323AbjFFL7V (ORCPT ); Tue, 6 Jun 2023 07:59:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237404AbjFFL7G (ORCPT ); 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Tue, 06 Jun 2023 04:58:51 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 6/7] PCI: epf-mhi: Use iATU for small transfers Date: Tue, 6 Jun 2023 17:28:13 +0530 Message-Id: <20230606115814.53319-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> References: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For transfers below 4K, let's use iATU since using eDMA for such small transfers is not efficient. This is mainly due to the fact that setting up a eDMA transfer and waiting for its completion adds some latency. This latency is negligible for large transfers but not for the smaller ones. With this hack, there is an increase in ~50Mbps throughput on both MHI UL (Uplink) and DL (Downlink) channels. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index f4d1d60bde56..94cf68bdd235 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -288,6 +288,9 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *m= hi_cntrl, u64 from, dma_addr_t dst_addr; int ret; =20 + if (size < SZ_4K) + return pci_epf_mhi_iatu_read(mhi_cntrl, from, to, size); + mutex_lock(&epf_mhi->lock); =20 config.direction =3D DMA_DEV_TO_MEM; @@ -354,6 +357,9 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *= mhi_cntrl, void *from, dma_addr_t src_addr; int ret; =20 + if (size < SZ_4K) + return pci_epf_mhi_iatu_write(mhi_cntrl, from, to, size); + mutex_lock(&epf_mhi->lock); =20 config.direction =3D DMA_MEM_TO_DEV; --=20 2.25.1 From nobody Mon Feb 9 09:46:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1775EC7EE24 for ; Tue, 6 Jun 2023 11:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237469AbjFFL73 (ORCPT ); Tue, 6 Jun 2023 07:59:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237446AbjFFL7N (ORCPT ); Tue, 6 Jun 2023 07:59:13 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 068801731 for ; Tue, 6 Jun 2023 04:58:55 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-528cdc9576cso3101393a12.0 for ; Tue, 06 Jun 2023 04:58:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686052735; x=1688644735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cRwHHVBuwFdTSPfIU1R1ZLyGoM8LybFGSYGhuRMiUuk=; b=GDNQ0tGgu2Z5y8Mf/D9JPoPQwu4ld0v9cyfkpZJS5csZsulT3j35QseR+SsQnfTBQC xOCAQh5Z7tFWRC0ztLdPhOS7aGuPg+3nb50IMfsVjzmLOOr0oSfNHvA58qaJpp69HbY0 ADuxzsTs2X4H/XZiXmTOr+s3/g+tWoAv5AunAx5Xkeqr0EwRRVddE2H1ykfRmy02eAiR kJ13TIm1dKH9TOloLhbQfqkeW1tq9tdVMTilRVH+vbqZPjlf8bOtU0I4peE4pbz9u3EP sTkXNWr+h35oehx9f7j1eiwU3AXVzAK6JGNhNjqjkNUBbyX/MndA38mtAc8VBx1n4vEb gPNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686052735; x=1688644735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cRwHHVBuwFdTSPfIU1R1ZLyGoM8LybFGSYGhuRMiUuk=; b=iPHhvnwV8d2tLAcarrsKHd29SC11rF99NVVL/C4sd2ohLQct3uwgMvG8Mtm95t0JQ0 Dphn7Sihi9N+6heikoFmbhR980Fdgtd1i0K2Tqxz3/G6Z+vhrXKaL4foo8Ci1MNbrOob OOPuzKFz9rlc5je1VG5kI5ogXTWexBjD0Ut3fMvUMwQXbk98g6Ny9kkGl7lauv+b9WYK 0KoLhIuAsWIUH7h48WL/8i2cHtPaVMAdC1R+WgJz2eIUK0jnJt9WIkJvIKkYPlP/6gRF BUrNFxuxqZezSh9mMEIOhI9ijhv+PVfadAbIJBAYuBp10oO4qorstCoLyMpdnfw9QNV+ mLjA== X-Gm-Message-State: AC+VfDwHNT6rFP8Xs7ow2hRDk+Zby2yvUXctpxunU1tGywpRIijojTr+ 7SqHd9kHZ9hkFj2oH3OjD8Pp X-Google-Smtp-Source: ACHHUZ4TaSeSgHzzlmzlfHDYxu6B/XdzkWmcSINkszkmDj0Di2XG9vgw4fFsdMUTnnzkxAr8YBTiSw== X-Received: by 2002:a17:902:7d98:b0:1a6:b971:faf6 with SMTP id a24-20020a1709027d9800b001a6b971faf6mr853968plm.35.1686052735442; Tue, 06 Jun 2023 04:58:55 -0700 (PDT) Received: from localhost.localdomain ([117.202.186.178]) by smtp.gmail.com with ESMTPSA id b5-20020a170903228500b001acaf7e22bdsm8419226plh.14.2023.06.06.04.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jun 2023 04:58:55 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 7/7] PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API Date: Tue, 6 Jun 2023 17:28:14 +0530 Message-Id: <20230606115814.53319-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> References: <20230606115814.53319-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add missing kernel-doc for pci_epc_mem_init() API. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-mem.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-= epc-mem.c index 7dcf6f480b82..a9c028f58da1 100644 --- a/drivers/pci/endpoint/pci-epc-mem.c +++ b/drivers/pci/endpoint/pci-epc-mem.c @@ -115,6 +115,16 @@ int pci_epc_multi_mem_init(struct pci_epc *epc, } EXPORT_SYMBOL_GPL(pci_epc_multi_mem_init); =20 +/** + * pci_epc_mem_init() - Initialize the pci_epc_mem structure + * @epc: the EPC device that invoked pci_epc_mem_init + * @base: Physical address of the window region + * @size: Total Size of the window region + * @page_size: Page size of the window region + * + * Invoke to initialize a single pci_epc_mem structure used by the + * endpoint functions to allocate memory for mapping the PCI host memory + */ int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base, size_t size, size_t page_size) { --=20 2.25.1