From nobody Sat Sep 21 00:47:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F387BC7EE24 for ; Mon, 5 Jun 2023 16:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230459AbjFEQVv (ORCPT ); Mon, 5 Jun 2023 12:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234903AbjFEQVk (ORCPT ); Mon, 5 Jun 2023 12:21:40 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFB11E9; Mon, 5 Jun 2023 09:21:39 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id AED526606E75; Mon, 5 Jun 2023 17:21:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982098; bh=eYWIdhW4aakZCc9KT/m2mXuoGNz20gM45H5p6PtQfaA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nyshmm6ObK9GxFVtiLunGY3XtIz9xexeLx/ePQwXglIhayFfZxi3sM4omcgO83LkK fIDCGlZexBM8iCi/9LZzmQHh/n+AGsC7CzWquCziocDuPiZZleX36sbD7So7qKe6U2 a14M9u+sY45vC2QNBgNfu1hIRjVXzcX9WuJEqKkRqHjtc2TtAd0H6LRC8JTsQsIE8q cIkHLvz4hxBdmrO6i8M3nl0Xhn5OA7N0BSypRMas2Siw2oDLjQBnYvYyiRU5zEVv84 lI1f2ImGC2qDbLdOsfIYKM4T8usjS4EZIxQU0k7MtKHkDa0EDYtymStIrURM8vbprx Z5zoOPbPdaCfA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Yunfei Dong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 6/6] arm64: dts: mediatek: mt8183: Add decoder Date: Mon, 5 Jun 2023 12:20:30 -0400 Message-Id: <20230605162030.274395-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..8bb10ed67e87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,45 @@ vdecsys: syscon@16000000 { #clock-cells =3D <1>; }; =20 + vcodec_dec: video-codec@16020000 { + compatible =3D "mediatek,mt8183-vcodec-dec"; + reg =3D <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names =3D "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg"; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp =3D <&scp>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks =3D <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_ACTIVE>; + clock-names =3D "vdec", "active"; + }; + larb1: larb@16010000 { compatible =3D "mediatek,mt8183-smi-larb"; reg =3D <0 0x16010000 0 0x1000>; --=20 2.40.1