From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28996C77B73 for ; Mon, 5 Jun 2023 16:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234700AbjFEQVc (ORCPT ); Mon, 5 Jun 2023 12:21:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232988AbjFEQV1 (ORCPT ); Mon, 5 Jun 2023 12:21:27 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C38BC94; Mon, 5 Jun 2023 09:21:26 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 51F236605840; Mon, 5 Jun 2023 17:21:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982085; bh=ATz/rOCQK/30QpZGojesEllhUcbCxgG6yCEU3vGr3XY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AUdKxlsBSpoteFxUFwz5M/rh+iK0lAMHfnQTu9vVSa4MmYwD6UIW5J5kdH0UOcKgV mvA2puSQ0KrQXzt5QqpYefEbBoCXtb7uDrINRj04CEaAhKMbAK4x0APzlEQosIthFO IkPpQg0xlMHsty2D/qCp/RiT2TMETjYZx9Xq0DZvTVvHpSQqV84kGen81Pi12dowNW 3aSyP8DCPv+l6yFbb8F3jEjQRw7SxSoKxS8LxvtqBZSf2E5QoLf1mdmh0RkdgQqhSj j7iiRiozlSOjqzgGAaG584JoRxZWKDfvigsFB1RJtxqomAXNWlxf0A03GYRo5I7Asd rhlHlpNqKK3ng== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/6] media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183 Date: Mon, 5 Jun 2023 12:20:25 -0400 Message-Id: <20230605162030.274395-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org MT8173 and MT8183 have different clocks, and consequently clock-names. Relax the number of clocks and set clock-names based on compatible. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../media/mediatek,vcodec-decoder.yaml | 29 +++++++++++++------ 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index fad59b486d5d..57d5ca776df0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -27,18 +27,12 @@ properties: maxItems: 1 =20 clocks: + minItems: 1 maxItems: 8 =20 clock-names: - items: - - const: vcodecpll - - const: univpll_d2 - - const: clk_cci400_sel - - const: vdec_sel - - const: vdecpll - - const: vencpll - - const: venc_lt_sel - - const: vdec_bus_clk_src + minItems: 1 + maxItems: 8 =20 assigned-clocks: true =20 @@ -88,6 +82,11 @@ allOf: required: - mediatek,scp =20 + properties: + clock-names: + items: + - const: vdec + - if: properties: compatible: @@ -99,6 +98,18 @@ allOf: required: - mediatek,vpu =20 + properties: + clock-names: + items: + - const: vcodecpll + - const: univpll_d2 + - const: clk_cci400_sel + - const: vdec_sel + - const: vdecpll + - const: vencpll + - const: venc_lt_sel + - const: vdec_bus_clk_src + additionalProperties: false =20 examples: --=20 2.40.1 From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CE3BC7EE32 for ; Mon, 5 Jun 2023 16:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234902AbjFEQVi (ORCPT ); Mon, 5 Jun 2023 12:21:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234656AbjFEQVb (ORCPT ); Mon, 5 Jun 2023 12:21:31 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE58ED2; Mon, 5 Jun 2023 09:21:29 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1A5546606E75; Mon, 5 Jun 2023 17:21:25 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982088; bh=hpuSfUwRgpVJ50aSOdpyF/fGgsKVyjO2zFPFVOsBbR0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BgQDAyVS5lY/HAGajbGzPNci3f/nLj+mgvCtY43vmi5C9uwzdn2auEh89rl5U8v8q utcPbqNSWLqK+JOYWVOlqIjKlNv9bxM8NLsVsVvNpJz/VTXna3jpHGahFBkLC1Sg9T 0SWxfgZUWDlpGgs2Io83WC1quPUMN5s8Zusxmf+SK9CCKViMAPhOKeihx878HP08KF 2PvcDGUk0Dj9NN3jCfSxfvvg35DnM0Y9qQDtCOhYOlnQvw9Ghy2aC3U5cegPItOzk3 PfkX5gjsNAdq7EZHBLQr2vPp6a/Ziqilm6GsOkrXXBWwuee9x+BGu6Jtx6L625t73i gjpT4MdgQ5fLg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 2/6] media: dt-bindings: mediatek,vcodec: Don't require assigned-clocks Date: Mon, 5 Jun 2023 12:20:26 -0400 Message-Id: <20230605162030.274395-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On MT8183 it's not necessary to configure the parent for the clocks. Remove the assigned-clocks and assigned-clock-parents from the required list. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Reviewed-by: Matthias Brugger --- .../devicetree/bindings/media/mediatek,vcodec-decoder.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index 57d5ca776df0..6447e6c86f29 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -67,8 +67,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents =20 allOf: - if: --=20 2.40.1 From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42954C7EE24 for ; Mon, 5 Jun 2023 16:21:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234911AbjFEQVm (ORCPT ); Mon, 5 Jun 2023 12:21:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234668AbjFEQVd (ORCPT ); Mon, 5 Jun 2023 12:21:33 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B131EA; Mon, 5 Jun 2023 09:21:32 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id DB2896606E8F; Mon, 5 Jun 2023 17:21:28 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982091; bh=FBxkyNk+wH42mt6PnhdzeId5YI52PJ33/87A7v+PAUw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WjIsU6PBPQljs3cQ78Cgl3WM66ZSuCLbOq5VIHZioKLnkOeABvFutQ6grd6TD3vk6 xwjYiWrpsAji/CfOAUSGybbUcMMOXplj4rqdJ8sfCb6ffrbnirCMI4MerrgFD5jKjw R6GPE3W/yPlYSYJhRtYvny8+cT/IM43tkOB7k/mbchRqjvZbU6fniXBFC2XIwEhrHE 2xGvvoWP/OfQ38BUzu45bjim1SUxYND4Ka1yH7NRYhoFlKsjwZ+N0c7iHMES046Aj+ jWOHzBtjIcCfJkrOBXTCJg/plkgykkiy98zFO2JDGnocRCaCYWozJwBeyI8FxUjZCQ 294Sym1jSsP5Q== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 3/6] media: dt-bindings: mediatek,vcodec: Remove VDEC_SYS for mt8183 Date: Mon, 5 Jun 2023 12:20:27 -0400 Message-Id: <20230605162030.274395-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The binding expects the first register space to be VDEC_SYS. But on mt8183, which uses the stateless decoders, this space is used only for controlling clocks and resets, which are better described as separate clock-controller and reset-controller nodes. In fact, in mt8173's devicetree there are already such separate clock-controller nodes, which cause duplicate addresses between the vdecsys node and the vcodec node. But for this SoC, since the stateful decoder code makes other uses of the VDEC_SYS register space, it's not straightforward to remove it. In order to avoid the same address conflict to happen on mt8183, since the only current use of the VDEC_SYS register space in the driver is to read the status of a clock that indicates the hardware is active, remove the VDEC_SYS register space from the binding and describe an extra clock that will be used to directly check the hardware status. Also add reg-names to be able to tell that this new register schema is used, so the driver can keep backward compatibility. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- .../media/mediatek,vcodec-decoder.yaml | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decode= r.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.ya= ml index 6447e6c86f29..36a53b2484d6 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -21,17 +21,21 @@ properties: - mediatek,mt8183-vcodec-dec =20 reg: + minItems: 11 maxItems: 12 =20 + reg-names: + minItems: 11 + interrupts: maxItems: 1 =20 clocks: - minItems: 1 + minItems: 2 maxItems: 8 =20 clock-names: - minItems: 1 + minItems: 2 maxItems: 8 =20 assigned-clocks: true @@ -84,6 +88,24 @@ allOf: clock-names: items: - const: vdec + - const: active + + reg: + maxItems: 11 + + reg-names: + items: + - const: misc + - const: ld + - const: top + - const: cm + - const: ad + - const: av + - const: pp + - const: hwd + - const: hwq + - const: hwb + - const: hwg =20 - if: properties: @@ -108,6 +130,9 @@ allOf: - const: venc_lt_sel - const: vdec_bus_clk_src =20 + reg: + minItems: 12 + additionalProperties: false =20 examples: --=20 2.40.1 From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC2DDC7EE24 for ; Mon, 5 Jun 2023 16:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjFEQVp (ORCPT ); Mon, 5 Jun 2023 12:21:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234801AbjFEQVg (ORCPT ); Mon, 5 Jun 2023 12:21:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB8FDE6; Mon, 5 Jun 2023 09:21:34 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id A1C676605840; Mon, 5 Jun 2023 17:21:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982093; bh=LS7cN4RBxcl8sllo4Y3gVv2KC3BFqrCKLyuDQi01anc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dFrp470exFqNjDXip/2dVacgLH8+NGfi6s9aOb5c3Xd/NNA2cniQpYP6pqD4WvWKz 0UeBz67010w+WI7BcBKabhyDmxWIJrmk8wTInHuRzsk8rjLIkquECK3izIa+Y7ole+ V4JzirlMIqyy8T0fhbdZ31B0lQ+SnJPwtQAGfH7cAYDbS1A1dqn1Vljp7bZm0IwZ2U HEzTbNfYVLq5t59SelN2UnuxqtNwX4bDa05a8t0U1Hl2UzPOTioEBY4SQuvcSDB6J7 h1SeQ8BLKUhIixTN8IBiSGzadB3OxHB+tnl1c0JGx2zBWPBgUrsm0H1j6d6gkofwU9 Gi6owjuw6kdOg== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Andrew-CT Chen , Mauro Carvalho Chehab , Tiffany Lin , Yunfei Dong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/6] media: mediatek: vcodec: Read HW active status from clock Date: Mon, 5 Jun 2023 12:20:28 -0400 Message-Id: <20230605162030.274395-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove the requirement of a VDEC_SYS reg iospace. To achieve that, rely on the "active" clock being passed through the DT, and read its status during IRQ handling to check whether the HW is active. The old behavior is still present when reg-names aren't supplied, as to keep backward compatibility. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 59 +++++++++++++++---- .../mediatek/vcodec/mtk_vcodec_dec_hw.c | 20 +++++-- .../mediatek/vcodec/mtk_vcodec_dec_pm.c | 12 +++- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + 4 files changed, 74 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index 9c652beb3f19..8038472fb67b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #include "mtk_vcodec_drv.h" #include "mtk_vcodec_dec.h" @@ -38,22 +39,29 @@ static int mtk_vcodec_get_hw_count(struct mtk_vcodec_de= v *dev) } } =20 +static bool mtk_vcodec_is_hw_active(struct mtk_vcodec_dev *dev) +{ + u32 cg_status =3D 0; + + if (!dev->reg_base[VDEC_SYS]) + return __clk_is_enabled(dev->pm.vdec_active_clk); + + cg_status =3D readl(dev->reg_base[VDEC_SYS]); + return (cg_status & VDEC_HW_ACTIVE) =3D=3D 0; +} + static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) { struct mtk_vcodec_dev *dev =3D priv; struct mtk_vcodec_ctx *ctx; - u32 cg_status =3D 0; unsigned int dec_done_status =3D 0; void __iomem *vdec_misc_addr =3D dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG; =20 ctx =3D mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); =20 - /* check if HW active or not */ - cg_status =3D readl(dev->reg_base[0]); - if ((cg_status & VDEC_HW_ACTIVE) !=3D 0) { - mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)", - cg_status); + if (!mtk_vcodec_is_hw_active(dev)) { + mtk_v4l2_err("DEC ISR, VDEC active is not 0x0"); return IRQ_HANDLED; } =20 @@ -82,6 +90,25 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_de= v *dev) { struct platform_device *pdev =3D dev->plat_dev; int reg_num, i; + struct resource *res; + bool no_vdecsys_reg =3D false; + static const char * const mtk_dec_reg_names[] =3D { + "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg" + }; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "misc"); + if (res) + no_vdecsys_reg =3D true; =20 /* Sizeof(u32) * 4 bytes for each register base. */ reg_num =3D of_property_count_elems_of_size(pdev->dev.of_node, "reg", @@ -91,12 +118,22 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_= dev *dev) return -EINVAL; } =20 - for (i =3D 0; i < reg_num; i++) { - dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); - if (IS_ERR(dev->reg_base[i])) - return PTR_ERR(dev->reg_base[i]); + if (!no_vdecsys_reg) { + for (i =3D 0; i < reg_num; i++) { + dev->reg_base[i] =3D devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(dev->reg_base[i])) + return PTR_ERR(dev->reg_base[i]); =20 - mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); + mtk_v4l2_debug(2, "reg[%d] base=3D%p", i, dev->reg_base[i]); + } + } else { + for (i =3D 0; i < reg_num; i++) { + dev->reg_base[i+1] =3D devm_platform_ioremap_resource_byname(pdev, mtk_= dec_reg_names[i]); + if (IS_ERR(dev->reg_base[i+1])) + return PTR_ERR(dev->reg_base[i+1]); + + mtk_v4l2_debug(2, "reg[%d] base=3D%p", i+1, dev->reg_base[i+1]); + } } =20 return 0; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c index b753bf54ebd9..4e786821015d 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "mtk_vcodec_drv.h" #include "mtk_vcodec_dec.h" @@ -63,22 +64,29 @@ static int mtk_vdec_hw_prob_done(struct mtk_vcodec_dev = *vdec_dev) return 0; } =20 +static bool mtk_vcodec_is_hw_active(struct mtk_vdec_hw_dev *dev) +{ + u32 cg_status; + + if (!dev->reg_base[VDEC_HW_SYS]) + return __clk_is_enabled(dev->pm.vdec_active_clk); + + cg_status =3D readl(dev->reg_base[VDEC_HW_SYS]); + return (cg_status & VDEC_HW_ACTIVE) =3D=3D 0; +} + static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv) { struct mtk_vdec_hw_dev *dev =3D priv; struct mtk_vcodec_ctx *ctx; - u32 cg_status; unsigned int dec_done_status; void __iomem *vdec_misc_addr =3D dev->reg_base[VDEC_HW_MISC] + VDEC_IRQ_CFG_REG; =20 ctx =3D mtk_vcodec_get_curr_ctx(dev->main_dev, dev->hw_idx); =20 - /* check if HW active or not */ - cg_status =3D readl(dev->reg_base[VDEC_HW_SYS]); - if (cg_status & VDEC_HW_ACTIVE) { - mtk_v4l2_err("vdec active is not 0x0 (0x%08x)", - cg_status); + if (!mtk_vcodec_is_hw_active(dev)) { + mtk_v4l2_err("vdec active is not 0x0"); return IRQ_HANDLED; } =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c index 777d445999e9..53e621965950 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c @@ -51,6 +51,9 @@ int mtk_vcodec_init_dec_clk(struct platform_device *pdev,= struct mtk_vcodec_pm * clk_info->clk_name); return PTR_ERR(clk_info->vcodec_clk); } + + if (strcmp(clk_info->clk_name, "active") =3D=3D 0) + pm->vdec_active_clk =3D clk_info->vcodec_clk; } =20 return 0; @@ -84,6 +87,9 @@ static void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm = *pm) =20 dec_clk =3D &pm->vdec_clk; for (i =3D 0; i < dec_clk->clk_num; i++) { + if (strcmp(dec_clk->clk_info[i].clk_name, "active") =3D=3D 0) + continue; + ret =3D clk_prepare_enable(dec_clk->clk_info[i].vcodec_clk); if (ret) { mtk_v4l2_err("clk_prepare_enable %d %s fail %d", i, @@ -104,8 +110,12 @@ static void mtk_vcodec_dec_clock_off(struct mtk_vcodec= _pm *pm) int i; =20 dec_clk =3D &pm->vdec_clk; - for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) + for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) { + if (strcmp(dec_clk->clk_info[i].clk_name, "active") =3D=3D 0) + continue; + clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); + } } =20 static void mtk_vcodec_dec_enable_irq(struct mtk_vcodec_dev *vdec_dev, int= hw_idx) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 9acab54fd650..180e74c69042 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -208,6 +208,7 @@ struct mtk_vcodec_pm { struct mtk_vcodec_clk vdec_clk; struct mtk_vcodec_clk venc_clk; struct device *dev; + struct clk *vdec_active_clk; }; =20 /** --=20 2.40.1 From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B83BC7EE2C for ; Mon, 5 Jun 2023 16:21:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230380AbjFEQVs (ORCPT ); Mon, 5 Jun 2023 12:21:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232988AbjFEQVi (ORCPT ); Mon, 5 Jun 2023 12:21:38 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 698EC106; Mon, 5 Jun 2023 09:21:37 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id E67D26602242; Mon, 5 Jun 2023 17:21:33 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982096; bh=0r6cQNK3uGc3pJiztNyfHAD9LI2rH/+twn3IcKzXoIo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V4JpGvCB73IwzBPjm0YatoVY3mRol/XEoRAZ3+D1ASiZxJth7e6ICWfWJeqBWhimK BcLbtD6U02KToCRPB6XzmesJlXIS/Bt+u6XO1cnk9kZk2hWb/eHHFYuKyi5Wv5T55I MSiybdyFVOttuRwEafHjMNlGmffYoW0qo6JWIpPRPJoxAa1XhLwHnQcGQ+3Vi/7Ssn M02O2owhQXpJCltgx4O1yvn8hJ6vzkJjNqVR+5JccMrpLw2v/DHhr3w78kjHFm/pPU 2IKG13naY6jadkBvhkwOxpqvKNoUP8NnUZKrkymSyF+rRzOStH1OucJWsyLdIn5bL3 Y2Yd5t9Hi0zAw== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= , Chen-Yu Tsai , Conor Dooley , Krzysztof Kozlowski , Michael Turquette , Miles Chen , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 5/6] clk: mediatek: mt8183: Add CLK_VDEC_ACTIVE to vdec Date: Mon, 5 Jun 2023 12:20:29 -0400 Message-Id: <20230605162030.274395-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the CLK_VDEC_ACTIVE clock to the vdec clock driver. This clock is enabled by the VPU once it starts decoding. Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/clk/mediatek/clk-mt8183-vdec.c | 5 +++++ include/dt-bindings/clock/mt8183-clk.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8183-vdec.c b/drivers/clk/mediatek/= clk-mt8183-vdec.c index 513b7956cbea..5830934a6d25 100644 --- a/drivers/clk/mediatek/clk-mt8183-vdec.c +++ b/drivers/clk/mediatek/clk-mt8183-vdec.c @@ -27,6 +27,10 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \ &mtk_clk_gate_ops_setclr_inv) =20 +#define GATE_VDEC0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr) + #define GATE_VDEC1_I(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \ &mtk_clk_gate_ops_setclr_inv) @@ -34,6 +38,7 @@ static const struct mtk_gate_regs vdec1_cg_regs =3D { static const struct mtk_gate vdec_clks[] =3D { /* VDEC0 */ GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_vdec", "mm_sel", 0), + GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "mm_sel", 4), /* VDEC1 */ GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1", "mm_sel", 0), }; diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/c= lock/mt8183-clk.h index a7b470b0ec8a..32dd7d91dbe2 100644 --- a/include/dt-bindings/clock/mt8183-clk.h +++ b/include/dt-bindings/clock/mt8183-clk.h @@ -357,7 +357,8 @@ /* VDEC_GCON */ #define CLK_VDEC_VDEC 0 #define CLK_VDEC_LARB1 1 -#define CLK_VDEC_NR_CLK 2 +#define CLK_VDEC_ACTIVE 2 +#define CLK_VDEC_NR_CLK 3 =20 /* VENC_GCON */ #define CLK_VENC_LARB 0 --=20 2.40.1 From nobody Fri Sep 20 18:44:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F387BC7EE24 for ; Mon, 5 Jun 2023 16:21:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230459AbjFEQVv (ORCPT ); Mon, 5 Jun 2023 12:21:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234903AbjFEQVk (ORCPT ); Mon, 5 Jun 2023 12:21:40 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFB11E9; Mon, 5 Jun 2023 09:21:39 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id AED526606E75; Mon, 5 Jun 2023 17:21:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685982098; bh=eYWIdhW4aakZCc9KT/m2mXuoGNz20gM45H5p6PtQfaA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Nyshmm6ObK9GxFVtiLunGY3XtIz9xexeLx/ePQwXglIhayFfZxi3sM4omcgO83LkK fIDCGlZexBM8iCi/9LZzmQHh/n+AGsC7CzWquCziocDuPiZZleX36sbD7So7qKe6U2 a14M9u+sY45vC2QNBgNfu1hIRjVXzcX9WuJEqKkRqHjtc2TtAd0H6LRC8JTsQsIE8q cIkHLvz4hxBdmrO6i8M3nl0Xhn5OA7N0BSypRMas2Siw2oDLjQBnYvYyiRU5zEVv84 lI1f2ImGC2qDbLdOsfIYKM4T8usjS4EZIxQU0k7MtKHkDa0EDYtymStIrURM8vbprx Z5zoOPbPdaCfA== From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Yunfei Dong , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH 6/6] arm64: dts: mediatek: mt8183: Add decoder Date: Mon, 5 Jun 2023 12:20:30 -0400 Message-Id: <20230605162030.274395-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230605162030.274395-1-nfraprado@collabora.com> References: <20230605162030.274395-1-nfraprado@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: N=C3=ADcolas F. R. A. Prado --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 5169779d01df..8bb10ed67e87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,45 @@ vdecsys: syscon@16000000 { #clock-cells =3D <1>; }; =20 + vcodec_dec: video-codec@16020000 { + compatible =3D "mediatek,mt8183-vcodec-dec"; + reg =3D <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names =3D "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg"; + interrupts =3D ; + iommus =3D <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp =3D <&scp>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks =3D <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_ACTIVE>; + clock-names =3D "vdec", "active"; + }; + larb1: larb@16010000 { compatible =3D "mediatek,mt8183-smi-larb"; reg =3D <0 0x16010000 0 0x1000>; --=20 2.40.1