From nobody Sun Feb 8 14:56:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77E5DC7EE23 for ; Mon, 5 Jun 2023 11:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231829AbjFELFE (ORCPT ); Mon, 5 Jun 2023 07:05:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231578AbjFELFB (ORCPT ); Mon, 5 Jun 2023 07:05:01 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F0A5F2; Mon, 5 Jun 2023 04:04:59 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 355B4lvN008502; Mon, 5 Jun 2023 06:04:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685963087; bh=ZgUYvyiKVgnOmW4p//WF3VcF42d3FC8Xm2zYqVM7i28=; h=From:To:CC:Subject:Date; b=UAW7cTULI4+z6p4wQnd8oTCXKUQGppslINJup18ncMrK3otzWMxs1rJw0Su9anl/L Eot1l7NmGZdm9OXze81iC3lfJ5OHolQg65iUHp69nvi3lARpvRasPV4Q5YCJJLzltG mQ+NqpOQj/UcpftIOlekvVyF5Cpu7idKSDxHUIII= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 355B4lUq114003 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 5 Jun 2023 06:04:47 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 5 Jun 2023 06:04:47 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 5 Jun 2023 06:04:47 -0500 Received: from ula0497641.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 355B4ieT111266; Mon, 5 Jun 2023 06:04:44 -0500 From: Neha Malcom Francis To: , , , , , CC: , , , Subject: [PATCH] arm64: dts: ti: k3-j721s2: Change CPTS clock parent Date: Mon, 5 Jun 2023 16:34:43 +0530 Message-ID: <20230605110443.84568-1-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's capability to re-initialise clock frequencies. CPTS and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs this reinitialisation to default frequency to be able to get 250MHz with its divider, CPTS can not get its required 200MHz with its divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side for the same reason) Signed-off-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..331e0c9b4db8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -738,6 +738,8 @@ cpts@310d0000 { reg-names =3D "cpts"; clocks =3D <&k3_clks 226 5>; clock-names =3D "cpts"; + assigned-clocks =3D <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents =3D <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended =3D <&main_navss_intr 391>; interrupt-names =3D "cpts"; ti,cpts-periodic-outputs =3D <6>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..b55a3e9daf85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -333,6 +333,8 @@ cpts@3d000 { reg =3D <0x0 0x3d000 0x0 0x400>; clocks =3D <&k3_clks 29 3>; clock-names =3D "cpts"; + assigned-clocks =3D <&k3_clks 29 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents =3D <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended =3D <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names =3D "cpts"; ti,cpts-ext-ts-inputs =3D <4>; --=20 2.34.1