From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F172C77B7A for ; Sat, 3 Jun 2023 20:03:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229724AbjFCUD2 (ORCPT ); Sat, 3 Jun 2023 16:03:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229692AbjFCUDZ (ORCPT ); Sat, 3 Jun 2023 16:03:25 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D51471B7; Sat, 3 Jun 2023 13:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822602; x=1717358602; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Sat, 3 Jun 2023 13:03:08 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible Date: Sun, 4 Jun 2023 01:32:23 +0530 Message-ID: <20230603200243.243878-2-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add sam9x60 compatible string support in the schema file Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm92= 00-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9= 200-tcb.yaml index a46411149571..c70c77a5e8e5 100644 --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.= yaml +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.= yaml @@ -20,6 +20,7 @@ properties: - atmel,at91rm9200-tcb - atmel,at91sam9x5-tcb - atmel,sama5d2-tcb + - microchip,sam9x60-tcb - const: simple-mfd - const: syscon =20 --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB2BFC7EE2D for ; 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charset="utf-8" Document at91sam9g45-ehci compatible for usb-ehci Signed-off-by: Varshini Rajendran Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index 9445764bd8de..7e486cc6cfb8 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -66,6 +66,7 @@ properties: - const: generic-ehci - items: - enum: + - atmel,at91sam9g45-ehci - cavium,octeon-6335-ehci - ibm,usb-ehci-440epx - ibm,usb-ehci-460ex --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DEEDC7EE2E for ; Sat, 3 Jun 2023 20:04:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229794AbjFCUEF (ORCPT ); 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X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="155388242" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:03:48 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:03:46 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:03:34 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property Date: Sun, 4 Jun 2023 01:32:25 +0530 Message-ID: <20230603200243.243878-4-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the property clock-names in the schema. It fixes the dtbs_warning, 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Varshini Rajendran --- Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Docu= mentation/devicetree/bindings/usb/generic-ehci.yaml index 7e486cc6cfb8..542ac26960fc 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -102,6 +102,10 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral =20 + clock-names: + minItems: 1 + maxItems: 4 + power-domains: maxItems: 1 =20 --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91688C7EE2D for ; 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X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="218711144" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:04:01 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:03:59 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:03:47 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc Date: Sun, 4 Jun 2023 01:32:26 +0530 Message-ID: <20230603200243.243878-5-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree file for SAM9X7 SoC family Signed-off-by: Varshini Rajendran [nicolas.ferre@microchip.com: add support for gmac to sam9x7] Signed-off-by: Nicolas Ferre [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc] Signed-off-by: Balamanikandan Gunasundar --- arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++ 1 file changed, 1333 insertions(+) create mode 100644 arch/arm/boot/dts/sam9x7.dtsi diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi new file mode 100644 index 000000000000..f98160182fe6 --- /dev/null +++ b/arch/arm/boot/dts/sam9x7.dtsi @@ -0,0 +1,1333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + model =3D "Microchip SAM9X7 SoC"; + compatible =3D "microchip,sam9x7"; + interrupt-parent =3D <&aic>; + + aliases { + serial0 =3D &dbgu; + gpio0 =3D &pioA; + gpio1 =3D &pioB; + gpio2 =3D &pioC; + gpio3 =3D &pioD; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "arm,arm926ej-s"; + device_type =3D "cpu"; + reg =3D <0>; + }; + }; + + clocks { + slow_xtal: slow_xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + main_xtal: main_xtal { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + }; + + sram: sram@300000 { + compatible =3D "mmio-sram"; + reg =3D <0x300000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x300000 0x10000>; + }; + + ahb { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + usb0: gadget@500000 { + compatible =3D "microchip,sam9x60-udc"; + reg =3D <0x500000 0x100000>, + <0xf803c000 0x400>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH 2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; + clock-names =3D "pclk", "hclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates =3D <480000000>; + status =3D "disabled"; + }; + + ohci0: usb@600000 { + compatible =3D "atmel,at91rm9200-ohci", "usb-ohci"; + reg =3D <0x600000 0x100000>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>= , <&pmc PMC_TYPE_SYSTEM 6>; + clock-names =3D "ohci_clk", "hclk", "uhpck"; + status =3D "disabled"; + }; + + ehci0: usb@700000 { + compatible =3D "atmel,at91sam9g45-ehci", "usb-ehci"; + reg =3D <0x700000 0x100000>; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH 2>; + clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names =3D "usb_clk", "ehci_clk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>; + assigned-clock-rates =3D <480000000>; + status =3D "disabled"; + }; + + sdmmc0: sdio-host@80000000 { + compatible =3D "microchip,sam9x60-sdhci"; + reg =3D <0x80000000 0x300>; + interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 12>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + + sdmmc1: sdio-host@90000000 { + compatible =3D "microchip,sam9x60-sdhci"; + reg =3D <0x90000000 0x300>; + interrupts =3D <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names =3D "hclock", "multclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates =3D <100000000>; + status =3D "disabled"; + }; + }; + + apb { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + flx4: flexcom@f0000000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf0000000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0000000 0x800>; + status =3D "disabled"; + + uart4: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi4: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c4: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx5: flexcom@f0004000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf0004000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0004000 0x800>; + status =3D "disabled"; + + uart5: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c5: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + dma0: dma-controller@f0008000 { + compatible =3D "microchip,sam9x60-dma", "atmel,sama5d4-dma"; + reg =3D <0xf0008000 0x1000>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells =3D <1>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names =3D "dma_clk"; + status =3D "disabled"; + }; + + ssc: ssc@f0010000 { + compatible =3D "atmel,at91sam9g45-ssc"; + reg =3D <0xf0010000 0x4000>; + interrupts =3D <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names =3D "pclk"; + }; + + gpu: gfx2d@f0018000 { + compatible =3D "microchip,sam9x60-gfx2d"; + reg =3D <0xf0018000 0x4000>; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names =3D "periph_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + i2s: i2s@f001c000 { + compatible =3D "microchip,sam9x60-i2smcc"; + reg =3D <0xf001c000 0x100>; + interrupts =3D <34 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(36))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(37))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; + clock-names =3D "pclk", "gclk"; + status =3D "disabled"; + }; + + flx11: flexcom@f0020000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf0020000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0020000 0x800>; + status =3D "disabled"; + + uart11: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c11: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx12: flexcom@f0024000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf0024000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf0024000 0x800>; + status =3D "disabled"; + + uart12: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c12: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + pit64b0: timer@f0028000 { + compatible =3D "microchip,sam9x60-pit64b"; + reg =3D <0xf0028000 0x100>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names =3D "pclk", "gclk"; + }; + + sha: sha@f002c000 { + compatible =3D "atmel,at91sam9g46-sha"; + reg =3D <0xf002c000 0x100>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(34))>; + dma-names =3D "tx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "sha_clk"; + }; + + trng: trng@f0030000 { + compatible =3D "microchip,sam9x60-trng"; + reg =3D <0xf0030000 0x100>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + status =3D "disabled"; + }; + + aes: aes@f0034000 { + compatible =3D "atmel,at91sam9g46-aes"; + reg =3D <0xf0034000 0x100>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(32))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(33))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "aes_clk"; + }; + + tdes: tdes@f0038000 { + compatible =3D "atmel,at91sam9g46-tdes"; + reg =3D <0xf0038000 0x100>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH 0>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(31))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(30))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "tdes_clk"; + }; + + classd: classd@f003c000 { + compatible =3D "atmel,sama5d2-classd"; + reg =3D <0xf003c000 0x100>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(35))>; + dma-names =3D "tx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; + clock-names =3D "pclk", "gclk"; + status =3D "disabled"; + }; + + pit64b1: timer@f0040000 { + compatible =3D "microchip,sam9x60-pit64b"; + reg =3D <0xf0040000 0x100>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; + clock-names =3D "pclk", "gclk"; + }; + + can0: can@f8000000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8000000 0x100>, <0x300000 0x7800>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <29 IRQ_TYPE_LEVEL_HIGH 0 + 68 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 2= 9>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x3400 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + can1: can@f8004000 { + compatible =3D "bosch,m_can"; + reg =3D <0xf8004000 0x100>, <0x300000 0xbc00>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D <30 IRQ_TYPE_LEVEL_HIGH 0 + 69 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names =3D "int0", "int1"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; + clock-names =3D "hclk", "cclk"; + assigned-clocks =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 3= 0>; + assigned-clock-rates =3D <480000000>, <40000000>; + assigned-clock-parents =3D <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYP= E_CORE PMC_UTMI>; + bosch,mram-cfg =3D <0x7800 0 0 64 0 0 32 32>; + status =3D "disabled"; + }; + + tcb: timer@f8008000 { + compatible =3D "microchip,sam9x60-tcb", "simple-mfd", "syscon"; + reg =3D <0xf8008000 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; + clock-names =3D "t0_clk", "slow_clk"; + status =3D "disabled"; + }; + + flx6: flexcom@f8010000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8010000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8010000 0x800>; + status =3D "disabled"; + + uart6: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx7: flexcom@f8014000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8014000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8014000 0x800>; + status =3D "disabled"; + + uart7: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx8: flexcom@f8018000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8018000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8018000 0x800>; + status =3D "disabled"; + + uart8: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c8: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx0: flexcom@f801c000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf801c000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf801c000 0x800>; + status =3D "disabled"; + + uart0: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@f8020000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8020000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8020000 0x800>; + status =3D "disabled"; + + uart1: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx2: flexcom@f8024000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8024000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8024000 0x800>; + status =3D "disabled"; + + uart2: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@f8028000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8028000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8028000 0x800>; + status =3D "disabled"; + + uart3: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names =3D "spi_clk"; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + gmac: ethernet@f802c000 { + compatible =3D "microchip,sam9x7-gem"; + reg =3D <0xf802c000 0x1000>; + interrupts =3D <24 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ + 60 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ + 61 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 2 */ + 62 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 3 */ + 63 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 4 */ + 64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; + clock-names =3D "hclk", "pclk"; + status =3D "disabled"; + }; + + flx9: flexcom@f8040000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8040000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8040000 0x800>; + status =3D "disabled"; + + uart9: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c9: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + flx10: flexcom@f8044000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8044000 0x200>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8044000 0x800>; + status =3D "disabled"; + + uart10: serial@200 { + compatible =3D "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names =3D "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + + i2c10: i2c@600 { + compatible =3D "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <16>; + status =3D "disabled"; + }; + }; + + xisc: xisc@f8048000 { + compatible =3D "microchip,sama7g5-isc"; + reg =3D <0xf8048000 0x2000>; + interrupts =3D <43 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names =3D "hclock"; + #clock-cells =3D <0>; + clock-output-names =3D "isc-mck"; + status =3D "disabled"; + + port { + xisc_in: endpoint { + bus-width =3D <14>; + hsync-active =3D <1>; + vsync-active =3D <1>; + remote-endpoint =3D <&csi2dc_out>; + }; + }; + }; + + sfr: sfr@f8050000 { + compatible =3D "microchip,sam9x60-sfr", "syscon"; + reg =3D <0xf8050000 0x100>; + }; + + csi2host: csi2host@f8058000 { + compatible =3D "snps,dw-csi"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0xf8058000 0x7FF>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 53>, <&pmc PMC_TYPE_GCK 55>; + clock-names =3D "perclk", "phyclk"; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 55>; + assigned-clock-rates =3D <26600000>; + snps,output-type =3D <1>; + phys =3D <&csi_dphy>; + status =3D "disabled"; + + port@1 { + reg =3D <1>; + csi2host_in: endpoint { + }; + }; + + port@2 { + reg =3D <2>; + csi2host_out: endpoint { + }; + }; + }; + + csi_dphy: dphy@f8058040 { + compatible =3D "snps,dw-dphy-rx"; + #phy-cells =3D <0>; + bus-width =3D <8>; + snps,dphy-frequency =3D <900000>; + snps,phy_type =3D <0>; + reg =3D <0xf8058040 0x20>; + status =3D "disabled"; + }; + + csi2dc: csi2dc@f805c000 { + compatible =3D "microchip,sama7g5-csi2dc"; + reg =3D <0xf805c000 0x500>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 52>, <&xisc>; + clock-names =3D "pclk", "scck"; + assigned-clocks =3D <&xisc>; + assigned-clock-rates =3D <266000000>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + port@0 { + reg =3D <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + csi2dc_out: endpoint { + bus-width =3D <14>; + hsync-active =3D <1>; + vsync-active =3D <1>; + remote-endpoint =3D <&xisc_in>; + }; + }; + }; + }; + + matrix: matrix@ffffde00 { + compatible =3D "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "= syscon"; + reg =3D <0xffffde00 0x200>; + }; + + pmecc: ecc-engine@ffffe000 { + compatible =3D "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg =3D <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + mpddrc: mpddrc@ffffe800 { + compatible =3D "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; + reg =3D <0xffffe800 0x200>; + clocks =3D <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clock-names =3D "ddrck", "mpddr"; + }; + + smc: smc@ffffea00 { + compatible =3D "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "sysco= n"; + reg =3D <0xffffea00 0x100>; + }; + + aic: interrupt-controller@fffff100 { + compatible =3D "microchip,sam9x7-aic"; + reg =3D <0xfffff100 0x100>; + #interrupt-cells =3D <3>; + interrupt-controller; + atmel,external-irqs =3D <31>; + }; + + dbgu: serial@fffff200 { + compatible =3D "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "at= mel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg =3D <0xfffff200 0x200>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH 7>; + dmas =3D <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(28))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(29))>; + dma-names =3D "tx", "rx"; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 47>; + clock-names =3D "usart"; + status =3D "disabled"; + }; + + pinctrl: pinctrl@fffff400 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl",= "simple-mfd"; + ranges =3D <0xfffff400 0xfffff400 0x800>; + + /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ + atmel,mux-mask =3D < + /* A B C D */ + 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ + 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000 /* pioB */ + 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ + 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ + >; + + pioA: gpio@fffff400 { + compatible =3D "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff400 0x200>; + interrupts =3D <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + + pioB: gpio@fffff600 { + compatible =3D "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff600 0x200>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <26>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 3>; + }; + + pioC: gpio@fffff800 { + compatible =3D "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffff800 0x200>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 4>; + }; + + pioD: gpio@fffffa00 { + compatible =3D "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atm= el,at91rm9200-gpio"; + reg =3D <0xfffffa00 0x200>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells =3D <2>; + gpio-controller; + #gpio-lines =3D <22>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + }; + }; + + pmc: pmc@fffffc00 { + compatible =3D "microchip,sam9x7-pmc", "syscon"; + reg =3D <0xfffffc00 0x200>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + #clock-cells =3D <2>; + clocks =3D <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names =3D "td_slck", "md_slck", "main_xtal"; + }; + + reset_controller: rstc@fffffe00 { + compatible =3D "microchip,sam9x60-rstc"; + reg =3D <0xfffffe00 0x10>; + clocks =3D <&clk32k 0>; + }; + + shutdown_controller: shdwc@fffffe10 { + compatible =3D "microchip,sam9x60-shdwc"; + reg =3D <0xfffffe10 0x10>; + clocks =3D <&clk32k 0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status =3D "disabled"; + }; + + rtt: rtc@fffffe20 { + compatible =3D "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg =3D <0xfffffe20 0x20>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + clk32k: sckc@fffffe50 { + compatible =3D "microchip,sam9x60-sckc"; + reg =3D <0xfffffe50 0x4>; + clocks =3D <&slow_xtal>; + #clock-cells =3D <1>; + }; + + gpbr: syscon@fffffe60 { + compatible =3D "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "sys= con"; + reg =3D <0xfffffe60 0x10>; + }; + + rtc: rtc@fffffea8 { + compatible =3D "microchip,sam9x60-rtc"; + reg =3D <0xfffffea8 0x100>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + }; + + watchdog: watchdog@ffffff80 { + compatible =3D "microchip,sam9x60-wdt"; + reg =3D <0xffffff80 0x24>; + interrupts =3D <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks =3D <&clk32k 0>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86A91C7EE2F for ; Sat, 3 Jun 2023 20:04:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229878AbjFCUEi (ORCPT ); Sat, 3 Jun 2023 16:04:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbjFCUE1 (ORCPT ); Sat, 3 Jun 2023 16:04:27 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 139FD1B7; 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Sat, 3 Jun 2023 13:04:12 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:04:00 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 05/21] ARM: configs: at91: enable config flags for sam9x7 SoC Date: Sun, 4 Jun 2023 01:32:27 +0530 Message-ID: <20230603200243.243878-6-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable config flags for SAM9X7 SoC Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 82bcf4dc7f54..6266a000736b 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=3Dy CONFIG_SOC_AT91RM9200=3Dy CONFIG_SOC_AT91SAM9=3Dy CONFIG_SOC_SAM9X60=3Dy +CONFIG_SOC_SAM9X7=3Dy # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set CONFIG_AEABI=3Dy CONFIG_UACCESS_WITH_MEMCPY=3Dy --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E34EC77B73 for ; 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X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="216104494" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:04:25 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:04:25 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:04:13 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 06/21] ARM: configs: at91: add mcan support Date: Sun, 4 Jun 2023 01:32:28 +0530 Message-ID: <20230603200243.243878-7-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable MCAN configs to support sam9x7 soc family Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index 6266a000736b..f18bcf2dcd24 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -82,6 +82,8 @@ CONFIG_DM9000=3Dy CONFIG_DAVICOM_PHY=3Dy CONFIG_MICREL_PHY=3Dy CONFIG_CAN_AT91=3Dy +CONFIG_CAN_M_CAN=3Dy +CONFIG_CAN_M_CAN_PLATFORM=3Dy CONFIG_LIBERTAS=3Dm CONFIG_LIBERTAS_SDIO=3Dm CONFIG_LIBERTAS_SPI=3Dm --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55862C7EE2F for ; Sat, 3 Jun 2023 20:04:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230031AbjFCUEx (ORCPT ); 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X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="216703633" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:04:40 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:04:38 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:04:26 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 07/21] ARM: configs: at91: Enable csi and isc support Date: Sun, 4 Jun 2023 01:32:29 +0530 Message-ID: <20230603200243.243878-8-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balamanikandan Gunasundar Enable CSI, ISC and IMX219 camera sensor support for image capture pipeline. Signed-off-by: Balamanikandan Gunasundar Signed-off-by: Varshini Rajendran --- arch/arm/configs/at91_dt_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_= defconfig index f18bcf2dcd24..6d1170bb2c81 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -141,7 +141,12 @@ CONFIG_MEDIA_PLATFORM_SUPPORT=3Dy CONFIG_MEDIA_USB_SUPPORT=3Dy CONFIG_USB_VIDEO_CLASS=3Dm CONFIG_V4L_PLATFORM_DRIVERS=3Dy +CONFIG_VIDEO_ATMEL_XISC=3Dy CONFIG_VIDEO_ATMEL_ISI=3Dy +CONFIG_VIDEO_MICROCHIP_CSI2DC=3Dy +CONFIG_DWC_MIPI_CSI2_HOST=3Dm +CONFIG_DWC_MIPI_DPHY_GEN3=3Dm +CONFIG_VIDEO_IMX219=3Dm CONFIG_VIDEO_MT9V032=3Dm CONFIG_VIDEO_OV2640=3Dm CONFIG_VIDEO_OV7740=3Dm --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by 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13:04:39 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family Date: Sun, 4 Jun 2023 01:32:30 +0530 Message-ID: <20230603200243.243878-9-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support and pm init config for sam9x7 soc Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- arch/arm/mach-at91/generic.h | 2 ++ arch/arm/mach-at91/pm.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0c3960a8b3eb..acf0b3c82a30 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -12,6 +12,7 @@ extern void __init at91rm9200_pm_init(void); extern void __init at91sam9_pm_init(void); extern void __init sam9x60_pm_init(void); +extern void __init sam9x7_pm_init(void); extern void __init sama5_pm_init(void); extern void __init sama5d2_pm_init(void); extern void __init sama7_pm_init(void); @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void); static inline void __init at91rm9200_pm_init(void) { } static inline void __init at91sam9_pm_init(void) { } static inline void __init sam9x60_pm_init(void) { } +static inline void __init sam9x7_pm_init(void) { } static inline void __init sama5_pm_init(void) { } static inline void __init sama5d2_pm_init(void) { } static inline void __init sama7_pm_init(void) { } diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 60dc56d8acfb..43a77ae0c38c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -232,6 +232,17 @@ static const struct of_device_id sama7g5_ws_ids[] =3D { { /* sentinel */ } }; =20 +static const struct of_device_id sam9x7_ws_ids[] =3D { + { .compatible =3D "microchip,sam9x60-rtc", .data =3D &ws_info[1] }, + { .compatible =3D "atmel,at91rm9200-ohci", .data =3D &ws_info[2] }, + { .compatible =3D "usb-ohci", .data =3D &ws_info[2] }, + { .compatible =3D "atmel,at91sam9g45-ehci", .data =3D &ws_info[2] }, + { .compatible =3D "usb-ehci", .data =3D &ws_info[2] }, + { .compatible =3D "microchip,sam9x60-rtt", .data =3D &ws_info[4] }, + { .compatible =3D "microchip,sam9x7-gem", .data =3D &ws_info[5] }, + { /* sentinel */ } +}; + static int at91_pm_config_ws(unsigned int pm_mode, bool set) { const struct wakeup_source_info *wsi; @@ -1133,6 +1144,7 @@ static const struct of_device_id gmac_ids[] __initcon= st =3D { { .compatible =3D "atmel,sama5d2-gem" }, { .compatible =3D "atmel,sama5d29-gem" }, { .compatible =3D "microchip,sama7g5-gem" }, + { .compatible =3D "microchip,sam9x7-gem" }, { }, }; =20 @@ -1360,6 +1372,7 @@ static const struct of_device_id atmel_pmc_ids[] __in= itconst =3D { { .compatible =3D "atmel,sama5d2-pmc", .data =3D &pmc_infos[1] }, { .compatible =3D "microchip,sam9x60-pmc", .data =3D &pmc_infos[4] }, { .compatible =3D "microchip,sama7g5-pmc", .data =3D &pmc_infos[5] }, + { .compatible =3D "microchip,sam9x7-pmc", .data =3D &pmc_infos[4] }, { /* sentinel */ }, }; =20 @@ -1497,6 +1510,28 @@ void __init sam9x60_pm_init(void) soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; } =20 +void __init sam9x7_pm_init(void) +{ + static const int modes[] __initconst =3D { + AT91_PM_STANDBY, AT91_PM_ULP0, + }; + + int ret; + + if (!IS_ENABLED(CONFIG_SOC_SAM9X7)) + return; + + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); + ret =3D at91_dt_ramc(false); + if (ret) + return; + + at91_pm_init(NULL); + + soc_pm.ws_ids =3D sam9x7_ws_ids; + soc_pm.config_pmc_ws =3D at91_sam9x60_config_pmc_ws; +} + void __init at91sam9_pm_init(void) { int ret; --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E363C77B7A for ; Sat, 3 Jun 2023 20:05:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbjFCUFV (ORCPT ); Sat, 3 Jun 2023 16:05:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230024AbjFCUFS (ORCPT ); Sat, 3 Jun 2023 16:05:18 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 026571BD; Sat, 3 Jun 2023 13:05:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822705; x=1717358705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j328QsBu4eVTOOKjQLsaJ9CBGwldAnFNwooMafcZCZE=; b=nJPlPocbtfUpZrB7nwDBJr+IsxJXf8TVEKs8Xmccud0rKeIfnWM3V5VE gKVCG7XK+n93tp5H+TjdHwuUmnnv+NZdN/ef9eP7qH2+lgk3lFWW31Uxb oRzf4xAKj07M9+B6dskKHFC0GHyxNy0piKUaRHU5t6CK1rfYHKDe9nYsJ naKatrxpwoVDwUBNl/zEwCwJPiuPghRrmg+EwARDJBWzCCVy5+V7Fcabb Npmykp7OXz0Wo6B0hJOiIvO+QYV602Ax2R/PlRIUt88uh/MWpH7t1wf6s Lrsb3a7U3VP+XDr9ml3xR91g/3ajocivfqcq8uM7XQCzi/s8TifApSGuv Q==; X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="216104547" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:05:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:05:04 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:04:52 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config Date: Sun, 4 Jun 2023 01:32:31 +0530 Message-ID: <20230603200243.243878-10-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add SoC init config for sam9x7 family Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm/mach-at91/sam9x7.c diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 794bd12ab0a8..7d8a7bc44e65 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_AT91RM9200) +=3D at91rm9200.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5) +=3D sama5.o sam_secure.o obj-$(CONFIG_SOC_SAMA7) +=3D sama7.o obj-$(CONFIG_SOC_SAMV7) +=3D samv7.o diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c new file mode 100644 index 000000000000..e322c5a3cdb6 --- /dev/null +++ b/arch/arm/mach-at91/sam9x7.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Setup code for SAM9X7. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + */ + +#include +#include + +#include +#include + +#include "generic.h" + +static void __init sam9x7_init(void) +{ + of_platform_default_populate(NULL, NULL, NULL); + + sam9x7_pm_init(); +} + +static const char *const sam9x7_dt_board_compat[] __initconst =3D { + "microchip,sam9x7", + NULL +}; + +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7") + /* Maintainer: Microchip */ + .init_machine =3D sam9x7_init, + .dt_compat =3D sam9x7_dt_board_compat, +MACHINE_END --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E37BAC77B7A for ; Sat, 3 Jun 2023 20:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbjFCUFm (ORCPT ); Sat, 3 Jun 2023 16:05:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49020 "EHLO lindbergh.monkeyblade.net" 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d="scan'208";a="228307953" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:05:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:05:17 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:05:05 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Date: Sun, 4 Jun 2023 01:32:32 +0530 Message-ID: <20230603200243.243878-11-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add config flag for sam9x7 SoC Signed-off-by: Varshini Rajendran --- arch/arm/mach-at91/Kconfig | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3dd9e718661b..4463afd7298a 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -143,11 +143,28 @@ config SOC_SAM9X60 help Select this if you are using Microchip's SAM9X60 SoC =20 +config SOC_SAM9X7 + bool "SAM9X7" + depends on ARCH_MULTI_V5 + select ATMEL_AIC5_IRQ + select ATMEL_PM if PM + select ATMEL_SDRAMC + select CPU_ARM926T + select HAVE_AT91_USB_CLK + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select MEMORY + select PINCTRL_AT91 + select SOC_SAM_V4_V5 + select SRAM if PM + help + Select this if you are using Microchip's SAM9X7 SoC + comment "Clocksource driver selection" =20 config ATMEL_CLOCKSOURCE_PIT bool "Periodic Interval Timer (PIT) support" - depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5 select ATMEL_PIT help @@ -157,7 +174,7 @@ config ATMEL_CLOCKSOURCE_PIT =20 config ATMEL_CLOCKSOURCE_TCB bool "Timer Counter Blocks (TCB) support" - default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SO= C_SAMA5 select ATMEL_TCB_CLKSRC help Select this to get a high precision clocksource based on a --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org 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15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:05:18 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7 Date: Sun, 4 Jun 2023 01:32:33 +0530 Message-ID: <20230603200243.243878-12-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for SAM9X7 SoC in the soc driver Signed-off-by: Varshini Rajendran Reviewed-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++ drivers/soc/atmel/soc.h | 9 +++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index cc9a3e107479..cae3452cbc60 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst =3D { AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH, "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif +#ifdef CONFIG_SOC_SAM9X7 + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH, + "sam9x72", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH, + "sam9x70", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 1Gb DDR3L SiP ", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 512Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 128Mb DDR2 SiP", "sam9x7"), + AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH, + AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH, + "sam9x75 2Gb DDR3L SiP", "sam9x7"), +#endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 7a9f47ce85fb..26dd26b4f179 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAMA7G5_CIDR_MATCH 0x00162100 +#define SAM9X7_CIDR_MATCH 0x09750020 =20 #define AT91SAM9M11_EXID_MATCH 0x00000001 #define AT91SAM9M10_EXID_MATCH 0x00000002 @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA7G54_D2G_EXID_MATCH 0x00000020 #define SAMA7G54_D4G_EXID_MATCH 0x00000028 =20 +#define SAM9X75_EXID_MATCH 0x00000000 +#define SAM9X72_EXID_MATCH 0x00000004 +#define SAM9X70_EXID_MATCH 0x00000005 +#define SAM9X75_D1G_EXID_MATCH 0x00000001 +#define SAM9X75_D5M_EXID_MATCH 0x00000002 +#define SAM9X75_D1M_EXID_MATCH 0x00000003 +#define SAM9X75_D2G_EXID_MATCH 0x00000006 + #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 08D47C7EE2F for ; Sat, 3 Jun 2023 20:06:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230264AbjFCUGL (ORCPT ); Sat, 3 Jun 2023 16:06:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49572 "EHLO lindbergh.monkeyblade.net" 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d="scan'208";a="214485442" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:05:44 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:05:43 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:05:31 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Date: Sun, 4 Jun 2023 01:32:34 +0530 Message-ID: <20230603200243.243878-13-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" -Support SoCs with different core frequency outputs for different PLL IDs by adding a separate parameter for handling the same in the PLL driver -Align sam9x60 and sama7g5 Soc PMC driver to PLL driver by adding core output freq range in the PLL characteristics configurations Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------ drivers/clk/at91/pmc.h | 1 + drivers/clk/at91/sam9x60.c | 7 +++++++ drivers/clk/at91/sama7g5.c | 7 +++++++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index 0882ed01d5c2..b3012641214c 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -23,9 +23,6 @@ #define UPLL_DIV 2 #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1) =20 -#define FCORE_MIN (600000000) -#define FCORE_MAX (1200000000) - #define PLL_MAX_ID 7 =20 struct sam9x60_pll_core { @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, unsigned long nmul =3D 0; unsigned long nfrac =3D 0; =20 - if (rate < FCORE_MIN || rate > FCORE_MAX) + if (rate < core->characteristics->core_output[0].min || + rate > core->characteristics->core_output[0].max) return -ERANGE; =20 /* @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sa= m9x60_pll_core *core, } =20 /* Check if resulted rate is a valid. */ - if (tmprate < FCORE_MIN || tmprate > FCORE_MAX) + if (tmprate < core->characteristics->core_output[0].min || + tmprate > core->characteristics->core_output[0].max) return -ERANGE; =20 if (update) { @@ -666,7 +665,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, sp= inlock_t *lock, goto free; } =20 - ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN, + ret =3D sam9x60_frac_pll_compute_mul_frac(&frac->core, + characteristics->core_output[0].min, parent_rate, true); if (ret < 0) { hw =3D ERR_PTR(ret); diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 1b3ca7dd9b57..3e36dcc464c1 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -75,6 +75,7 @@ struct clk_pll_characteristics { struct clk_range input; int num_output; const struct clk_range *output; + const struct clk_range *core_output; u16 *icpll; u8 *out; u8 upll : 1; diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index ac070db58195..452ad45cf251 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + static const struct clk_pll_characteristics plla_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(plla_outputs), .output =3D plla_outputs, + .core_output =3D core_outputs, }; =20 static const struct clk_range upll_outputs[] =3D { @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characte= ristics =3D { .input =3D { .min =3D 12000000, .max =3D 48000000 }, .num_output =3D ARRAY_SIZE(upll_outputs), .output =3D upll_outputs, + .core_output =3D core_outputs, .upll =3D true, }; =20 diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index f135b662f1ff..468a3c5449b5 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -104,11 +104,17 @@ static const struct clk_range pll_outputs[] =3D { { .min =3D 2343750, .max =3D 1200000000 }, }; =20 +/* Fractional PLL core output range. */ +static const struct clk_range core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + /* CPU PLL characteristics. */ static const struct clk_pll_characteristics cpu_pll_characteristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(cpu_pll_outputs), .output =3D cpu_pll_outputs, + .core_output =3D core_outputs, }; =20 /* PLL characteristics. */ @@ -116,6 +122,7 @@ static const struct clk_pll_characteristics pll_charact= eristics =3D { .input =3D { .min =3D 12000000, .max =3D 50000000 }, .num_output =3D ARRAY_SIZE(pll_outputs), .output =3D pll_outputs, + .core_output =3D core_outputs, }; =20 /* --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE551C7EE32 for ; Sat, 3 Jun 2023 20:06:39 +0000 (UTC) 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msln28PXLKKHGZavElPFajyzzk9Vf1JUI942lx8gKIBkauvRSK8thpElE kPUKFC1Ya3x5qFAuVT+RYT7vn6C8MvfMPxmIq6laHag0RcxXkTAl7aRZO Et7ziO4WF9wi5pbXxXeecj8pf4fQcZwQnpFky/UJcE5CuWf99Em7iQSQF Q==; X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="216104611" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:05:56 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:05:56 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:05:43 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers Date: Sun, 4 Jun 2023 01:32:35 +0530 Message-ID: <20230603200243.243878-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for hardware dividers for PLL IDs in sam9x7 Soc PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each fcorepllack -----> HW Div =3D 2 -+--> fpllack | +--> HW Div =3D 2 ---> fplladiv2ck Signed-off-by: Varshini Rajendran --- drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++---- drivers/clk/at91/pmc.h | 1 + 2 files changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9= x60-pll.c index b3012641214c..76273ea74f8b 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct= clk_hw *hw, { struct sam9x60_pll_core *core =3D to_sam9x60_pll_core(hw); struct sam9x60_frac *frac =3D to_sam9x60_frac(core); + unsigned long freq; =20 - return parent_rate * (frac->mul + 1) + + freq =3D parent_rate * (frac->mul + 1) + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); + + if (core->layout->div2) + freq >>=3D 1; + + return freq; } =20 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struc= t clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1)); } =20 +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate >> 1; +} + static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core, unsigned long *parent_rate, unsigned long rate) @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = =3D { .restore_context =3D sam9x60_div_pll_restore_context, }; =20 +static const struct clk_ops sam9x60_fixed_div_pll_ops =3D { + .prepare =3D sam9x60_div_pll_prepare, + .unprepare =3D sam9x60_div_pll_unprepare, + .is_prepared =3D sam9x60_div_pll_is_prepared, + .recalc_rate =3D sam9x60_fixed_div_pll_recalc_rate, + .round_rate =3D sam9x60_div_pll_round_rate, + .save_context =3D sam9x60_div_pll_save_context, + .restore_context =3D sam9x60_div_pll_restore_context, +}; + struct clk_hw * __init sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock, const char *name, const char *parent_name, @@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, s= pinlock_t *lock, init.name =3D name; init.parent_names =3D &parent_name; init.num_parents =3D 1; - if (flags & CLK_SET_RATE_GATE) - init.ops =3D &sam9x60_div_pll_ops; - else - init.ops =3D &sam9x60_div_pll_ops_chg; + + if (layout->div2) { + init.ops =3D &sam9x60_fixed_div_pll_ops; + } else { + if (flags & CLK_SET_RATE_GATE) + init.ops =3D &sam9x60_div_pll_ops; + else + init.ops =3D &sam9x60_div_pll_ops_chg; + } + init.flags =3D flags; =20 div->core.id =3D id; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 3e36dcc464c1..1dd01f30bdee 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -64,6 +64,7 @@ struct clk_pll_layout { u8 frac_shift; u8 div_shift; u8 endiv_shift; + u8 div2; }; =20 extern const struct clk_pll_layout at91rm9200_pll_layout; --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7AF0C7EE24 for ; Sat, 3 Jun 2023 20:08:16 +0000 (UTC) Received: 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Subject: [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver Date: Sun, 4 Jun 2023 01:32:36 +0530 Message-ID: <20230603200243.243878-15-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a driver for the PMC clocks of sam9x7 Soc family Signed-off-by: Varshini Rajendran --- drivers/clk/at91/Makefile | 1 + drivers/clk/at91/sam9x7.c | 947 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 948 insertions(+) create mode 100644 drivers/clk/at91/sam9x7.c diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile index 89061b85e7d2..8e3684ba2c74 100644 --- a/drivers/clk/at91/Makefile +++ b/drivers/clk/at91/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9260.o at91sam9rl.= o at91sam9x5.o dt-compat. obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9g45.o dt-compat.o obj-$(CONFIG_SOC_AT91SAM9) +=3D at91sam9n12.o at91sam9x5.o dt-compat.o obj-$(CONFIG_SOC_SAM9X60) +=3D sam9x60.o +obj-$(CONFIG_SOC_SAM9X7) +=3D sam9x7.o obj-$(CONFIG_SOC_SAMA5D3) +=3D sama5d3.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D4) +=3D sama5d4.o dt-compat.o obj-$(CONFIG_SOC_SAMA5D2) +=3D sama5d2.o dt-compat.o diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c new file mode 100644 index 000000000000..8232a2af14be --- /dev/null +++ b/drivers/clk/at91/sam9x7.c @@ -0,0 +1,947 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SAM9X7 PMC code. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Varshini Rajendran + * + */ +#include +#include +#include +#include + +#include + +#include "pmc.h" + +#define SAM9X7_INIT_TABLE(_table, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) \ + (_table)[_i] =3D _i; \ + } while (0) + +#define SAM9X7_FILL_TABLE(_to, _from, _count) \ + do { \ + u8 _i; \ + for (_i =3D 0; _i < (_count); _i++) { \ + (_to)[_i] =3D (_from)[_i]; \ + } \ + } while (0) + +static DEFINE_SPINLOCK(pmc_pll_lock); +static DEFINE_SPINLOCK(mck_lock); + +/** + * enum pll_ids - PLL clocks identifiers + * @PLL_ID_PLLA: PLLA identifier + * @PLL_ID_UPLL: UPLL identifier + * @PLL_ID_AUDIO: Audio PLL identifier + * @PLL_ID_LVDS: LVDS PLL identifier + * @PLL_ID_PLLA_DIV2: PLLA DIV2 identifier + * @PLL_ID_MAX: Max PLL Identifier + */ +enum pll_ids { + PLL_ID_PLLA, + PLL_ID_UPLL, + PLL_ID_AUDIO, + PLL_ID_LVDS, + PLL_ID_PLLA_DIV2, + PLL_ID_MAX, +}; + +/** + * enum pll_type - PLL type identifiers + * @PLL_TYPE_FRAC: fractional PLL identifier + * @PLL_TYPE_DIV: divider PLL identifier + */ +enum pll_type { + PLL_TYPE_FRAC, + PLL_TYPE_DIV, +}; + +static const struct clk_master_characteristics mck_characteristics =3D { + .output =3D { .min =3D 32000000, .max =3D 266666667 }, + .divisors =3D { 1, 2, 4, 3 }, + .have_div3_pres =3D 1, +}; + +static const struct clk_master_layout sam9x7_master_layout =3D { + .mask =3D 0x373, + .pres_shift =3D 4, + .offset =3D 0x28, +}; + +/* Fractional PLL core output range. */ +static const struct clk_range plla_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +static const struct clk_range upll_core_outputs[] =3D { + { .min =3D 600000000, .max =3D 1200000000 }, +}; + +static const struct clk_range lvdspll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_core_outputs[] =3D { + { .min =3D 400000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_core_outputs[] =3D { + { .min =3D 375000000, .max =3D 1600000000 }, +}; + +/* Fractional PLL output range. */ +static const struct clk_range plla_outputs[] =3D { + { .min =3D 732421, .max =3D 800000000 }, +}; + +static const struct clk_range upll_outputs[] =3D { + { .min =3D 300000000, .max =3D 600000000 }, +}; + +static const struct clk_range lvdspll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range audiopll_outputs[] =3D { + { .min =3D 10000000, .max =3D 800000000 }, +}; + +static const struct clk_range plladiv2_outputs[] =3D { + { .min =3D 366210, .max =3D 400000000 }, +}; + +/* PLL characteristics. */ +static const struct clk_pll_characteristics plla_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plla_outputs), + .output =3D plla_outputs, + .core_output =3D plla_core_outputs, +}; + +static const struct clk_pll_characteristics upll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(upll_outputs), + .output =3D upll_outputs, + .core_output =3D upll_core_outputs, + .upll =3D true, +}; + +static const struct clk_pll_characteristics lvdspll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(lvdspll_outputs), + .output =3D lvdspll_outputs, + .core_output =3D lvdspll_core_outputs, +}; + +static const struct clk_pll_characteristics audiopll_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(audiopll_outputs), + .output =3D audiopll_outputs, + .core_output =3D audiopll_core_outputs, +}; + +static const struct clk_pll_characteristics plladiv2_characteristics =3D { + .input =3D { .min =3D 20000000, .max =3D 50000000 }, + .num_output =3D ARRAY_SIZE(plladiv2_outputs), + .output =3D plladiv2_outputs, + .core_output =3D plladiv2_core_outputs, +}; + +/* Layout for fractional PLL ID PLLA. */ +static const struct clk_pll_layout plla_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, + .div2 =3D 1, +}; + +/* Layout for fractional PLLs. */ +static const struct clk_pll_layout pll_frac_layout =3D { + .mul_mask =3D GENMASK(31, 24), + .frac_mask =3D GENMASK(21, 0), + .mul_shift =3D 24, + .frac_shift =3D 0, +}; + +/* Layout for DIV PLLs. */ +static const struct clk_pll_layout pll_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, +}; + +/* Layout for DIV PLL ID PLLADIV2. */ +static const struct clk_pll_layout plladiv2_divpmc_layout =3D { + .div_mask =3D GENMASK(7, 0), + .endiv_mask =3D BIT(29), + .div_shift =3D 0, + .endiv_shift =3D 29, + .div2 =3D 1, +}; + +/* Layout for DIVIO dividers. */ +static const struct clk_pll_layout pll_divio_layout =3D { + .div_mask =3D GENMASK(19, 12), + .endiv_mask =3D BIT(30), + .div_shift =3D 12, + .endiv_shift =3D 30, +}; + +/* + * PLL clocks description + * @n: clock name + * @p: clock parent + * @l: clock layout + * @t: clock type + * @c: pll characteristics + * @f: true if clock is critical and cannot be disabled + * @eid: export index in sam9x7->chws[] array + */ +static const struct { + const char *n; + const char *p; + const struct clk_pll_layout *l; + u8 t; + const struct clk_pll_characteristics *c; + unsigned long f; + u8 eid; +} sam9x7_plls[][PLL_ID_MAX] =3D { + [PLL_ID_PLLA] =3D { + { + .n =3D "plla_fracck", + .p =3D "mainck", + .l =3D &plla_frac_layout, + .t =3D PLL_TYPE_FRAC, + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plla_characteristics, + }, + + { + .n =3D "plla_divpmcck", + .p =3D "plla_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .eid =3D PMC_PLLACK, + .c =3D &plla_characteristics, + }, + }, + + [PLL_ID_UPLL] =3D { + { + .n =3D "upll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .t =3D PLL_TYPE_FRAC, + .f =3D CLK_SET_RATE_GATE, + .c =3D &upll_characteristics, + }, + + { + .n =3D "upll_divpmcck", + .p =3D "upll_fracck", + .l =3D &pll_divpmc_layout, + .t =3D PLL_TYPE_DIV, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .eid =3D PMC_UTMI, + .c =3D &upll_characteristics, + }, + }, + + [PLL_ID_AUDIO] =3D { + { + .n =3D "audiopll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "audiopll_divpmcck", + .p =3D "audiopll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_DIV, + }, + + { + .n =3D "audiopll_diviock", + .p =3D "audiopll_fracck", + .l =3D &pll_divio_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &audiopll_characteristics, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_LVDS] =3D { + { + .n =3D "lvdspll_fracck", + .p =3D "main_osc", + .l =3D &pll_frac_layout, + .f =3D CLK_SET_RATE_GATE, + .c =3D &lvdspll_characteristics, + .t =3D PLL_TYPE_FRAC, + }, + + { + .n =3D "lvdspll_divpmcck", + .p =3D "lvdspll_fracck", + .l =3D &pll_divpmc_layout, + .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | + CLK_SET_RATE_PARENT, + .c =3D &lvdspll_characteristics, + .t =3D PLL_TYPE_DIV, + }, + }, + + [PLL_ID_PLLA_DIV2] =3D { + { + .n =3D "plla_div2pmcck", + .p =3D "plla_fracck", + .l =3D &plladiv2_divpmc_layout, + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .t =3D PLL_TYPE_DIV, + }, + }, +}; + +static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { + .pres_mask =3D 0xff, + .pres_shift =3D 8, + .css_mask =3D 0x1f, + .have_slck_mck =3D 0, + .is_pres_direct =3D 1, +}; + +static const struct clk_pcr_layout sam9x7_pcr_layout =3D { + .offset =3D 0x88, + .cmd =3D BIT(31), + .gckcss_mask =3D GENMASK(12, 8), + .pid_mask =3D GENMASK(6, 0), +}; + +static const struct { + char *n; + char *p; + u8 id; + unsigned long flags; +} sam9x7_systemck[] =3D { + /* + * ddrck feeds DDR controller and is enabled by bootloader thus we need + * to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, + { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, + { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, + { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, +}; + +/* + * Peripheral clocks description + * @n: clock name + * @f: true if clock is critical and cannot be disabled + * @id: peripheral id + */ +static const struct { + char *n; + unsigned long f; + u8 id; +} sam9x7_periphck[] =3D { + { .n =3D "pioA_clk", .id =3D 2, }, + { .n =3D "pioB_clk", .id =3D 3, }, + { .n =3D "pioC_clk", .id =3D 4, }, + { .n =3D "flex0_clk", .id =3D 5, }, + { .n =3D "flex1_clk", .id =3D 6, }, + { .n =3D "flex2_clk", .id =3D 7, }, + { .n =3D "flex3_clk", .id =3D 8, }, + { .n =3D "flex6_clk", .id =3D 9, }, + { .n =3D "flex7_clk", .id =3D 10, }, + { .n =3D "flex8_clk", .id =3D 11, }, + { .n =3D "sdmmc0_clk", .id =3D 12, }, + { .n =3D "flex4_clk", .id =3D 13, }, + { .n =3D "flex5_clk", .id =3D 14, }, + { .n =3D "flex9_clk", .id =3D 15, }, + { .n =3D "flex10_clk", .id =3D 16, }, + { .n =3D "tcb0_clk", .id =3D 17, }, + { .n =3D "pwm_clk", .id =3D 18, }, + { .n =3D "adc_clk", .id =3D 19, }, + { .n =3D "dma0_clk", .id =3D 20, }, + { .n =3D "uhphs_clk", .id =3D 22, }, + { .n =3D "udphs_clk", .id =3D 23, }, + { .n =3D "macb0_clk", .id =3D 24, }, + { .n =3D "lcd_clk", .id =3D 25, }, + { .n =3D "sdmmc1_clk", .id =3D 26, }, + { .n =3D "ssc_clk", .id =3D 28, }, + { .n =3D "can0_clk", .id =3D 29, }, + { .n =3D "can1_clk", .id =3D 30, }, + { .n =3D "flex11_clk", .id =3D 32, }, + { .n =3D "flex12_clk", .id =3D 33, }, + { .n =3D "i2s_clk", .id =3D 34, }, + { .n =3D "qspi_clk", .id =3D 35, }, + { .n =3D "gfx2d_clk", .id =3D 36, }, + { .n =3D "pit64b0_clk", .id =3D 37, }, + { .n =3D "trng_clk", .id =3D 38, }, + { .n =3D "aes_clk", .id =3D 39, }, + { .n =3D "tdes_clk", .id =3D 40, }, + { .n =3D "sha_clk", .id =3D 41, }, + { .n =3D "classd_clk", .id =3D 42, }, + { .n =3D "isi_clk", .id =3D 43, }, + { .n =3D "pioD_clk", .id =3D 44, }, + { .n =3D "tcb1_clk", .id =3D 45, }, + { .n =3D "dbgu_clk", .id =3D 47, }, + /* + * mpddr_clk feeds DDR controller and is enabled by bootloader thus we + * need to keep it enabled in case there is no Linux consumer for it. + */ + { .n =3D "mpddr_clk", .id =3D 49, .f =3D CLK_IS_CRITICAL }, + { .n =3D "csi2dc_clk", .id =3D 52, }, + { .n =3D "csi4l_clk", .id =3D 53, }, + { .n =3D "dsi4l_clk", .id =3D 54, }, + { .n =3D "lvdsc_clk", .id =3D 56, }, + { .n =3D "pit64b1_clk", .id =3D 58, }, + { .n =3D "puf_clk", .id =3D 59, }, + { .n =3D "gmactsu_clk", .id =3D 67, }, +}; + +/* + * Generic clock description + * @n: clock name + * @pp: PLL parents + * @pp_mux_table: PLL parents mux table + * @r: clock output range + * @pp_chg_id: id in parent array of changeable PLL parent + * @pp_count: PLL parents count + * @id: clock id + */ +static const struct { + const char *n; + const char *pp[8]; + const char pp_mux_table[8]; + struct clk_range r; + int pp_chg_id; + u8 pp_count; + u8 id; +} sam9x7_gck[] =3D { + { + .n =3D "flex0_gclk", + .id =3D 5, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex1_gclk", + .id =3D 6, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex2_gclk", + .id =3D 7, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex3_gclk", + .id =3D 8, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex6_gclk", + .id =3D 9, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex7_gclk", + .id =3D 10, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex8_gclk", + .id =3D 11, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc0_gclk", + .id =3D 12, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex4_gclk", + .id =3D 13, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex5_gclk", + .id =3D 14, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex9_gclk", + .id =3D 15, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex10_gclk", + .id =3D 16, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb0_gclk", + .id =3D 17, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "adc_gclk", + .id =3D 19, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "lcd_gclk", + .id =3D 25, + .r =3D { .max =3D 75000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "sdmmc1_gclk", + .id =3D 26, + .r =3D { .max =3D 105000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan0_gclk", + .id =3D 29, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mcan1_gclk", + .id =3D 30, + .r =3D { .max =3D 80000000 }, + .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 5, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex11_gclk", + .id =3D 32, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "flex12_gclk", + .id =3D 33, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "i2s_gclk", + .id =3D 34, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "qspi_gclk", + .id =3D 35, + .r =3D { .max =3D 20000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b0_gclk", + .id =3D 37, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "classd_gclk", + .id =3D 42, + .r =3D { .max =3D 100000000 }, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "tcb1_gclk", + .id =3D 45, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "dbgu_gclk", + .id =3D 47, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "mipiphy_gclk", + .id =3D 55, + .r =3D { .max =3D 27000000 }, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "pit64b1_gclk", + .id =3D 58, + .pp =3D { "plla_div2pmcck", }, + .pp_mux_table =3D { 8, }, + .pp_count =3D 1, + .pp_chg_id =3D INT_MIN, + }, + + { + .n =3D "gmac_gclk", + .id =3D 67, + .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp_mux_table =3D { 6, 8, }, + .pp_count =3D 2, + .pp_chg_id =3D INT_MIN, + }, +}; + +static void __init sam9x7_pmc_setup(struct device_node *np) +{ + struct clk_range range =3D CLK_RANGE(0, 0); + const char *td_slck_name, *md_slck_name, *mainxtal_name; + struct pmc_data *sam9x7_pmc; + const char *parent_names[9]; + void **alloc_mem =3D NULL; + int alloc_mem_size =3D 0; + struct clk_hw *main_osc_hw; + struct regmap *regmap; + struct clk_hw *hw; + int i, j; + + i =3D of_property_match_string(np, "clock-names", "td_slck"); + if (i < 0) + return; + + td_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "md_slck"); + if (i < 0) + return; + + md_slck_name =3D of_clk_get_parent_name(np, i); + + i =3D of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name =3D of_clk_get_parent_name(np, i); + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) + return; + + sam9x7_pmc =3D pmc_data_allocate(PMC_PLLACK + 1, + nck(sam9x7_systemck), + nck(sam9x7_periphck), + nck(sam9x7_gck), 8); + if (!sam9x7_pmc) + return; + + alloc_mem =3D kmalloc(sizeof(void *) * + (ARRAY_SIZE(sam9x7_gck)), + GFP_KERNEL); + if (!alloc_mem) + goto err_free; + + hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0); + if (IS_ERR(hw)) + goto err_free; + main_osc_hw =3D hw; + + parent_names[0] =3D "main_rc_osc"; + parent_names[1] =3D "main_osc"; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MAIN] =3D hw; + + for (i =3D 0; i < PLL_ID_MAX; i++) { + for (j =3D 0; j < 3; j++) { + struct clk_hw *parent_hw; + + if (!sam9x7_plls[i][j].n) + continue; + + switch (sam9x7_plls[i][j].t) { + case PLL_TYPE_FRAC: + if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; + else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) + parent_hw =3D main_osc_hw; + else + parent_hw =3D __clk_get_hw(of_clk_get_by_name + (np, sam9x7_plls[i][j].p)); + + hw =3D sam9x60_clk_register_frac_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, + parent_hw, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f); + break; + + case PLL_TYPE_DIV: + hw =3D sam9x60_clk_register_div_pll(regmap, + &pmc_pll_lock, + sam9x7_plls[i][j].n, + sam9x7_plls[i][j].p, i, + sam9x7_plls[i][j].c, + sam9x7_plls[i][j].l, + sam9x7_plls[i][j].f, 0); + break; + + default: + continue; + } + + if (IS_ERR(hw)) + goto err_free; + + if (sam9x7_plls[i][j].eid) + sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; + } + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D "mainck"; + parent_names[2] =3D "plla_divpmcck"; + parent_names[3] =3D "upll_divpmcck"; + hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, + parent_names, &sam9x7_master_layout, + &mck_characteristics, &mck_lock); + if (IS_ERR(hw)) + goto err_free; + + hw =3D at91_clk_register_master_div(regmap, "masterck_div", + "masterck_pres", &sam9x7_master_layout, + &mck_characteristics, &mck_lock, + CLK_SET_RATE_GATE, 0); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->chws[PMC_MCK] =3D hw; + + parent_names[0] =3D "plla_divpmcck"; + parent_names[1] =3D "upll_divpmcck"; + parent_names[2] =3D "main_osc"; + hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(hw)) + goto err_free; + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + parent_names[4] =3D "plla_divpmcck"; + parent_names[5] =3D "upll_divpmcck"; + parent_names[6] =3D "audiopll_divpmcck"; + for (i =3D 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw =3D at91_clk_register_programmable(regmap, name, + parent_names, 7, i, + &sam9x7_programmable_layout, + NULL); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->pchws[i] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { + hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, + sam9x7_systemck[i].p, + sam9x7_systemck[i].id, + sam9x7_systemck[i].flags); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->shws[sam9x7_systemck[i].id] =3D hw; + } + + for (i =3D 0; i < ARRAY_SIZE(sam9x7_periphck); i++) { + hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_periphck[i].n, + "masterck_div", + sam9x7_periphck[i].id, + &range, INT_MIN, + sam9x7_periphck[i].f); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; + } + + parent_names[0] =3D md_slck_name; + parent_names[1] =3D td_slck_name; + parent_names[2] =3D "mainck"; + parent_names[3] =3D "masterck_div"; + for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { + u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + u32 *mux_table; + + mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), + GFP_KERNEL); + if (!mux_table) + goto err_free; + + SAM9X7_INIT_TABLE(mux_table, 4); + SAM9X7_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, + sam9x7_gck[i].pp_count); + SAM9X7_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + sam9x7_gck[i].pp_count); + + hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, + &sam9x7_pcr_layout, + sam9x7_gck[i].n, + parent_names, mux_table, + num_parents, + sam9x7_gck[i].id, + &sam9x7_gck[i].r, + sam9x7_gck[i].pp_chg_id); + if (IS_ERR(hw)) + goto err_free; + + sam9x7_pmc->ghws[sam9x7_gck[i].id] =3D hw; + alloc_mem[alloc_mem_size++] =3D mux_table; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc); + + return; + +err_free: + if (alloc_mem) { + for (i =3D 0; i < alloc_mem_size; i++) + kfree(alloc_mem[i]); + kfree(alloc_mem); + } + kfree(sam9x7_pmc); +} + +/* Some clks are used for a clocksource */ +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup); --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CEAEC77B7A for ; Sat, 3 Jun 2023 20:08:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230511AbjFCUIE (ORCPT ); Sat, 3 Jun 2023 16:08:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230345AbjFCUHx (ORCPT ); Sat, 3 Jun 2023 16:07:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9253E7A; Sat, 3 Jun 2023 13:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822846; x=1717358846; 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2023 13:06:22 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:06:10 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sun, 4 Jun 2023 01:32:37 +0530 Message-ID: <20230603200243.243878-16-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the support added for the Advanced interrupt controller(AIC) chip in the sam9x7 soc family Signed-off-by: Varshini Rajendran --- .../devicetree/bindings/interrupt-controller/atmel,aic.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,a= ic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.t= xt index 7079d44bf3ba..2c267a66a3ea 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,7 @@ Required properties: - compatible: Should be: - "atmel,-aic" where can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - - "microchip,-aic" where can be "sam9x60" + - "microchip,-aic" where can be "sam9x60", "sam9x7" =20 - interrupt-controller: Identifies the node as an interrupt controller. - #interrupt-cells: The number of cells to define the interrupts. It shoul= d be 3. --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B7C3C7EE24 for ; Sat, 3 Jun 2023 20:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231810AbjFCUIw (ORCPT ); Sat, 3 Jun 2023 16:08:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231144AbjFCUID (ORCPT ); Sat, 3 Jun 2023 16:08:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AAF310DC; Sat, 3 Jun 2023 13:07:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822856; x=1717358856; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xbMFJDkuvSAVzLORTJHW0ZL04qI1N0hFjbaAsJ5qgb0=; b=nBqI7VWyXXR62muB4JtVZap2kyYltMqU5qPeeGyKZFkVVetB4fccGb/A DpWd3dOqdmJc0OQ4YregWn9IUddlcOcf7VBjWNvGBbFvPJ7OP6uMBumNH m7j1mA3SPZQuhiPmZKwbRxs92DjKIRhpVOPAO0oadG9Gtgvknjrg8GFrz pXFmbKMZQCG1Py3VoI82iueE0JGotbIOhyi+9a92QU+09DI9LGmS0kAst p7yYhHYMt9RJKqH7v5umIaY+ryYmALNCLsssc6fLM/ZaKLYVcGjkB+/C+ nvUSJ/ZLqL8eHgLpAsTRQN5yTRZ0dRFw3eAHH1ZdhEl/Xur7XmVFlh0dy A==; X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="214485489" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:06:37 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:06:35 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:06:23 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 16/21] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sun, 4 Jun 2023 01:32:38 +0530 Message-ID: <20230603200243.243878-17-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran --- drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-a= ic5.c index 145535bd7560..bab11900f3ef 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __in= itconst =3D { { .compatible =3D "atmel,sama5d3", .data =3D sama5d3_aic_irq_fixup }, { .compatible =3D "atmel,sama5d4", .data =3D sama5d3_aic_irq_fixup }, { .compatible =3D "microchip,sam9x60", .data =3D sam9x60_aic_irq_fixup }, + { .compatible =3D "microchip,sam9x7", .data =3D sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; =20 @@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_n= ode *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_ini= t); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init); --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62780C77B7A for ; Sat, 3 Jun 2023 20:09:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232032AbjFCUJP (ORCPT ); Sat, 3 Jun 2023 16:09:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231981AbjFCUIq (ORCPT ); Sat, 3 Jun 2023 16:08:46 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 209A5E72; Sat, 3 Jun 2023 13:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; 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Sat, 3 Jun 2023 13:06:48 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:06:36 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Date: Sun, 4 Jun 2023 01:32:39 +0530 Message-ID: <20230603200243.243878-18-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use sam9x7 pmc's compatible to lookup for in the SHDWC driver Signed-off-by: Varshini Rajendran --- drivers/power/reset/at91-sama5d2_shdwc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset= /at91-sama5d2_shdwc.c index d8ecffe72f16..d0f29b99f25e 100644 --- a/drivers/power/reset/at91-sama5d2_shdwc.c +++ b/drivers/power/reset/at91-sama5d2_shdwc.c @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] =3D { { .compatible =3D "atmel,sama5d2-pmc" }, { .compatible =3D "microchip,sam9x60-pmc" }, { .compatible =3D "microchip,sama7g5-pmc" }, + { .compatible =3D "microchip,sam9x7-pmc" }, { /* Sentinel. */ } }; =20 --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E19AEC7EE2D for ; Sat, 3 Jun 2023 20:09:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231540AbjFCUJH (ORCPT ); Sat, 3 Jun 2023 16:09:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231557AbjFCUIo (ORCPT ); Sat, 3 Jun 2023 16:08:44 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DB42E54; Sat, 3 Jun 2023 13:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685822869; x=1717358869; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; 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Sat, 3 Jun 2023 13:06:48 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 18/21] power: reset: at91-reset: add reset support for sam9x7 soc Date: Sun, 4 Jun 2023 01:32:40 +0530 Message-ID: <20230603200243.243878-19-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add power reset support for SAM9X7 SoC Signed-off-by: Varshini Rajendran --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8c87eeda0fec..6c4ad81a0059 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF config POWER_RESET_AT91_RESET tristate "Atmel AT91 reset driver" depends on ARCH_AT91 - default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5 + default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports restart for Atmel AT91SAM9 and SAMA5 SoCs --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAC66C7EE32 for ; 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X-IronPort-AV: E=Sophos;i="6.00,216,1681196400"; d="scan'208";a="216104659" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Jun 2023 13:07:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Sat, 3 Jun 2023 13:07:14 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Sat, 3 Jun 2023 13:07:01 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH 19/21] power: reset: at91-reset: add sdhwc support for sam9x7 soc Date: Sun, 4 Jun 2023 01:32:41 +0530 Message-ID: <20230603200243.243878-20-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230603200243.243878-1-varshini.rajendran@microchip.com> References: <20230603200243.243878-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add shutdown controller support for SAM9X7 SoC Signed-off-by: Varshini Rajendran --- drivers/power/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 6c4ad81a0059..59459f5abbed 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET config POWER_RESET_AT91_SAMA5D2_SHDWC tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" depends on ARCH_AT91 - default SOC_SAM9X60 || SOC_SAMA5 + default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5 help This driver supports the alternate shutdown controller for some Atmel SAMA5 SoCs. It is present for example on SAMA5D2 SoC. --=20 2.25.1 From nobody Sun Feb 8 01:51:59 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A12B2C77B7A for ; Sat, 3 Jun 2023 20:09:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233276AbjFCUJ3 (ORCPT ); Sat, 3 Jun 2023 16:09:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232334AbjFCUIt (ORCPT ); Sat, 3 Jun 2023 16:08:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1852610FA; Sat, 3 Jun 2023 13:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; 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charset="utf-8" From: Nicolas Ferre Add support for GMAC in sam9x7 SoC family Signed-off-by: Varshini Rajendran Signed-off-by: Nicolas Ferre --- drivers/net/ethernet/cadence/macb_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/etherne= t/cadence/macb_main.c index 29a1199dad14..609c8e9305ba 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] =3D { { .compatible =3D "microchip,mpfs-macb", .data =3D &mpfs_config }, { .compatible =3D "microchip,sama7g5-gem", .data =3D &sama7g5_gem_config = }, { .compatible =3D "microchip,sama7g5-emac", .data =3D &sama7g5_emac_confi= g }, + { .compatible =3D "microchip,sam9x7-gem", .data =3D &sama7g5_gem_config }, { .compatible =3D "xlnx,zynqmp-gem", .data =3D &zynqmp_config}, { .compatible =3D "xlnx,zynq-gem", .data =3D &zynq_config }, { .compatible =3D "xlnx,versal-gem", .data =3D &versal_config}, --=20 2.25.1