From nobody Sat Apr 27 19:26:15 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18561C7EE2C for ; Fri, 2 Jun 2023 22:12:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236639AbjFBWMo (ORCPT ); Fri, 2 Jun 2023 18:12:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236565AbjFBWMm (ORCPT ); Fri, 2 Jun 2023 18:12:42 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7792E1BC for ; Fri, 2 Jun 2023 15:12:39 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba8337ade1cso3507060276.2 for ; Fri, 02 Jun 2023 15:12:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1685743958; x=1688335958; h=cc:to:from:subject:message-id:mime-version:date:reply-to:from:to:cc :subject:date:message-id:reply-to; bh=hZOQLIvJzczYTMAnaTGjzB0ofTaMaErv1XOCluG82ws=; b=ztnEwzy36DzIiYsf21ckOGWKoNk9x0+aF0krJRVhEGILD6FboIXDsRdHNE4nHzs8yQ D0nQnrSycvryY8KmsmF2B9P+c4iKhgxXfpMIAYDhOOw8Z3YfjvifOVAHHXtSc+VA4lcv vtJB58g21yx16+MjcUO0PWPLRYaen/R1GkwQ2R5DygvBCHRATnuSJUlx9qzrWJAfKbuJ PDq3fVh+dV2cn7B7iX8gv4dOVqZwH8Jk56seTtG571ZyY1FT4iGz8sB+Ge3BmXFEKay0 2jChpUvDjsXGJDyGTqf9E4tDl+OsuY07liagomRKpZ9cdyEwbNKENiZZMzwTBN9qtJQx Dnzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685743958; x=1688335958; h=cc:to:from:subject:message-id:mime-version:date:reply-to :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hZOQLIvJzczYTMAnaTGjzB0ofTaMaErv1XOCluG82ws=; b=Fto3IqZIGnuSZ5EuwUD/YOi+0gn2HboQXDN+phz2RgH+q2PcpSjmlA/UBRLkYXJ+FL /hzMFWFtqfFZ4CR9D2Qj8h4O9q2lbkIDtBHlGC3R8EvQ0xAVEvoh9JWsdrV/xDS3WDeZ H/v9RwPq9M2aQVevQVAu3n1R2tJ5Gcjx88CVwhpKeIiGVkpjAQNxpC4ah85sbIipMKEm YH1e1ZlHvilRxXYJju2SKxYQOY69HXYa4Sz89lXjLUVgo9RUQH4dInp9jO4qj3i19BdQ kZ7WeSuQOEqPJHdS+TANOuesZo2tYngideqvmJJPEcSg1NtX/H6fHhvWBKGc0pn+BsH2 +A7A== X-Gm-Message-State: AC+VfDydlph/mGYMeyFpJ+xkvXxYUCEkEor6W8cIyyqwjsgVjBlbNeC5 vPne6xg+U2BWSHPxN9LcV6W4vvxs46E= X-Google-Smtp-Source: ACHHUZ5kEM4UotGbjNhuGYnPNZSPFcZdv+PhWsaBh77AzL3xpMn6mZn9HFXaERTjVE4vBhdvz3jiI7Tpz7A= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:728:b0:ba1:d0:7f7c with SMTP id l8-20020a056902072800b00ba100d07f7cmr1667909ybt.2.1685743958805; Fri, 02 Jun 2023 15:12:38 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 2 Jun 2023 15:12:36 -0700 Mime-Version: 1.0 X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog Message-ID: <20230602221236.952888-1-seanjc@google.com> Subject: [PATCH] KVM: x86/pmu: Rename global_ovf_ctrl_mask to global_status_mask From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Like Xu Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename global_ovf_ctrl_mask to global_status_mask to avoid confusion now that Intel has renamed GLOBAL_OVF_CTRL to GLOBAL_STATUS_RESET in PMU v4. GLOBAL_OVF_CTRL and GLOBAL_STATUS_RESET are the same MSR index, i.e. are just different names for the same thing, but the SDM provides different entries in the IA-32 Architectural MSRs table, which gets really confusing when looking at PMU v4 definitions since it *looks* like GLOBAL_STATUS has bits that don't exist in GLOBAL_OVF_CTRL, but in reality the bits are simply defined in the GLOBAL_STATUS_RESET entry. No functional change intended. Cc: Like Xu Signed-off-by: Sean Christopherson --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/vmx/pmu_intel.c | 18 ++++++++++++++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index fb9d1f2d6136..28bd38303d70 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -523,7 +523,7 @@ struct kvm_pmu { u64 global_status; u64 counter_bitmask[2]; u64 global_ctrl_mask; - u64 global_ovf_ctrl_mask; + u64 global_status_mask; u64 reserved_bits; u64 raw_event_mask; struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC]; diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 741efe2c497b..fb96cbfc9ae8 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -427,7 +427,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) } break; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - if (data & pmu->global_ovf_ctrl_mask) + /* + * GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in + * GLOBAL_STATUS, and so the set of reserved bits is the same. + */ + if (data & pmu->global_status_mask) return 1; =20 if (!msr_info->host_initiated) @@ -531,7 +535,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->reserved_bits =3D 0xffffffff00200000ull; pmu->raw_event_mask =3D X86_RAW_EVENT_MASK; pmu->global_ctrl_mask =3D ~0ull; - pmu->global_ovf_ctrl_mask =3D ~0ull; + pmu->global_status_mask =3D ~0ull; pmu->fixed_ctr_ctrl_mask =3D ~0ull; pmu->pebs_enable_mask =3D ~0ull; pmu->pebs_data_cfg_mask =3D ~0ull; @@ -585,11 +589,17 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) counter_mask =3D ~(((1ull << pmu->nr_arch_gp_counters) - 1) | (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED)); pmu->global_ctrl_mask =3D counter_mask; - pmu->global_ovf_ctrl_mask =3D pmu->global_ctrl_mask + + /* + * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET) + * share reserved bit definitions. The kernel just happens to use + * OVF_CTRL for the names. + */ + pmu->global_status_mask =3D pmu->global_ctrl_mask & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF | MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD); if (vmx_pt_mode_is_host_guest()) - pmu->global_ovf_ctrl_mask &=3D + pmu->global_status_mask &=3D ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; =20 entry =3D kvm_find_cpuid_entry_index(vcpu, 7, 0); base-commit: b9846a698c9aff4eb2214a06ac83638ad098f33f --=20 2.41.0.rc2.161.g9c6817b8e7-goog