From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C36F9C7EE2C for ; Fri, 2 Jun 2023 11:48:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234747AbjFBLs2 (ORCPT ); Fri, 2 Jun 2023 07:48:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234946AbjFBLsX (ORCPT ); Fri, 2 Jun 2023 07:48:23 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23965E40 for ; Fri, 2 Jun 2023 04:48:17 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-974265a1a40so687573366b.0 for ; Fri, 02 Jun 2023 04:48:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685706496; x=1688298496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r0zU7Dw1WndhbqaoD+kPCUAlyhQSbREoS3q5/cnYVdE=; b=xU2SB4snMyVjG1gINs7Xdv/dfK4UPJmAHTyyr5SeJBDQgBKiEs+CsENPuT0OzSEXdB rvE3NE/8URXDdPboCVvc1PlELSiVNTxO+M7BHpe8+FjSHUZPE76cGnST4v+evNMiqTrg n9qzv9WySwDIBJbexI8HTuWbssvRRGnaz4iX4o9hr7Ermijj35iiuORMzHShKOJdqpl1 co2HCPuyVMvo1hjSW4LA9421Ha1SL5xxej6xAh18ykY9RB+bFCJR+dXd0BudJNhMFMZq GxLywVorFzstauhTfthR0INXveF+1K8P3g0ms7mMuf7dz0q8whfT1Wq83NjE0xJiCIzW ugig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685706496; x=1688298496; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r0zU7Dw1WndhbqaoD+kPCUAlyhQSbREoS3q5/cnYVdE=; b=JYRVhZeoHPrpYjt/d7w1/NUhLMv2T8TjIBpr/q8Y68ww73+syTonGyHaZirez7DoB6 3fc/JFsX0j4Gr0y88vrYLEzy7vNKdgIzE6VHGCy4hoedkhy0elEX9Q4RVZaJSqToNqae zsKeA17uCc0ithHS1Z7k70L45xsrP9ku89Pg7LFVLKjQsMFOY2MXRAgDZKH1ahC62jpq L9S6S3nZ6ifuhBjnvzelvrozaALCTIzQY8NLtp9B70qIQaHY+2INwq8uftN9mff0KFia dKACVt59OoS0J25hWjpENq0YGQpUiFAe67wK+R3CGI3Sh1XG7ivFD7N9F4wgJvKXRM5y 2zPw== X-Gm-Message-State: AC+VfDzNwdTaKVvWWGCSTMAFiuA2JBJ9QoyoMv8xDdOVoanYZRPSDbZl qahC06PFDi6OKzSTDmCW+HCT X-Google-Smtp-Source: ACHHUZ7LI2+IlH59pt8ko3MiFznl/5VBuS17O3Y0YcYRY+ASQi14xiH7FxVxi4thT8WjnUJ3xeofWg== X-Received: by 2002:a17:907:1c88:b0:976:f2e:ad6a with SMTP id nb8-20020a1709071c8800b009760f2ead6amr50921ejc.28.1685706496436; Fri, 02 Jun 2023 04:48:16 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:16 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 1/9] PCI: endpoint: Add missing documentation about the MSI/MSI-X range Date: Fri, 2 Jun 2023 17:17:48 +0530 Message-Id: <20230602114756.36586-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Both pci_epc_raise_irq() and pci_epc_map_msi_irq() APIs expects the MSI/MSI-X vectors to start from 1 but it is not documented. Add the range info to the kdoc of the APIs to make it clear. Fixes: 5e8cb4033807 ("PCI: endpoint: Add EP core layer to enable EP control= ler and EP functions") Fixes: 87d5972e476f ("PCI: endpoint: Add pci_epc_ops to map MSI IRQ") Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index 46c9a5c3ca14..0cf602c83d4a 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -213,7 +213,7 @@ EXPORT_SYMBOL_GPL(pci_epc_start); * @func_no: the physical endpoint function number in the EPC device * @vfunc_no: the virtual endpoint function number in the physical function * @type: specify the type of interrupt; legacy, MSI or MSI-X - * @interrupt_num: the MSI or MSI-X interrupt number + * @interrupt_num: the MSI or MSI-X interrupt number with range (1-N) * * Invoke to raise an legacy, MSI or MSI-X interrupt */ @@ -246,7 +246,7 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq); * @func_no: the physical endpoint function number in the EPC device * @vfunc_no: the virtual endpoint function number in the physical function * @phys_addr: the physical address of the outbound region - * @interrupt_num: the MSI interrupt number + * @interrupt_num: the MSI interrupt number with range (1-N) * @entry_size: Size of Outbound address region for each interrupt * @msi_data: the data that should be written in order to raise MSI interr= upt * with interrupt number as 'interrupt num' --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6AE5C7EE29 for ; Fri, 2 Jun 2023 11:48:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234939AbjFBLsh (ORCPT ); Fri, 2 Jun 2023 07:48:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234774AbjFBLsf (ORCPT ); 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Fri, 02 Jun 2023 04:48:21 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:20 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 2/9] PCI: endpoint: Pass EPF device ID to the probe function Date: Fri, 2 Jun 2023 17:17:49 +0530 Message-Id: <20230602114756.36586-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the EPF probe function doesn't get the device ID argument needed to correctly identify the device table ID of the EPF device. When multiple entries are added to the "struct pci_epf_device_id" table, the probe function needs to identify the correct one. This is achieved by modifying the pci_epf_match_id() function to return the match ID pointer and passing it to the driver's probe function. pci_epf_device_match() function can return bool based on the return value of pci_epf_match_id(). Reviewed-by: Kishon Vijay Abraham I Signed-off-by: Manivannan Sadhasivam Reviewed-by: Damien Le Moal --- drivers/pci/endpoint/functions/pci-epf-ntb.c | 3 ++- drivers/pci/endpoint/functions/pci-epf-test.c | 2 +- drivers/pci/endpoint/functions/pci-epf-vntb.c | 2 +- drivers/pci/endpoint/pci-epf-core.c | 18 +++++++++++------- include/linux/pci-epf.h | 4 +++- 5 files changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-ntb.c b/drivers/pci/end= point/functions/pci-epf-ntb.c index 9a00448c7e61..980b4ecf19a2 100644 --- a/drivers/pci/endpoint/functions/pci-epf-ntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-ntb.c @@ -2075,11 +2075,12 @@ static struct config_group *epf_ntb_add_cfs(struct = pci_epf *epf, /** * epf_ntb_probe() - Probe NTB function driver * @epf: NTB endpoint function device + * @id: NTB endpoint function device ID * * Probe NTB function driver when endpoint function bus detects a NTB * endpoint function. */ -static int epf_ntb_probe(struct pci_epf *epf) +static int epf_ntb_probe(struct pci_epf *epf, const struct pci_epf_device_= id *id) { struct epf_ntb *ntb; struct device *dev; diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/en= dpoint/functions/pci-epf-test.c index 0f9d2ec822ac..d5fcc78a5b73 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -980,7 +980,7 @@ static const struct pci_epf_device_id pci_epf_test_ids[= ] =3D { {}, }; =20 -static int pci_epf_test_probe(struct pci_epf *epf) +static int pci_epf_test_probe(struct pci_epf *epf, const struct pci_epf_de= vice_id *id) { struct pci_epf_test *epf_test; struct device *dev =3D &epf->dev; diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/en= dpoint/functions/pci-epf-vntb.c index b7c7a8af99f4..122eb7a12028 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -1401,7 +1401,7 @@ static struct pci_epf_ops epf_ntb_ops =3D { * * Returns: Zero for success, or an error code in case of failure */ -static int epf_ntb_probe(struct pci_epf *epf) +static int epf_ntb_probe(struct pci_epf *epf, const struct pci_epf_device_= id *id) { struct epf_ntb *ntb; struct device *dev; diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci= -epf-core.c index 2036e38be093..ea6e0aef0bb3 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -493,16 +493,16 @@ static const struct device_type pci_epf_type =3D { .release =3D pci_epf_dev_release, }; =20 -static int -pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf = *epf) +static const struct pci_epf_device_id +*pci_epf_match_id(const struct pci_epf_device_id *id, const struct pci_epf= *epf) { while (id->name[0]) { if (strcmp(epf->name, id->name) =3D=3D 0) - return true; + return id; id++; } =20 - return false; + return NULL; } =20 static int pci_epf_device_match(struct device *dev, struct device_driver *= drv) @@ -510,8 +510,12 @@ static int pci_epf_device_match(struct device *dev, st= ruct device_driver *drv) struct pci_epf *epf =3D to_pci_epf(dev); struct pci_epf_driver *driver =3D to_pci_epf_driver(drv); =20 - if (driver->id_table) - return pci_epf_match_id(driver->id_table, epf); + if (driver->id_table) { + if (pci_epf_match_id(driver->id_table, epf)) + return true; + else + return false; + } =20 return !strcmp(epf->name, drv->name); } @@ -526,7 +530,7 @@ static int pci_epf_device_probe(struct device *dev) =20 epf->driver =3D driver; =20 - return driver->probe(epf); + return driver->probe(epf, pci_epf_match_id(driver->id_table, epf)); } =20 static void pci_epf_device_remove(struct device *dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index a215dc8ce693..bc613f0df7e3 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -89,7 +89,7 @@ struct pci_epc_event_ops { * @id_table: identifies EPF devices for probing */ struct pci_epf_driver { - int (*probe)(struct pci_epf *epf); + int (*probe)(struct pci_epf *epf, const struct pci_epf_device_id *id); void (*remove)(struct pci_epf *epf); =20 struct device_driver driver; @@ -131,6 +131,7 @@ struct pci_epf_bar { * @epc: the EPC device to which this EPF device is bound * @epf_pf: the physical EPF device to which this virtual EPF device is bo= und * @driver: the EPF driver to which this EPF device is bound + * @id: Pointer to the EPF device ID * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc * @lock: mutex to protect pci_epf_ops * @sec_epc: the secondary EPC device to which this EPF device is bound @@ -158,6 +159,7 @@ struct pci_epf { struct pci_epc *epc; struct pci_epf *epf_pf; struct pci_epf_driver *driver; + const struct pci_epf_device_id *id; struct list_head list; /* mutex to protect against concurrent access of pci_epf_ops */ struct mutex lock; --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67072C7EE29 for ; Fri, 2 Jun 2023 11:49:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234971AbjFBLtD (ORCPT ); Fri, 2 Jun 2023 07:49:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235010AbjFBLsu (ORCPT ); Fri, 2 Jun 2023 07:48:50 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4549FE4A for ; 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charset="utf-8" When the EPC is started or stopped multiple times from configfs, just return -EALREADY. There is no need to call the EPC start/stop functions in those cases. Reviewed-by: Kishon Vijay Abraham I Signed-off-by: Manivannan Sadhasivam Reviewed-by: Damien Le Moal --- drivers/pci/endpoint/pci-ep-cfs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-e= p-cfs.c index 4b8ac0ac84d5..7e0e430e4ceb 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -178,6 +178,9 @@ static ssize_t pci_epc_start_store(struct config_item *= item, const char *page, if (kstrtobool(page, &start) < 0) return -EINVAL; =20 + if (start =3D=3D epc_group->start) + return -EALREADY; + if (!start) { pci_epc_stop(epc); epc_group->start =3D 0; --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D01BFC7EE29 for ; Fri, 2 Jun 2023 11:49:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235391AbjFBLtj (ORCPT ); Fri, 2 Jun 2023 07:49:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235248AbjFBLt3 (ORCPT ); Fri, 2 Jun 2023 07:49:29 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA02110F0 for ; Fri, 2 Jun 2023 04:48:58 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-96f5d651170so684131266b.1 for ; Fri, 02 Jun 2023 04:48:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685706511; x=1688298511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zqb+azKNXB55HXMybpmBlfsJ54xPwbKSsj/GKkm5OMs=; b=CmDuMRPYvAeuG4xG1voNSkDADQ4mSy35RnYW8mibureiXJUAdvu5Cy5191oz2MB2Xp A+9L6ziZqxZpLbFEbwsHaej1rbDIc5r5HYpnzHHKr6u12Hw/xA4Li7k6SKBdpmJ9KqED ADJ3khYZIhGj5zBvTrS8F8v8yI0aaCmrMc6GT8J6qKfS0hZsWhsg172TaXBoUnjDsweA Ct3IgNC2SBXX2B3WJ4AlFBCisJfI1TNDORzN7qRmYX/zel88Kz6KRH7V80ETyy443chQ 9YathxSaJn3eQn+nsQ2BPKRTZk0WT3A1pSmlYTiPvQerDsLUY0cbAlhB6FE7ANQfrnXZ lcTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685706511; x=1688298511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zqb+azKNXB55HXMybpmBlfsJ54xPwbKSsj/GKkm5OMs=; b=REgUgixxopAYeoDqblk00lGNGpNXwc91G5ijveVoqI8su36f/nmpJpdLUVxsA5RLIu l/9YXk1+cJHPwPFu+Ldsw73+JpwqWQqZmXQalk87QPuJ38bRj5htsFL6AKdtU9DtNhHP QOJs9h9jDyN8iMh5ZXWw9dBz2UiUrpl3k4Vi6CekhybloUletoofh0ruiosXAN0XOiQK JtMR3DgxJKpDERHL+zQV2f4sPvUUD04D2he1K19OI1LFTR9kJcspG9sHN32WxlmJOcJT ko3ZvaCdXvqotctnD+7XWIXcJgizDNdxqczawMT6Vr3djs5dLRtSv6ut4WFxpIUUob5t pbWg== X-Gm-Message-State: AC+VfDy8QVx7oGoMCckmyl3MLNxE4G0P6V3W0dnoBy7R8qk5y/uMJW+B PdU96Y+XjpJ0xRVhGZfKlUpa X-Google-Smtp-Source: ACHHUZ4dplUnJ2Tud7HGQSzoROiGmmBYfraoLDoPBVt48ClU40rqY8euFPInRMUXM/jWwRSenMceZw== X-Received: by 2002:a17:906:9756:b0:966:1bf2:2af5 with SMTP id o22-20020a170906975600b009661bf22af5mr4455612ejy.22.1685706511417; Fri, 02 Jun 2023 04:48:31 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:31 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 4/9] PCI: endpoint: Add linkdown notifier support Date: Fri, 2 Jun 2023 17:17:51 +0530 Message-Id: <20230602114756.36586-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to notify the EPF device about the linkdown event from the EPC device. Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 26 ++++++++++++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 2 ++ 3 files changed, 29 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index 0cf602c83d4a..e0570b52698d 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -706,6 +706,32 @@ void pci_epc_linkup(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_linkup); =20 +/** + * pci_epc_linkdown() - Notify the EPF device that EPC device has dropped = the + * connection with the Root Complex. + * @epc: the EPC device which has dropped the link with the host + * + * Invoke to Notify the EPF device that the EPC device has dropped the + * connection with the Root Complex. + */ +void pci_epc_linkdown(struct pci_epc *epc) +{ + struct pci_epf *epf; + + if (!epc || IS_ERR(epc)) + return; + + mutex_lock(&epc->list_lock); + list_for_each_entry(epf, &epc->pci_epf, list) { + mutex_lock(&epf->lock); + if (epf->event_ops && epf->event_ops->link_down) + epf->event_ops->link_down(epf); + mutex_unlock(&epf->lock); + } + mutex_unlock(&epc->list_lock); +} +EXPORT_SYMBOL_GPL(pci_epc_linkdown); + /** * pci_epc_init_notify() - Notify the EPF device that EPC device's core * initialization is completed. diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 301bb0e53707..63a6cc5e5282 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -203,6 +203,7 @@ void pci_epc_destroy(struct pci_epc *epc); int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); void pci_epc_linkup(struct pci_epc *epc); +void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index bc613f0df7e3..f8e5a63d0c83 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -71,10 +71,12 @@ struct pci_epf_ops { * struct pci_epf_event_ops - Callbacks for capturing the EPC events * @core_init: Callback for the EPC initialization complete event * @link_up: Callback for the EPC link up event + * @link_down: Callback for the EPC link down event */ struct pci_epc_event_ops { int (*core_init)(struct pci_epf *epf); int (*link_up)(struct pci_epf *epf); + int (*link_down)(struct pci_epf *epf); }; =20 /** --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C178C7EE32 for ; Fri, 2 Jun 2023 11:49:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235427AbjFBLt4 (ORCPT ); Fri, 2 Jun 2023 07:49:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235374AbjFBLth (ORCPT ); Fri, 2 Jun 2023 07:49:37 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C080E4D for ; Fri, 2 Jun 2023 04:49:08 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-5149e65c218so2865456a12.2 for ; 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charset="utf-8" Add support to notify the EPF device about the Bus Master Enable (BME) event received by the EPC device from the Root complex. Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 26 ++++++++++++++++++++++++++ include/linux/pci-epc.h | 1 + include/linux/pci-epf.h | 2 ++ 3 files changed, 29 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index e0570b52698d..6c54fa5684d2 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -758,6 +758,32 @@ void pci_epc_init_notify(struct pci_epc *epc) } EXPORT_SYMBOL_GPL(pci_epc_init_notify); =20 +/** + * pci_epc_bme_notify() - Notify the EPF device that the EPC device has re= ceived + * the BME event from the Root complex + * @epc: the EPC device that received the BME event + * + * Invoke to Notify the EPF device that the EPC device has received the Bus + * Master Enable (BME) event from the Root complex + */ +void pci_epc_bme_notify(struct pci_epc *epc) +{ + struct pci_epf *epf; + + if (!epc || IS_ERR(epc)) + return; + + mutex_lock(&epc->list_lock); + list_for_each_entry(epf, &epc->pci_epf, list) { + mutex_lock(&epf->lock); + if (epf->event_ops && epf->event_ops->bme) + epf->event_ops->bme(epf); + mutex_unlock(&epf->lock); + } + mutex_unlock(&epc->list_lock); +} +EXPORT_SYMBOL_GPL(pci_epc_bme_notify); + /** * pci_epc_destroy() - destroy the EPC device * @epc: the EPC device that has to be destroyed diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 63a6cc5e5282..5cb694031072 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -205,6 +205,7 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf= *epf, void pci_epc_linkup(struct pci_epc *epc); void pci_epc_linkdown(struct pci_epc *epc); void pci_epc_init_notify(struct pci_epc *epc); +void pci_epc_bme_notify(struct pci_epc *epc); void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf, enum pci_epc_interface_type type); int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index f8e5a63d0c83..f34b3b32a0e7 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -72,11 +72,13 @@ struct pci_epf_ops { * @core_init: Callback for the EPC initialization complete event * @link_up: Callback for the EPC link up event * @link_down: Callback for the EPC link down event + * @bme: Callback for the EPC BME (Bus Master Enable) event */ struct pci_epc_event_ops { int (*core_init)(struct pci_epf *epf); int (*link_up)(struct pci_epf *epf); int (*link_down)(struct pci_epf *epf); + int (*bme)(struct pci_epf *epf); }; =20 /** --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9820C7EE24 for ; Fri, 2 Jun 2023 11:50:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235694AbjFBLuv (ORCPT ); Fri, 2 Jun 2023 07:50:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235416AbjFBLtk (ORCPT ); Fri, 2 Jun 2023 07:49:40 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13DD0E79 for ; Fri, 2 Jun 2023 04:49:11 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-973f78329e3so290573766b.3 for ; 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charset="utf-8" Add support to pass Link down notification to Endpoint function driver so that the LINK_DOWN event can be processed by the function. Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 19b32839ea26..4ce01ff7527c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -569,6 +569,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int i= rq, void *data) if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) { dev_dbg(dev, "Received Linkdown event\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_DOWN; + pci_epc_linkdown(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_ENABLED; --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77BE6C7EE2C for ; Fri, 2 Jun 2023 11:50:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235266AbjFBLt7 (ORCPT ); Fri, 2 Jun 2023 07:49:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235171AbjFBLtm (ORCPT ); Fri, 2 Jun 2023 07:49:42 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860FCE4E for ; Fri, 2 Jun 2023 04:49:13 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-96f5d651170so684188266b.1 for ; Fri, 02 Jun 2023 04:49:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685706526; x=1688298526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/jN1DFdq3v+G4ZtKLRtAY1iZ3VaX7EJSiV3mNgkD3+0=; b=fgJ9d0gC66MmH9yZ6G/kQEzeBbcRAEGBdK81vpdKYumSID5QE+T1+pqhICpCetTOZT 413Vtx+Whyw1o2E0KyUi4n1HG1jT8YQ9jqeX/gR9tBUHoFsuSS8UfU0dy9QctLyANAyF g4AfX8656D76Vq0E4xKNAZWuh7XM4f4b4EBdZjBv0gBMoJgfHrHgiWAEUL+mXjQodif9 QwTYPpWY0KuYNGOVyV7oVZZriTGQOnGkKKbEke+ETehknAhpqjVrbdzd2nstuVhGVVRI +IRRW98+ONYrtLyYa1MwPeE9WXIt9et+dq+ZUiZvg64gErsYBy98KxBEJYq3MJlnevnO IqsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685706526; x=1688298526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/jN1DFdq3v+G4ZtKLRtAY1iZ3VaX7EJSiV3mNgkD3+0=; b=jyAyNELXVGfRDwC5fl7bnO6Bwb79l+pPhXJhvhMrgZCR1T+wDJeie07dvrI/VO74OQ 76ZeDUpZwssYTtwu8Xyw7d0/wMptvVrR1QpMbBb2Z8AA0L4pKOochydfC97wMirkyiTg OhCowiXUmfBn23thuULuHGa+xMgOqfkcDASD5xAsCdA9Pa818wPGHJIQRmI4715doUxm nratAsyITanZzM1V+UFVklInT143Kjc6pK0VLWgeq55N4RF6XzyNIaSXud/UxAi37pQt 9szZ0VItLPZ9LaiM+Bh2vSvO4KobOHlXJZjTs1fZjJOkWBZb9YiQEJ+SVaz1rrBxUnDl rfsA== X-Gm-Message-State: AC+VfDwBgFoi7E7aTYH4RhFlxVCW5UcixXPYF737tTH3ibLPZv+NcKBs OHKCljeAweSrSP+Fx7az/cJg X-Google-Smtp-Source: ACHHUZ4R49ZdyNxhsTOQyfS6IO+unlD/2kxVmaZwdq0TDNSGMuepnDPZJzd0yLW3wXmeYJTdmiInhQ== X-Received: by 2002:a17:907:9709:b0:965:ae3a:52c8 with SMTP id jg9-20020a170907970900b00965ae3a52c8mr4168161ejc.32.1685706526634; Fri, 02 Jun 2023 04:48:46 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:46 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 7/9] PCI: qcom-ep: Add support for BME notification Date: Fri, 2 Jun 2023 17:17:54 +0530 Message-Id: <20230602114756.36586-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support to pass BME (Bus Master Enable) notification to Endpoint function driver so that the BME event can be processed by the function. Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index 4ce01ff7527c..1435f516d3f7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -573,6 +573,7 @@ static irqreturn_t qcom_pcie_ep_global_irq_thread(int i= rq, void *data) } else if (FIELD_GET(PARF_INT_ALL_BME, status)) { dev_dbg(dev, "Received BME event. Link is enabled!\n"); pcie_ep->link_status =3D QCOM_PCIE_EP_LINK_ENABLED; + pci_epc_bme_notify(pci->ep.epc); } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) { dev_dbg(dev, "Received PM Turn-off event! Entering L23\n"); val =3D readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6B9BC7EE24 for ; Fri, 2 Jun 2023 11:50:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235527AbjFBLuG (ORCPT ); Fri, 2 Jun 2023 07:50:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235437AbjFBLtr (ORCPT ); Fri, 2 Jun 2023 07:49:47 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67DCD10C4 for ; Fri, 2 Jun 2023 04:49:16 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-5147a478c38so2867533a12.0 for ; Fri, 02 Jun 2023 04:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685706531; x=1688298531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NjgpVSwib4nuNHZhdqCSk8pCl93HMUnG2C938yjE0+U=; b=LAq7P4MS+/yqmNpbVL0uPeBvicvoYLtU2xroR2Iuc/qKAasgicMvdhYy9aotLXol0X nQ/P6yooj5RLyoy5H/JE5sldqZjjzlCnUh4UtcVrl2mb27uCOaO02syL23E+D8H+LyZ+ vOsGRcQhSMmSAlJL/mDeBW0KBdgTrGSNok245LcnarMyWgI8GCQ4AxeImZ74J7a2z52v ZmsZV5ddjc08Rf8bK9csWwBQfGj27KAdm3HBxD2nv/I9U2mJ1/mRAbAywM/J0d61nWs3 KMTYWK7xAc+0zmbMnDtB6HsFtf4Igp04XdjyJP14ZBWWu1bQoKy5+nuc/7mOelDFTHK2 X9fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685706531; x=1688298531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NjgpVSwib4nuNHZhdqCSk8pCl93HMUnG2C938yjE0+U=; b=buHHvFhrJHxTAoOgl4Il/wfi9jXPWm0fKriLROkqvQQ27ubFG+bwZEhkGLKVnNXnsw xtU+h+VqQiTQGhX18Pd9TmJKsJoxtEobzix3Cymw+1jbLRRtXXrXHiBWTApLGvFihN7D 7M2Da7lYiGOgXN6zZqqV0TwT1URXskGEcqbI1cU2QZAXqgj4DA8U0wiWDk2j6KNf0KjE aBbwdLgfd5svILDhmohnZcC2X2pepzavzHc3fZpadxvoRSekn/kVRJejGZwM8urKbjuq v7aZIkfuLAjFQIJVfAQ2FGmI9gE9QtyfFEpZvAAuA4hwiNHbXFId0rFjo85OKHRoZQr+ ux6g== X-Gm-Message-State: AC+VfDz3zbqAqLwB81n2ge1FrZLNLr5ilgk4qj9y+sUMpuKuhEtdDkcX CRVp77LLGtjHtRDfxEttFOJpgePgsefUOQyq6w== X-Google-Smtp-Source: ACHHUZ4dfCXE8wfVDHdYs6Zk+wbd5/OsxKeKw7hKTDVdTSVI/ttCCg9ZBAn3V2Nu8oS4uetzHRvEsw== X-Received: by 2002:a17:907:3e86:b0:95e:d3f5:3d47 with SMTP id hs6-20020a1709073e8600b0095ed3f53d47mr11650939ejc.48.1685706531709; Fri, 02 Jun 2023 04:48:51 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:51 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 8/9] PCI: endpoint: Add PCI Endpoint function driver for MHI bus Date: Fri, 2 Jun 2023 17:17:55 +0530 Message-Id: <20230602114756.36586-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCI Endpoint driver for the Qualcomm MHI (Modem Host Interface) bus. The driver implements the MHI function over PCI in the endpoint device such as SDX55 modem. The MHI endpoint function driver acts as a controller driver for the MHI Endpoint stack and carries out all PCI related activities like mapping the host memory using iATU, triggering MSIs etc... Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Damien Le Moal Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/Kconfig | 10 + drivers/pci/endpoint/functions/Makefile | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 465 +++++++++++++++++++ 3 files changed, 476 insertions(+) create mode 100644 drivers/pci/endpoint/functions/pci-epf-mhi.c diff --git a/drivers/pci/endpoint/functions/Kconfig b/drivers/pci/endpoint/= functions/Kconfig index 9fd560886871..f5171b4fabbe 100644 --- a/drivers/pci/endpoint/functions/Kconfig +++ b/drivers/pci/endpoint/functions/Kconfig @@ -37,3 +37,13 @@ config PCI_EPF_VNTB between PCI Root Port and PCIe Endpoint. =20 If in doubt, say "N" to disable Endpoint NTB driver. + +config PCI_EPF_MHI + tristate "PCI Endpoint driver for MHI bus" + depends on PCI_ENDPOINT && MHI_BUS_EP + help + Enable this configuration option to enable the PCI Endpoint + driver for Modem Host Interface (MHI) bus in Qualcomm Endpoint + devices such as SDX55. + + If in doubt, say "N" to disable Endpoint driver for MHI bus. diff --git a/drivers/pci/endpoint/functions/Makefile b/drivers/pci/endpoint= /functions/Makefile index 5c13001deaba..696473fce50e 100644 --- a/drivers/pci/endpoint/functions/Makefile +++ b/drivers/pci/endpoint/functions/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_EPF_TEST) +=3D pci-epf-test.o obj-$(CONFIG_PCI_EPF_NTB) +=3D pci-epf-ntb.o obj-$(CONFIG_PCI_EPF_VNTB) +=3D pci-epf-vntb.o +obj-$(CONFIG_PCI_EPF_MHI) +=3D pci-epf-mhi.o diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c new file mode 100644 index 000000000000..0504ee13f692 --- /dev/null +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI EPF driver for MHI Endpoint devices + * + * Copyright (C) 2023 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include + +#define MHI_VERSION_1_0 0x01000000 + +#define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl) + +struct pci_epf_mhi_ep_info { + const struct mhi_ep_cntrl_config *config; + struct pci_epf_header *epf_header; + enum pci_barno bar_num; + u32 epf_flags; + u32 msi_count; + u32 mru; +}; + +#define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \ + { \ + .num =3D ch_num, \ + .name =3D ch_name, \ + .dir =3D direction, \ + } + +#define MHI_EP_CHANNEL_CONFIG_UL(ch_num, ch_name) \ + MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_TO_DEVICE) + +#define MHI_EP_CHANNEL_CONFIG_DL(ch_num, ch_name) \ + MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, DMA_FROM_DEVICE) + +static const struct mhi_ep_channel_config mhi_v1_channels[] =3D { + MHI_EP_CHANNEL_CONFIG_UL(0, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_DL(1, "LOOPBACK"), + MHI_EP_CHANNEL_CONFIG_UL(2, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_DL(3, "SAHARA"), + MHI_EP_CHANNEL_CONFIG_UL(4, "DIAG"), + MHI_EP_CHANNEL_CONFIG_DL(5, "DIAG"), + MHI_EP_CHANNEL_CONFIG_UL(6, "SSR"), + MHI_EP_CHANNEL_CONFIG_DL(7, "SSR"), + MHI_EP_CHANNEL_CONFIG_UL(8, "QDSS"), + MHI_EP_CHANNEL_CONFIG_DL(9, "QDSS"), + MHI_EP_CHANNEL_CONFIG_UL(10, "EFS"), + MHI_EP_CHANNEL_CONFIG_DL(11, "EFS"), + MHI_EP_CHANNEL_CONFIG_UL(12, "MBIM"), + MHI_EP_CHANNEL_CONFIG_DL(13, "MBIM"), + MHI_EP_CHANNEL_CONFIG_UL(14, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(15, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(16, "QMI"), + MHI_EP_CHANNEL_CONFIG_DL(17, "QMI"), + MHI_EP_CHANNEL_CONFIG_UL(18, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_DL(19, "IP-CTRL-1"), + MHI_EP_CHANNEL_CONFIG_UL(20, "IPCR"), + MHI_EP_CHANNEL_CONFIG_DL(21, "IPCR"), + MHI_EP_CHANNEL_CONFIG_UL(32, "DUN"), + MHI_EP_CHANNEL_CONFIG_DL(33, "DUN"), + MHI_EP_CHANNEL_CONFIG_UL(46, "IP_SW0"), + MHI_EP_CHANNEL_CONFIG_DL(47, "IP_SW0"), +}; + +static const struct mhi_ep_cntrl_config mhi_v1_config =3D { + .max_channels =3D 128, + .num_channels =3D ARRAY_SIZE(mhi_v1_channels), + .ch_cfg =3D mhi_v1_channels, + .mhi_version =3D MHI_VERSION_1_0, +}; + +static struct pci_epf_header sdx55_header =3D { + .vendorid =3D PCI_VENDOR_ID_QCOM, + .deviceid =3D 0x0306, + .baseclass_code =3D PCI_BASE_CLASS_COMMUNICATION, + .subclass_code =3D PCI_CLASS_COMMUNICATION_MODEM & 0xff, + .interrupt_pin =3D PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sdx55_info =3D { + .config =3D &mhi_v1_config, + .epf_header =3D &sdx55_header, + .bar_num =3D BAR_0, + .epf_flags =3D PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count =3D 32, + .mru =3D 0x8000, +}; + +struct pci_epf_mhi { + const struct pci_epf_mhi_ep_info *info; + struct mhi_ep_cntrl mhi_cntrl; + struct pci_epf *epf; + struct mutex lock; + void __iomem *mmio; + resource_size_t mmio_phys; + u32 mmio_size; + int irq; +}; + +static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci= _addr, + phys_addr_t *paddr, void __iomem **vaddr, + size_t offset, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + int ret; + + *vaddr =3D pci_epc_mem_alloc_addr(epc, paddr, size + offset); + if (!vaddr) + return -ENOMEM; + + ret =3D pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, *paddr, + pci_addr - offset, size + offset); + if (ret) { + pci_epc_mem_free_addr(epc, *paddr, *vaddr, size + offset); + return ret; + } + + return 0; +} + +static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_a= ddr, + phys_addr_t *paddr, void __iomem **vaddr, + size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct pci_epc *epc =3D epf_mhi->epf->epc; + size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + int ret; + + ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr, + offset, size); + if (ret) + return ret; + + *paddr =3D *paddr + offset; + *vaddr =3D *vaddr + offset; + + return 0; +} + +static void __pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, + u64 pci_addr, phys_addr_t paddr, + void __iomem *vaddr, size_t offset, + size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + + pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, paddr - offset); + pci_epc_mem_free_addr(epc, paddr - offset, vaddr - offset, + size + offset); +} + +static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci= _addr, + phys_addr_t paddr, void __iomem *vaddr, + size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + size_t offset =3D pci_addr & (epc->mem->window.page_size - 1); + + __pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset, + size); +} + +static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vect= or) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct pci_epf *epf =3D epf_mhi->epf; + struct pci_epc *epc =3D epf->epc; + + /* + * MHI supplies 0 based MSI vector but the API expects the vector to be + * 1 based, so we need to increment the vector by 1. + */ + pci_epc_raise_irq(epc, epf->func_no, epf->vfunc_no, PCI_EPC_IRQ_MSI, + vector + 1); +} + +static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 = from, + void *to, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + size_t offset =3D from % SZ_4K; + void __iomem *tre_buf; + phys_addr_t tre_phys; + int ret; + + mutex_lock(&epf_mhi->lock); + + ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, from, &tre_phys, &tre_buf, + offset, size); + if (ret) { + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_fromio(to, tre_buf + offset, size); + + __pci_epf_mhi_unmap_free(mhi_cntrl, from, tre_phys, tre_buf, offset, + size); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, + void *from, u64 to, size_t size) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + size_t offset =3D to % SZ_4K; + void __iomem *tre_buf; + phys_addr_t tre_phys; + int ret; + + mutex_lock(&epf_mhi->lock); + + ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, to, &tre_phys, &tre_buf, + offset, size); + if (ret) { + mutex_unlock(&epf_mhi->lock); + return ret; + } + + memcpy_toio(tre_buf + offset, from, size); + + __pci_epf_mhi_unmap_free(mhi_cntrl, to, tre_phys, tre_buf, offset, + size); + + mutex_unlock(&epf_mhi->lock); + + return 0; +} + +static int pci_epf_mhi_core_init(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; + struct pci_epf_bar *epf_bar =3D &epf->bar[info->bar_num]; + struct pci_epc *epc =3D epf->epc; + struct device *dev =3D &epf->dev; + int ret; + + epf_bar->phys_addr =3D epf_mhi->mmio_phys; + epf_bar->size =3D epf_mhi->mmio_size; + epf_bar->barno =3D info->bar_num; + epf_bar->flags =3D info->epf_flags; + ret =3D pci_epc_set_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); + if (ret) { + dev_err(dev, "Failed to set BAR: %d\n", ret); + return ret; + } + + ret =3D pci_epc_set_msi(epc, epf->func_no, epf->vfunc_no, + order_base_2(info->msi_count)); + if (ret) { + dev_err(dev, "Failed to set MSI configuration: %d\n", ret); + return ret; + } + + ret =3D pci_epc_write_header(epc, epf->func_no, epf->vfunc_no, + epf->header); + if (ret) { + dev_err(dev, "Failed to set Configuration header: %d\n", ret); + return ret; + } + + return 0; +} + +static int pci_epf_mhi_link_up(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + struct pci_epc *epc =3D epf->epc; + struct device *dev =3D &epf->dev; + int ret; + + mhi_cntrl->mmio =3D epf_mhi->mmio; + mhi_cntrl->irq =3D epf_mhi->irq; + mhi_cntrl->mru =3D info->mru; + + /* Assign the struct dev of PCI EP as MHI controller device */ + mhi_cntrl->cntrl_dev =3D epc->dev.parent; + mhi_cntrl->raise_irq =3D pci_epf_mhi_raise_irq; + mhi_cntrl->alloc_map =3D pci_epf_mhi_alloc_map; + mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; + mhi_cntrl->read_from_host =3D pci_epf_mhi_read_from_host; + mhi_cntrl->write_to_host =3D pci_epf_mhi_write_to_host; + + /* Register the MHI EP controller */ + ret =3D mhi_ep_register_controller(mhi_cntrl, info->config); + if (ret) { + dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); + return ret; + } + + return 0; +} + +static int pci_epf_mhi_link_down(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + + if (mhi_cntrl->mhi_dev) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + } + + return 0; +} + +static int pci_epf_mhi_bme(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + struct device *dev =3D &epf->dev; + int ret; + + /* + * Power up the MHI EP stack if link is up and stack is in power down + * state. + */ + if (!mhi_cntrl->enabled && mhi_cntrl->mhi_dev) { + ret =3D mhi_ep_power_up(mhi_cntrl); + if (ret) { + dev_err(dev, "Failed to power up MHI EP: %d\n", ret); + mhi_ep_unregister_controller(mhi_cntrl); + } + } + + return 0; +} + +static int pci_epf_mhi_bind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + struct pci_epc *epc =3D epf->epc; + struct platform_device *pdev =3D to_platform_device(epc->dev.parent); + struct device *dev =3D &epf->dev; + struct resource *res; + int ret; + + /* Get MMIO base address from Endpoint controller */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mmio"); + epf_mhi->mmio_phys =3D res->start; + epf_mhi->mmio_size =3D resource_size(res); + + epf_mhi->mmio =3D ioremap(epf_mhi->mmio_phys, epf_mhi->mmio_size); + if (IS_ERR(epf_mhi->mmio)) + return PTR_ERR(epf_mhi->mmio); + + ret =3D platform_get_irq_byname(pdev, "doorbell"); + if (ret < 0) { + dev_err(dev, "Failed to get Doorbell IRQ\n"); + iounmap(epf_mhi->mmio); + return ret; + } + + epf_mhi->irq =3D ret; + + return 0; +} + +static void pci_epf_mhi_unbind(struct pci_epf *epf) +{ + struct pci_epf_mhi *epf_mhi =3D epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info =3D epf_mhi->info; + struct pci_epf_bar *epf_bar =3D &epf->bar[info->bar_num]; + struct mhi_ep_cntrl *mhi_cntrl =3D &epf_mhi->mhi_cntrl; + struct pci_epc *epc =3D epf->epc; + + /* + * Forcefully power down the MHI EP stack. Only way to bring the MHI EP + * stack back to working state after successive bind is by getting BME + * from host. + */ + if (mhi_cntrl->mhi_dev) { + mhi_ep_power_down(mhi_cntrl); + mhi_ep_unregister_controller(mhi_cntrl); + } + + iounmap(epf_mhi->mmio); + pci_epc_clear_bar(epc, epf->func_no, epf->vfunc_no, epf_bar); +} + +static struct pci_epc_event_ops pci_epf_mhi_event_ops =3D { + .core_init =3D pci_epf_mhi_core_init, + .link_up =3D pci_epf_mhi_link_up, + .link_down =3D pci_epf_mhi_link_down, + .bme =3D pci_epf_mhi_bme, +}; + +static int pci_epf_mhi_probe(struct pci_epf *epf, + const struct pci_epf_device_id *id) +{ + struct pci_epf_mhi_ep_info *info =3D + (struct pci_epf_mhi_ep_info *)id->driver_data; + struct pci_epf_mhi *epf_mhi; + struct device *dev =3D &epf->dev; + + epf_mhi =3D devm_kzalloc(dev, sizeof(*epf_mhi), GFP_KERNEL); + if (!epf_mhi) + return -ENOMEM; + + epf->header =3D info->epf_header; + epf_mhi->info =3D info; + epf_mhi->epf =3D epf; + + epf->event_ops =3D &pci_epf_mhi_event_ops; + + mutex_init(&epf_mhi->lock); + + epf_set_drvdata(epf, epf_mhi); + + return 0; +} + +static const struct pci_epf_device_id pci_epf_mhi_ids[] =3D { + { + .name =3D "sdx55", .driver_data =3D (kernel_ulong_t)&sdx55_info, + }, + {}, +}; + +static struct pci_epf_ops pci_epf_mhi_ops =3D { + .unbind =3D pci_epf_mhi_unbind, + .bind =3D pci_epf_mhi_bind, +}; + +static struct pci_epf_driver pci_epf_mhi_driver =3D { + .driver.name =3D "pci_epf_mhi", + .probe =3D pci_epf_mhi_probe, + .id_table =3D pci_epf_mhi_ids, + .ops =3D &pci_epf_mhi_ops, + .owner =3D THIS_MODULE, +}; + +static int __init pci_epf_mhi_init(void) +{ + return pci_epf_register_driver(&pci_epf_mhi_driver); +} +module_init(pci_epf_mhi_init); + +static void __exit pci_epf_mhi_exit(void) +{ + pci_epf_unregister_driver(&pci_epf_mhi_driver); +} +module_exit(pci_epf_mhi_exit); + +MODULE_DESCRIPTION("PCI EPF driver for MHI Endpoint devices"); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon Feb 9 10:13:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79584C7EE29 for ; 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Fri, 02 Jun 2023 04:48:56 -0700 (PDT) Received: from localhost.localdomain ([117.217.186.79]) by smtp.gmail.com with ESMTPSA id qu25-20020a170907111900b00974530bb44dsm658924ejb.183.2023.06.02.04.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jun 2023 04:48:56 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dlemoal@kernel.org, Manivannan Sadhasivam Subject: [PATCH v6 9/9] MAINTAINERS: Add PCI MHI endpoint function driver under MHI bus Date: Fri, 2 Jun 2023 17:17:56 +0530 Message-Id: <20230602114756.36586-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> References: <20230602114756.36586-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PCI endpoint driver for MHI bus under the MHI bus entry in MAINTAINERS file. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Damien Le Moal --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 07625a47cf08..a4ac2d567334 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13630,6 +13630,7 @@ F: Documentation/ABI/stable/sysfs-bus-mhi F: Documentation/mhi/ F: drivers/bus/mhi/ F: drivers/net/mhi_* +F: drivers/pci/endpoint/functions/pci-epf-mhi.c F: include/linux/mhi.h =20 MICROBLAZE ARCHITECTURE --=20 2.25.1