From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A20A1C77B7E for ; Thu, 1 Jun 2023 21:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232834AbjFAVhM (ORCPT ); Thu, 1 Jun 2023 17:37:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232401AbjFAVhJ (ORCPT ); Thu, 1 Jun 2023 17:37:09 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AB6E19B for ; Thu, 1 Jun 2023 14:37:08 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-65292f79456so414788b3a.2 for ; Thu, 01 Jun 2023 14:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1685655427; x=1688247427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HjRakdb30yszASmxf/wTOyUnLRsbS0tBSqMyHI/mgmg=; b=BuG16CgsJZuRqklwqhtraGtO9mDBkjKRduhSYXiCHYmDshIggjlraGD2H9A4z6yorm wBu2dEQorFkxnRHLq3Cn+M+LkZWex3ajMYBEgSEujM238OkqShSG0aa2MrkveBlrCXC5 p6NW7FtAcuIScDFj5KSELcmbgvEEVbSabk3PI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685655427; x=1688247427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjRakdb30yszASmxf/wTOyUnLRsbS0tBSqMyHI/mgmg=; b=i9Kd6y9nYYJi94gxAISYewPWIy5HSmm33S2QV8Q3RLEzO7lWH4Yrbn2BtQdXshMOwH +KAb9zHKYqSwyIG1jlkCvLnPbPNGRi09ixmjsR8c1xDpNl2RchKA9zAxqVrgJpfNgaoG 1HttAbunsSW6bXL0Enn/F28/1jYPkf2DmnGAqKVVT4uesfuG/hQsnf94hOrW3CJznI+y g+hvpa3yrH8oaaH0qpDtmrR1OzZpXAWCKEkaTu9jeHnk/wkSuda9ldJ4rBv5kp2o7hod 47+V9+D5YmQuK1WzYHqW72auoUda+dS79TKnLa0fcjyGb9RFSL2ACLZ1xvT7nmJl8okn Ccug== X-Gm-Message-State: AC+VfDzSANHt6dZc74+pkklc4rBd9gyJXwvuNicZK6ePs8/hKHSGOuKu FLR5OR3k7tngwyQrCkiiO8DkLW3Y0IzUkvOpLgs= X-Google-Smtp-Source: ACHHUZ7X4JWk69pwtWfobliPNOJVZLyvG8aXSBcL3S43aA7yIba6lfLCLzZNDwufKt9JnCsD52RTZQ== X-Received: by 2002:a05:6a21:1647:b0:111:6a14:7d0 with SMTP id no7-20020a056a21164700b001116a1407d0mr6606398pzb.60.1685655427621; Thu, 01 Jun 2023 14:37:07 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:11b8:2d2:7e02:6bff]) by smtp.gmail.com with ESMTPSA id g22-20020aa78756000000b0064d48d98260sm5319534pfo.156.2023.06.01.14.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 14:37:07 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Masayoshi Mizuma , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v9 1/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Thu, 1 Jun 2023 14:31:45 -0700 Message-ID: <20230601143109.v9.1.I1223c11c88937bd0cbd9b086d4ef216985797302@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler update in case of SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Signed-off-by: Sumit Garg Reviewed-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- (no changes since v1) drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 0c6c1af9a5b7..ed37e02d4c5f 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -525,6 +525,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) static int gic_irq_nmi_setup(struct irq_data *d) { struct irq_desc *desc =3D irq_to_desc(d->irq); + u32 idx; =20 if (!gic_supports_nmi()) return -EINVAL; @@ -542,16 +543,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) return -EINVAL; =20 /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx =3D gic_get_ppi_index(d); =20 /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); desc->handle_irq =3D handle_percpu_devid_fasteoi_nmi; } - } else { + break; + default: desc->handle_irq =3D handle_fasteoi_nmi; + break; } =20 gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -562,6 +569,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) static void gic_irq_nmi_teardown(struct irq_data *d) { struct irq_desc *desc =3D irq_to_desc(d->irq); + u32 idx; =20 if (WARN_ON(!gic_supports_nmi())) return; @@ -579,14 +587,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) return; =20 /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx =3D gic_get_ppi_index(d); =20 /* Tearing down NMI, only switch handler for last NMI */ if (refcount_dec_and_test(&ppi_nmi_refs[idx])) desc->handle_irq =3D handle_percpu_devid_irq; - } else { + break; + default: desc->handle_irq =3D handle_fasteoi_irq; + break; } =20 gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -2001,6 +2015,7 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, =20 gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); =20 @@ -2013,8 +2028,6 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, gicv2m_init(handle, gic_data.domain); } =20 - gic_enable_nmi_support(); - return 0; =20 out_free: --=20 2.41.0.rc2.161.g9c6817b8e7-goog From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1EA9C7EE23 for ; Thu, 1 Jun 2023 21:37:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232402AbjFAVhQ (ORCPT ); Thu, 1 Jun 2023 17:37:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229618AbjFAVhL (ORCPT ); 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Thu, 01 Jun 2023 14:37:09 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Douglas Anderson , Frederic Weisbecker , "Gautham R. Shenoy" , Ingo Molnar , linux-kernel@vger.kernel.org Subject: [PATCH v9 2/7] arm64: idle: Tag the arm64 idle functions as __cpuidle Date: Thu, 1 Jun 2023 14:31:46 -0700 Message-ID: <20230601143109.v9.2.I4baba13e220bdd24d11400c67f137c35f07f82c7@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As per the (somewhat recent) comment before the definition of `__cpuidle`, the tag is like `noinstr` but also marks a function so it can be identified by cpu_in_idle(). Let'a add this. After doing this then when we dump stack traces of all processors using nmi_cpu_backtrace() then instead of getting useless backtraces we get things like: NMI backtrace for cpu N skipped: idling at cpu_do_idle+0x94/0x98 NOTE: this patch won't make cpu_in_idle() work perfectly for arm64, but it doesn't hurt and does catch some cases. Specifically an example that wasn't caught in my testing looked like this: gic_cpu_sys_reg_init+0x1f8/0x314 gic_cpu_pm_notifier+0x40/0x78 raw_notifier_call_chain+0x5c/0x134 cpu_pm_notify+0x38/0x64 cpu_pm_exit+0x20/0x2c psci_enter_idle_state+0x48/0x70 cpuidle_enter_state+0xb8/0x260 cpuidle_enter+0x44/0x5c do_idle+0x188/0x30c Signed-off-by: Douglas Anderson Acked-by: Mark Rutland --- Changes in v9: - Added to commit message that this doesn't catch all cases. Changes in v8: - "Tag the arm64 idle functions as __cpuidle" new for v8 arch/arm64/kernel/idle.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/idle.c b/arch/arm64/kernel/idle.c index c1125753fe9b..05cfb347ec26 100644 --- a/arch/arm64/kernel/idle.c +++ b/arch/arm64/kernel/idle.c @@ -20,7 +20,7 @@ * ensure that interrupts are not masked at the PMR (because the core will * not wake up if we block the wake up signal in the interrupt controller). */ -void noinstr cpu_do_idle(void) +void __cpuidle cpu_do_idle(void) { struct arm_cpuidle_irq_context context; =20 @@ -35,7 +35,7 @@ void noinstr cpu_do_idle(void) /* * This is our default idle handler. */ -void noinstr arch_cpu_idle(void) +void __cpuidle arch_cpu_idle(void) { /* * This should do all the clock switching and wait for interrupt --=20 2.41.0.rc2.161.g9c6817b8e7-goog From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80B2AC7EE23 for ; Thu, 1 Jun 2023 21:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232912AbjFAVhV (ORCPT ); Thu, 1 Jun 2023 17:37:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232836AbjFAVhO (ORCPT ); Thu, 1 Jun 2023 17:37:14 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC6DA19B for ; Thu, 1 Jun 2023 14:37:12 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-652a6cf1918so294693b3a.1 for ; Thu, 01 Jun 2023 14:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1685655432; x=1688247432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VxngL/nWZ9CvmSVXwg8pkM18NqkUW/hq6cWY9xHbU50=; b=aXtBMJsuEHVcZIKV7cLRpp9gJah5t0XCzX6mPhaAfDBP1dJ5ow0nIMbyHBqXyExXs/ iONAnH757E2JdGKhPAJpJ0T+0at+owiwzn2oTUIqycF0fDPlNwbji/qaAjIXJsOAh/DF EzBp3VrZJfcftxuQAMYGMNArokNyBuLgHVwN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685655432; x=1688247432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VxngL/nWZ9CvmSVXwg8pkM18NqkUW/hq6cWY9xHbU50=; b=SVQn6hBXGRfOonl/DPD7pkHCOaHdr7rPI+wxrCXo7vDj31hsNhbyc9nfrBzAx/gOOv fqZO1sgOOhamnc0Ab2YNSk7yszxUPfivagUr+frPJp1BjIkTirlCDHfFhRuDGbnsR3aS +5dRzDkEbNXoQI+oxI9dRJqLqUnqeTHeD9ch/f0aQzcxP/fU8ns61J2aTQNeSEri14aj EGATVzpGp989JXfB5CHggcRfNZlWzfX6Eu+fGfbPf/IxW024pWd2Rox++FNiX6AM0/E3 UtAKC4yqstTUYBnqgX0c+49pOjRyfNETnnqjQg6vSNomFYKhUtVrOS49pDMFXZ0PUReH 9wkw== X-Gm-Message-State: AC+VfDzgqjB8lS2ll9UGf82A1jcikuEanH/pzz1t/vPnYGk+Mmr8e6b1 4cxNxjYVnT5VQmGj4djmNlbDgw== X-Google-Smtp-Source: ACHHUZ5ef/rtEIYJxyW1OxKT1bSL//A95UwWPCmZBbTCdj36TOdor4jNJCZmCSlkwGKN3QsCenCWSg== X-Received: by 2002:a05:6a00:8ca:b0:64c:b45f:fc86 with SMTP id s10-20020a056a0008ca00b0064cb45ffc86mr10767019pfu.17.1685655432123; Thu, 01 Jun 2023 14:37:12 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:11b8:2d2:7e02:6bff]) by smtp.gmail.com with ESMTPSA id g22-20020aa78756000000b0064d48d98260sm5319534pfo.156.2023.06.01.14.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 14:37:11 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Douglas Anderson , Andrey Konovalov , Masahiro Yamada , linux-kernel@vger.kernel.org Subject: [PATCH v9 3/7] arm64: Add framework for a debug IPI Date: Thu, 1 Jun 2023 14:31:47 -0700 Message-ID: <20230601143109.v9.3.Ie6c132b96ebbbcddbf6954b9469ed40a6960343c@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg Introduce a framework for an IPI that will be used for debug purposes. The primary use case of this IPI will be to generate stack crawls on other CPUs, but it will also be used to round up CPUs for kgdb. When possible, we try to allocate this debug IPI as an NMI (or a pseudo NMI). If that fails (due to CONFIG, an incompatible interrupt controller, a quirk, missing the "irqchip.gicv3_pseudo_nmi=3D1" kernel parameter, etc) we fall back to a normal IPI. NOTE: hooking this up for CPU backtrace / kgdb will happen in a future patch, this just adds the framework. Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson --- I didn't get any feedback from v8 patch #10 [1], but I went ahead and folded it in here anyway since it really simplfies things. If people don't like the fallback to regular IPI, I can also undo it. [1] https://lore.kernel.org/r/20230419155341.v8.10.Ic3659997d6243139d0522fc= 3afcdfd88d7a5f030@changeid/ Changes in v9: - Fold in v8 patch #10 ("Fallback to a regular IPI if NMI isn't enabled") - Moved header file out of "include" since it didn't need to be there. - Remove arm64_supports_nmi() - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. Changes in v8: - debug_ipi_setup() and debug_ipi_teardown() no longer take cpu param arch/arm64/kernel/Makefile | 2 +- arch/arm64/kernel/ipi_debug.c | 76 +++++++++++++++++++++++++++++++++++ arch/arm64/kernel/ipi_debug.h | 13 ++++++ 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/kernel/ipi_debug.c create mode 100644 arch/arm64/kernel/ipi_debug.h diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index cc22011ab66a..737838f803b7 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -34,7 +34,7 @@ obj-y :=3D debug-monitors.o entry.o irq.o fpsimd.o \ cpufeature.o alternative.o cacheinfo.o \ smp.o smp_spin_table.o topology.o smccc-call.o \ syscall.o proton-pack.o idreg-override.o idle.o \ - patching.o + patching.o ipi_debug.o =20 obj-$(CONFIG_COMPAT) +=3D sys32.o signal32.o \ sys_compat.o diff --git a/arch/arm64/kernel/ipi_debug.c b/arch/arm64/kernel/ipi_debug.c new file mode 100644 index 000000000000..b57833e31eaf --- /dev/null +++ b/arch/arm64/kernel/ipi_debug.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Debug IPI support + * + * Copyright (C) 2020 Linaro Limited + * Author: Sumit Garg + */ + +#include +#include +#include + +#include "ipi_debug.h" + +static struct irq_desc *ipi_debug_desc __read_mostly; +static int ipi_debug_id __read_mostly; +static bool is_nmi; + +void arm64_debug_ipi(cpumask_t *mask) +{ + if (WARN_ON_ONCE(!ipi_debug_desc)) + return; + + __ipi_send_mask(ipi_debug_desc, mask); +} + +static irqreturn_t ipi_debug_handler(int irq, void *data) +{ + /* nop, NMI handlers for special features can be added here. */ + + return IRQ_NONE; +} + +void debug_ipi_setup(void) +{ + if (!ipi_debug_desc) + return; + + if (is_nmi) { + if (!prepare_percpu_nmi(ipi_debug_id)) + enable_percpu_nmi(ipi_debug_id, IRQ_TYPE_NONE); + } else { + enable_percpu_irq(ipi_debug_id, IRQ_TYPE_NONE); + } +} + +void debug_ipi_teardown(void) +{ + if (!ipi_debug_desc) + return; + + if (is_nmi) { + disable_percpu_nmi(ipi_debug_id); + teardown_percpu_nmi(ipi_debug_id); + } else { + disable_percpu_irq(ipi_debug_id); + } +} + +void __init set_smp_debug_ipi(int ipi) +{ + int err; + + if (!request_percpu_nmi(ipi, ipi_debug_handler, "IPI", &cpu_number)) { + is_nmi =3D true; + } else { + err =3D request_percpu_irq(ipi, ipi_debug_handler, "IPI", &cpu_number); + if (WARN_ON(err)) + return; + + irq_set_status_flags(ipi, IRQ_HIDDEN); + } + + ipi_debug_desc =3D irq_to_desc(ipi); + ipi_debug_id =3D ipi; +} diff --git a/arch/arm64/kernel/ipi_debug.h b/arch/arm64/kernel/ipi_debug.h new file mode 100644 index 000000000000..f6011a09282f --- /dev/null +++ b/arch/arm64/kernel/ipi_debug.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_NMI_H +#define __ASM_NMI_H + +#include + +void arm64_debug_ipi(cpumask_t *mask); + +void set_smp_debug_ipi(int ipi); +void debug_ipi_setup(void); +void debug_ipi_teardown(void); + +#endif --=20 2.41.0.rc2.161.g9c6817b8e7-goog From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFE89C77B7E for ; Thu, 1 Jun 2023 21:37:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232876AbjFAVhd (ORCPT ); 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Thu, 01 Jun 2023 14:37:13 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Douglas Anderson , Ben Dooks , Ingo Molnar , Josh Poimboeuf , Valentin Schneider , linux-kernel@vger.kernel.org Subject: [PATCH v9 4/7] arm64: smp: Assign and setup the debug IPI Date: Thu, 1 Jun 2023 14:31:48 -0700 Message-ID: <20230601143109.v9.4.I6d7f7d5fa0aa293c8c3374194947254b93114d37@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg All current arm64 interrupt controllers have at least 8 IPIs. Currently we are only using 7 of them on arm64. Let's use the 8th one as a debug IPI. This uses the new "debug IPI" infrastructure which will try to allocate this IPI as an NMI/pseudo NMI if possible. Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson --- I could imagine that people object to using up the last free IPI on interrupt controllers with only 8 IPIs. However, it shouldn't be a big deal. If we later need an extra IPI, it shouldn't be too hard to combine some of the existing ones. Presumably we could just get rid of the "crash stop" IPI and have the normal "stop" IPI do the crash if "waiting_for_crash_ipi" is non-zero Changes in v9: - Add a warning if we don't have enough IPIs for the NMI IPI - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. - Update commit description Changes in v8: - debug_ipi_setup() and debug_ipi_teardown() no longer take cpu param arch/arm64/kernel/smp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index edd63894d61e..db019b49d3bd 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -53,6 +53,8 @@ =20 #include =20 +#include "ipi_debug.h" + DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); EXPORT_PER_CPU_SYMBOL(cpu_number); =20 @@ -935,6 +937,8 @@ static void ipi_setup(int cpu) =20 for (i =3D 0; i < nr_ipi; i++) enable_percpu_irq(ipi_irq_base + i, 0); + + debug_ipi_setup(); } =20 #ifdef CONFIG_HOTPLUG_CPU @@ -947,6 +951,8 @@ static void ipi_teardown(int cpu) =20 for (i =3D 0; i < nr_ipi; i++) disable_percpu_irq(ipi_irq_base + i); + + debug_ipi_teardown(); } #endif =20 @@ -968,6 +974,11 @@ void __init set_smp_ipi_range(int ipi_base, int n) irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); } =20 + if (n > nr_ipi) + set_smp_debug_ipi(ipi_base + nr_ipi); + else + WARN(1, "Not enough IPIs for NMI IPI\n"); + ipi_irq_base =3D ipi_base; =20 /* Setup the boot CPU immediately */ --=20 2.41.0.rc2.161.g9c6817b8e7-goog From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A4DDC77B7E for ; Thu, 1 Jun 2023 21:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233083AbjFAVhk (ORCPT ); Thu, 1 Jun 2023 17:37:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232932AbjFAVh0 (ORCPT ); Thu, 1 Jun 2023 17:37:26 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 282621AE for ; Thu, 1 Jun 2023 14:37:17 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-65131e85be4so929728b3a.1 for ; Thu, 01 Jun 2023 14:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1685655436; x=1688247436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9zVBczE5O/mOGSjCuNx2rXBFKme8bX0ZhvLdtMhoiJw=; b=gJtJ5FNgW645QFhWJrwgv+eoPxUDcKJjQ0xUeo56kyURgPks4SkoC2MQNDgXTtkZn7 QpKWQwG1Ny/ElORyKFDpyWZbKE5bj+Wp8fgVBvS+d/n6lwbgm1qW/f/93p6MP2NY714A nlF2KzG2LMv/VRRI6kZ2Dt7zapyMsrojNB0GU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685655436; x=1688247436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9zVBczE5O/mOGSjCuNx2rXBFKme8bX0ZhvLdtMhoiJw=; b=EgiiG6afsu+1dL6qy8+rhQKqerhSCxzUnSEUGwWjRt9udq3TKEsfOSyI75mzkimmRC oK4n/exPZsuOTpdghzaRgBpAdAE/gcj59a8R1DLeIw7FBBZAh0OnXWKw5lAZv4F6yHPH +QvTOt6M2ZEi+xYEqMXWc9TF5U0EO52LbrEzzsfsOqdy/NXdnjzbDhRGbga0hHGY4kIl /nNpinaOTzXeS1Z3xRiDLmG37nFoH5BsDfOannPF5MuQa8na3+T6fnkk4QtnW797z6w/ bOC9FIsOZybkkW/GnjMc03QepugSbnS8YwajOBXr/Mo8xHBABPzLh1Efn94IVSLgaAJ1 Xhsg== X-Gm-Message-State: AC+VfDyQ4ZY/deGTe0ufzlmlm1BcN/1TiAygfzukFJkDIb0SwtxqzI72 d+muuZzCreuUGW7Rv55zr7a9yg== X-Google-Smtp-Source: ACHHUZ5+oSxNdbJJZmlNccaogK7aaVEwJBbdqRJ3q2/KAcjer9oPcCVCtZIErTbQBeOU2bnwefC/oQ== X-Received: by 2002:a05:6a00:1797:b0:651:ce88:27f5 with SMTP id s23-20020a056a00179700b00651ce8827f5mr2208089pfg.13.1685655436495; Thu, 01 Jun 2023 14:37:16 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:11b8:2d2:7e02:6bff]) by smtp.gmail.com with ESMTPSA id g22-20020aa78756000000b0064d48d98260sm5319534pfo.156.2023.06.01.14.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 14:37:15 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v9 5/7] arm64: ipi_debug: Add support for backtrace using the debug IPI Date: Thu, 1 Jun 2023 14:31:49 -0700 Message-ID: <20230601143109.v9.5.I65981105e1f62550b0316625dd1e599deaf9e1aa@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg Enable arch_trigger_cpumask_backtrace() support on arm64 using the new debug IPI. With this arm64 can now get backtraces in cases where callers of the trigger_xyz_backtrace() class of functions don't check the return code and implement a fallback. One example is `kernel.softlockup_all_cpu_backtrace`. This also allows us to backtrace hard locked up CPUs in cases where the debug IPI is backed by an NMI (or pseudo NMI). Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson --- Changes in v9: - Added comments that we might not be using NMI always. - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. - arch_trigger_cpumask_backtrace() no longer returns bool Changes in v8: - Removed "#ifdef CONFIG_SMP" since arm64 is always SMP arch/arm64/include/asm/irq.h | 3 +++ arch/arm64/kernel/ipi_debug.c | 25 +++++++++++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/irq.h b/arch/arm64/include/asm/irq.h index fac08e18bcd5..be2d103f316e 100644 --- a/arch/arm64/include/asm/irq.h +++ b/arch/arm64/include/asm/irq.h @@ -6,6 +6,9 @@ =20 #include =20 +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_se= lf); +#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace + struct pt_regs; =20 int set_handle_irq(void (*handle_irq)(struct pt_regs *)); diff --git a/arch/arm64/kernel/ipi_debug.c b/arch/arm64/kernel/ipi_debug.c index b57833e31eaf..6984ed507e1f 100644 --- a/arch/arm64/kernel/ipi_debug.c +++ b/arch/arm64/kernel/ipi_debug.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include =20 #include "ipi_debug.h" @@ -24,11 +25,31 @@ void arm64_debug_ipi(cpumask_t *mask) __ipi_send_mask(ipi_debug_desc, mask); } =20 +void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_se= lf) +{ + /* + * NOTE: though nmi_trigger_cpumask_backtrace has "nmi_" in the name, + * nothing about it truly needs to be backed by an NMI, it's just that + * it's _allowed_ to be called from an NMI. If set_smp_debug_ipi() + * failed to get an NMI (or pseudo-NMI) this will just be backed by a + * regular IPI. + */ + nmi_trigger_cpumask_backtrace(mask, exclude_self, arm64_debug_ipi); +} + static irqreturn_t ipi_debug_handler(int irq, void *data) { - /* nop, NMI handlers for special features can be added here. */ + irqreturn_t ret =3D IRQ_NONE; + + /* + * NOTE: Just like in arch_trigger_cpumask_backtrace(), we're calling + * a function with "nmi_" in the name but it works fine even if we + * are using a regulaor IPI. + */ + if (nmi_cpu_backtrace(get_irq_regs())) + ret =3D IRQ_HANDLED; =20 - return IRQ_NONE; + return ret; } =20 void debug_ipi_setup(void) --=20 2.41.0.rc2.161.g9c6817b8e7-goog From nobody Sat Feb 7 23:34:04 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A723C7EE23 for ; Thu, 1 Jun 2023 21:37:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232229AbjFAVhm (ORCPT ); Thu, 1 Jun 2023 17:37:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232971AbjFAVh1 (ORCPT ); Thu, 1 Jun 2023 17:37:27 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D3B9E40 for ; Thu, 1 Jun 2023 14:37:19 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-52c30fa5271so685699a12.0 for ; Thu, 01 Jun 2023 14:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1685655439; x=1688247439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MfGBHBvKGGFx2dApaWUV0FsGkRnAHULREps6A6RYWJ4=; b=AkgOfxeqMJ+Uowmkx4hw7IQZ50qdy2xVCPyodSzFbID79vkX/uuep2hjtkAVQf+ZMY 2Ois27dY1aNRlYZc7JAHlkdtHKB/6T3f05uoIAoto3JEclpb7k9RtEHCD6+WC8K9AjHR 0/+O26QCTSXFLaWGDuAgWq5b1oezjD46LgHAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685655439; x=1688247439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MfGBHBvKGGFx2dApaWUV0FsGkRnAHULREps6A6RYWJ4=; b=N7HWJtLG4dL5P1bvft8Bpwy+A9annUOLMGKJWXlILXdsxka3YZxKrHUIzUd4SDECyT /R4ThtXT11aVK278FRcwrhr6ts2V1oix9YYk4NCMfq2TEjo1sOwteQtYQmSMiplTLo7O UnLmqUTwOyXWR0Oy6Go2eWuPkTqDbd2+OPsXw7GFt3aQa4GbUhHlFE3SJjmSbadf2Yns zT2NJwvdYrbv1cZ5ybz7E5vJMzzGnI4LnTs106VHipaR38+zOj79lIOGkmR3A/A5YKLI XXT8twiNeYsBlfAAN8C+dEsEF+nX8aSYFPmaoDJVGn2uomKUSxsqGYoQKk3Kzcobd6/n w7wQ== X-Gm-Message-State: AC+VfDzreSiaq2b3vy3VJGX/tQ6BgY+SUBB/CTXBN/1NpQPPRBsWPb4x IivrW8+wErqOQV/TnzXfFzrYUA== X-Google-Smtp-Source: ACHHUZ6c761aOPieAnWSz/n26mxi7TuDnyom5n4cFPpm2ooQ6JFhgncQbyJIHjA9N7SSHuxDQFh8Yw== X-Received: by 2002:a05:6a20:1583:b0:10f:759d:c5b2 with SMTP id h3-20020a056a20158300b0010f759dc5b2mr8808767pzj.45.1685655438667; Thu, 01 Jun 2023 14:37:18 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:11b8:2d2:7e02:6bff]) by smtp.gmail.com with ESMTPSA id g22-20020aa78756000000b0064d48d98260sm5319534pfo.156.2023.06.01.14.37.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 14:37:18 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Douglas Anderson , Jason Wessel , linux-kernel@vger.kernel.org Subject: [PATCH v9 6/7] kgdb: Provide a stub kgdb_nmicallback() if !CONFIG_KGDB Date: Thu, 1 Jun 2023 14:31:50 -0700 Message-ID: <20230601143109.v9.6.Ia3aeac89bb6751b682237e76e5ba594318e4b1aa@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To save architectures from needing to wrap the call in #ifdefs, add a stub no-op version of kgdb_nmicallback(), which returns 1 if it didn't handle anything. Reviewed-by: Daniel Thompson Signed-off-by: Douglas Anderson --- In v9 this is the only kgdb dependency. I'm assuming it could go through the arm64 tree? If that's not a good idea, we could always change the patch ("arm64: kgdb: Roundup cpus using IPI as NMI") not to depend on it by only calling kgdb_nmicallback() if CONFIG_KGDB is not defined. Changes in v9: - Added missing "inline" Changes in v8: - "Provide a stub kgdb_nmicallback() if !CONFIG_KGDB" new for v8 include/linux/kgdb.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/kgdb.h b/include/linux/kgdb.h index 258cdde8d356..76e891ee9e37 100644 --- a/include/linux/kgdb.h +++ b/include/linux/kgdb.h @@ -365,5 +365,6 @@ extern void kgdb_free_init_mem(void); #define dbg_late_init() static inline void kgdb_panic(const char *msg) {} static inline void kgdb_free_init_mem(void) { } +static inline int kgdb_nmicallback(int cpu, void *regs) { return 1; } #endif /* ! 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Wysocki" , Lecopzer Chen , Douglas Anderson , Wei Li , linux-kernel@vger.kernel.org Subject: [PATCH v9 7/7] arm64: kgdb: Roundup cpus using the debug IPI Date: Thu, 1 Jun 2023 14:31:51 -0700 Message-ID: <20230601143109.v9.7.I2ef26d1b3bfbed2d10a281942b0da7d9854de05e@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg Let's use the debug IPI for rounding up CPUs in kgdb. When the debug IPI is backed by an NMI (or pseudo NMI) then this will let us debug even hard locked CPUs. When the debug IPI isn't backed by an NMI then this won't really have any huge benefit but it will still work. Signed-off-by: Sumit Garg Signed-off-by: Douglas Anderson --- Changes in v9: - Remove fallback for when debug IPI isn't available. - Renamed "NMI IPI" to "debug IPI" since it might not be backed by NMI. arch/arm64/kernel/ipi_debug.c | 5 +++++ arch/arm64/kernel/kgdb.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/kernel/ipi_debug.c b/arch/arm64/kernel/ipi_debug.c index 6984ed507e1f..5794894d94f1 100644 --- a/arch/arm64/kernel/ipi_debug.c +++ b/arch/arm64/kernel/ipi_debug.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include =20 @@ -40,6 +41,7 @@ void arch_trigger_cpumask_backtrace(const cpumask_t *mask= , bool exclude_self) static irqreturn_t ipi_debug_handler(int irq, void *data) { irqreturn_t ret =3D IRQ_NONE; + unsigned int cpu =3D smp_processor_id(); =20 /* * NOTE: Just like in arch_trigger_cpumask_backtrace(), we're calling @@ -49,6 +51,9 @@ static irqreturn_t ipi_debug_handler(int irq, void *data) if (nmi_cpu_backtrace(get_irq_regs())) ret =3D IRQ_HANDLED; =20 + if (!kgdb_nmicallback(cpu, get_irq_regs())) + ret =3D IRQ_HANDLED; + return ret; } =20 diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index 4e1f983df3d1..9c4c47507cd4 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -20,6 +20,8 @@ #include #include =20 +#include "ipi_debug.h" + struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =3D { { "x0", 8, offsetof(struct pt_regs, regs[0])}, { "x1", 8, offsetof(struct pt_regs, regs[1])}, @@ -356,3 +358,15 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt) return aarch64_insn_write((void *)bpt->bpt_addr, *(u32 *)bpt->saved_instr); } + +void kgdb_roundup_cpus(void) +{ + struct cpumask mask; + + cpumask_copy(&mask, cpu_online_mask); + cpumask_clear_cpu(raw_smp_processor_id(), &mask); + if (cpumask_empty(&mask)) + return; + + arm64_debug_ipi(&mask); +} --=20 2.41.0.rc2.161.g9c6817b8e7-goog