From nobody Mon Feb 9 23:39:43 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A20A1C77B7E for ; Thu, 1 Jun 2023 21:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232834AbjFAVhM (ORCPT ); Thu, 1 Jun 2023 17:37:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232401AbjFAVhJ (ORCPT ); Thu, 1 Jun 2023 17:37:09 -0400 Received: from mail-pf1-x42e.google.com (mail-pf1-x42e.google.com [IPv6:2607:f8b0:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AB6E19B for ; Thu, 1 Jun 2023 14:37:08 -0700 (PDT) Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-65292f79456so414788b3a.2 for ; Thu, 01 Jun 2023 14:37:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1685655427; x=1688247427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HjRakdb30yszASmxf/wTOyUnLRsbS0tBSqMyHI/mgmg=; b=BuG16CgsJZuRqklwqhtraGtO9mDBkjKRduhSYXiCHYmDshIggjlraGD2H9A4z6yorm wBu2dEQorFkxnRHLq3Cn+M+LkZWex3ajMYBEgSEujM238OkqShSG0aa2MrkveBlrCXC5 p6NW7FtAcuIScDFj5KSELcmbgvEEVbSabk3PI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685655427; x=1688247427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HjRakdb30yszASmxf/wTOyUnLRsbS0tBSqMyHI/mgmg=; b=i9Kd6y9nYYJi94gxAISYewPWIy5HSmm33S2QV8Q3RLEzO7lWH4Yrbn2BtQdXshMOwH +KAb9zHKYqSwyIG1jlkCvLnPbPNGRi09ixmjsR8c1xDpNl2RchKA9zAxqVrgJpfNgaoG 1HttAbunsSW6bXL0Enn/F28/1jYPkf2DmnGAqKVVT4uesfuG/hQsnf94hOrW3CJznI+y g+hvpa3yrH8oaaH0qpDtmrR1OzZpXAWCKEkaTu9jeHnk/wkSuda9ldJ4rBv5kp2o7hod 47+V9+D5YmQuK1WzYHqW72auoUda+dS79TKnLa0fcjyGb9RFSL2ACLZ1xvT7nmJl8okn Ccug== X-Gm-Message-State: AC+VfDzSANHt6dZc74+pkklc4rBd9gyJXwvuNicZK6ePs8/hKHSGOuKu FLR5OR3k7tngwyQrCkiiO8DkLW3Y0IzUkvOpLgs= X-Google-Smtp-Source: ACHHUZ7X4JWk69pwtWfobliPNOJVZLyvG8aXSBcL3S43aA7yIba6lfLCLzZNDwufKt9JnCsD52RTZQ== X-Received: by 2002:a05:6a21:1647:b0:111:6a14:7d0 with SMTP id no7-20020a056a21164700b001116a1407d0mr6606398pzb.60.1685655427621; Thu, 01 Jun 2023 14:37:07 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:11b8:2d2:7e02:6bff]) by smtp.gmail.com with ESMTPSA id g22-20020aa78756000000b0064d48d98260sm5319534pfo.156.2023.06.01.14.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 14:37:07 -0700 (PDT) From: Douglas Anderson To: Mark Rutland , Catalin Marinas , Will Deacon , Sumit Garg , Daniel Thompson , Marc Zyngier Cc: linux-perf-users@vger.kernel.org, ito-yuichi@fujitsu.com, Chen-Yu Tsai , Ard Biesheuvel , Stephen Boyd , Peter Zijlstra , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, Masayoshi Mizuma , "Rafael J . Wysocki" , Lecopzer Chen , Masayoshi Mizuma , Douglas Anderson , linux-kernel@vger.kernel.org Subject: [PATCH v9 1/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Thu, 1 Jun 2023 14:31:45 -0700 Message-ID: <20230601143109.v9.1.I1223c11c88937bd0cbd9b086d4ef216985797302@changeid> X-Mailer: git-send-email 2.41.0.rc2.161.g9c6817b8e7-goog In-Reply-To: <20230601213440.2488667-1-dianders@chromium.org> References: <20230601213440.2488667-1-dianders@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sumit Garg Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler update in case of SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Signed-off-by: Sumit Garg Reviewed-by: Masayoshi Mizuma Tested-by: Chen-Yu Tsai Signed-off-by: Douglas Anderson --- (no changes since v1) drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 0c6c1af9a5b7..ed37e02d4c5f 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -525,6 +525,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) static int gic_irq_nmi_setup(struct irq_data *d) { struct irq_desc *desc =3D irq_to_desc(d->irq); + u32 idx; =20 if (!gic_supports_nmi()) return -EINVAL; @@ -542,16 +543,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) return -EINVAL; =20 /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx =3D gic_get_ppi_index(d); =20 /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); desc->handle_irq =3D handle_percpu_devid_fasteoi_nmi; } - } else { + break; + default: desc->handle_irq =3D handle_fasteoi_nmi; + break; } =20 gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -562,6 +569,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) static void gic_irq_nmi_teardown(struct irq_data *d) { struct irq_desc *desc =3D irq_to_desc(d->irq); + u32 idx; =20 if (WARN_ON(!gic_supports_nmi())) return; @@ -579,14 +587,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) return; =20 /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx =3D gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx =3D gic_get_ppi_index(d); =20 /* Tearing down NMI, only switch handler for last NMI */ if (refcount_dec_and_test(&ppi_nmi_refs[idx])) desc->handle_irq =3D handle_percpu_devid_irq; - } else { + break; + default: desc->handle_irq =3D handle_fasteoi_irq; + break; } =20 gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -2001,6 +2015,7 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, =20 gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); =20 @@ -2013,8 +2028,6 @@ static int __init gic_init_bases(phys_addr_t dist_phy= s_base, gicv2m_init(handle, gic_data.domain); } =20 - gic_enable_nmi_support(); - return 0; =20 out_free: --=20 2.41.0.rc2.161.g9c6817b8e7-goog