From nobody Fri Sep 20 20:40:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C715C7EE29 for ; Thu, 1 Jun 2023 12:11:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbjFAMLW (ORCPT ); Thu, 1 Jun 2023 08:11:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233376AbjFAMKr (ORCPT ); Thu, 1 Jun 2023 08:10:47 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 404171BD for ; Thu, 1 Jun 2023 05:10:36 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:a962:cd4d:a84:1eab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 1CAD46606EC5; Thu, 1 Jun 2023 13:10:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685621434; bh=jXr0wGpGehE+iesVyt9aBsjAnzI1CbtR4qvojrtKsGU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=btz23QJNeYZcKh9q3ng8cjgvHSSXEqlrV2EIUUeMeXB7GuaWlaJDe2hQFC1cX+iTt 7oSlA4zCX9464gTunz8m0wtBcE4PII4BsNd2RgDBhRJPMbTbH1zvbQ8LBlbX3klZOi 6EHcZSqrpziGyEOQgaH1TB1qqtkQO10HrMCt/Mxw3qYN4oi8BP3rvffnZYyJSPmjtz xSWD/RCy9x3pzwD/7TWEaav+tBrwkavsMQn9j2UT7F6iytyTnZfymcZsy6ZcqPwD1c L3AhumiLibmbyNjPjtDxD7ZerRZLiwsqvG/POY4nBNVrhyzTfOwIM+8e7z1mhCJYD1 hmZkoeuvwdtvA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v5 08/11] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Thu, 1 Jun 2023 14:10:19 +0200 Message-Id: <20230601121022.2401844-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121022.2401844-1-angelogioacchino.delregno@collabora.com> References: <20230601121022.2401844-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 74 ++++++++++++++--------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 407fb0264b80..f1a0b18b6c1a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -25,6 +25,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 =20 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -38,6 +40,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; u8 lut_bits; }; @@ -84,9 +87,10 @@ void mtk_gamma_set_common(struct device *dev, void __iom= em *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; - u16 lut_size; + u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -94,43 +98,57 @@ void mtk_gamma_set_common(struct device *dev, void __io= mem *regs, struct drm_crt =20 if (gamma && gamma->data) { lut_diff =3D gamma->data->lut_diff; + lut_bank_size =3D gamma->data->lut_bank_size; lut_bits =3D gamma->data->lut_bits; lut_size =3D gamma->data->lut_size; } else { lut_diff =3D false; + lut_bank_size =3D LUT_SIZE_DEFAULT; lut_bits =3D LUT_BITS_DEFAULT; lut_size =3D LUT_SIZE_DEFAULT; } + num_lut_banks =3D lut_size / lut_bank_size; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; - for (i =3D 0; i < lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red =3D drm_color_lut_extract(lut[i].red, lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[i].green, lut_bits); - hwlut.blue =3D drm_color_lut_extract(lut[i].blue, lut_bits); - - if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red =3D lut[i].red - lut[i - 1].red; - diff.red =3D drm_color_lut_extract(diff.red, lut_bits); - - diff.green =3D lut[i].green - lut[i - 1].green; - diff.green =3D drm_color_lut_extract(diff.green, lut_bits); - - diff.blue =3D lut[i].blue - lut[i - 1].blue; - diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); - - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, regs + DISP_GAMMA_BANK); + } + + for (i =3D 0; i < lut_bank_size; i++) { + int n =3D (cur_bank * lut_bank_size) + i; + struct drm_color_lut diff, hwlut; + + hwlut.red =3D drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green =3D drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); + + if (!lut_diff || (i % 2 =3D=3D 0)) { + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red =3D lut[n].red - lut[n - 1].red; + diff.red =3D drm_color_lut_extract(diff.red, lut_bits); + + diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D drm_color_lut_extract(diff.green, lut_bits); + + diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); + + word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, (lut_base + i * 4)); } - writel(word, (lut_base + i * 4)); } =20 /* Enable the gamma table */ @@ -241,11 +259,13 @@ static int mtk_disp_gamma_remove(struct platform_devi= ce *pdev) =20 static const struct mtk_disp_gamma_data mt8173_gamma_driver_data =3D { .has_dither =3D true, + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_size =3D 512, }; =20 static const struct mtk_disp_gamma_data mt8183_gamma_driver_data =3D { + .lut_bank_size =3D 512, .lut_bits =3D 10, .lut_diff =3D true, .lut_size =3D 512, --=20 2.40.1