From nobody Fri Sep 20 20:40:49 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDAF2C77B7A for ; Thu, 1 Jun 2023 12:11:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232171AbjFAMLo (ORCPT ); Thu, 1 Jun 2023 08:11:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233240AbjFAMKw (ORCPT ); Thu, 1 Jun 2023 08:10:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29213E59 for ; Thu, 1 Jun 2023 05:10:39 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:a962:cd4d:a84:1eab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id F17CE6606ED7; Thu, 1 Jun 2023 13:10:36 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1685621437; bh=k6yQCRlit5JxfvQfZrkIdCkk5RffSQQgb2OwFWhKw18=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GQDwwCB43cpH4K4v3wlQgfn9aUvAx3fNf84J5qLtmWcNyU2eOtmY+zRB1GcxQUGIr eyW3+DTXOPtleYLhX41rhwu7JBgvmETd+P8Kt43WMmGraNUfc535K/JVZY0a6/V02r 8h8BeLQEVxj5G3DL7s7hnPgbbZFqkjaES852xda6TAIWmojs+2v6LTeVftN1p/ZSUS O8w24Q0K7yUQaWeNz3iSsupIR6tJ0Rw03X2ycP8XfHDr28Is6BcYdQqnvFP0j8myP1 VG6tKo+LnUJE3rsbXRHy/TphLoPiQZ+7B2Lyis7i5+jDXs4MYuOq91JwIpQEO/sXo7 rpNihEHWYAZ2g== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v5 11/11] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Thu, 1 Jun 2023 14:10:22 +0200 Message-Id: <20230601121022.2401844-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230601121022.2401844-1-angelogioacchino.delregno@collabora.com> References: <20230601121022.2401844-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index e9655b661364..bd530e603264 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -23,6 +23,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -89,6 +90,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return lut_size; } =20 +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +{ + u64 first, last; + + first =3D lut[0].red + lut[0].green + lut[0].blue; + last =3D lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); @@ -178,6 +189,14 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt } } =20 + if (gamma && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &=3D ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |=3D FIELD_PREP(GAMMA_LUT_EN, 1); =20 --=20 2.40.1