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[83.9.29.77]) by smtp.gmail.com with ESMTPSA id v3-20020a056512048300b004f3b258feefsm1031119lfq.179.2023.06.01.02.39.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 02:39:13 -0700 (PDT) From: Konrad Dybcio Date: Thu, 01 Jun 2023 11:39:08 +0200 Subject: [PATCH 2/2] clk: qcom: gcc-sm6115: Add missing PLL config properties MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org> References: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org> In-Reply-To: <20230601-topic-alpha_ctl-v1-0-b6a932dfcf68@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Iskren Chernev Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1685612350; l=1703; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SPvCmzGhftB/XAFnbpI3W945MryOao+OxYb3yPb5WLA=; b=uGXQdD8bVwAhRq4ZoZThpA9708kDy5PvmDdfw0OR+wSrx/VVrfjEvTo0oMvQnX2USKv7X49/s sqLe0MHvgTTCKwf2DsNlypPUHln9cUvl2/My+YBt5zNO26e3gpZc/UV X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the driver was ported upstream, PLL ctl register values were omitted. Add them to ensure the PLLs are fully configured like we expect them to. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver f= or SM6115") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 5f09aefa7fb9..033e308ff865 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config =3D { .vco_mask =3D GENMASK(21, 20), .main_output_mask =3D BIT(0), .config_ctl_val =3D 0x4001055b, + .test_ctl_hi1_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, }; =20 static struct clk_alpha_pll gpll10 =3D { @@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config =3D { .vco_val =3D 0x2 << 20, .vco_mask =3D GENMASK(21, 20), .config_ctl_val =3D 0x4001055b, + .test_ctl_hi1_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, }; =20 static struct clk_alpha_pll gpll11 =3D { @@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config =3D { .post_div_val =3D 0x1 << 8, .post_div_mask =3D GENMASK(11, 8), .config_ctl_val =3D 0x4001055b, + .test_ctl_hi1_val =3D 0x1, + .test_ctl_hi_mask =3D 0x1, }; =20 static struct clk_alpha_pll gpll8 =3D { @@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config =3D { .post_div_mask =3D GENMASK(9, 8), .main_output_mask =3D BIT(0), .config_ctl_val =3D 0x00004289, + .test_ctl_mask =3D GENMASK(31, 0), + .test_ctl_val =3D 0x08000000, }; =20 static struct clk_alpha_pll gpll9 =3D { --=20 2.40.1