From nobody Mon Feb 9 13:07:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67762C77B73 for ; Wed, 31 May 2023 14:25:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235858AbjEaOZq (ORCPT ); Wed, 31 May 2023 10:25:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236674AbjEaOY4 (ORCPT ); Wed, 31 May 2023 10:24:56 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 268DBC5; Wed, 31 May 2023 07:24:48 -0700 (PDT) Received: from kwepemi500025.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4QWWjs5PclzTkwv; Wed, 31 May 2023 22:24:33 +0800 (CST) Received: from vm10-29-85-105.huawei.com (10.29.85.105) by kwepemi500025.china.huawei.com (7.221.188.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 31 May 2023 22:24:43 +0800 From: Jiantao Zhang To: , , , , , , , , CC: Subject: [PATCH] PCI: controller: Fix calculation error of msix pending table offset Date: Wed, 31 May 2023 22:24:42 +0800 Message-ID: <20230531142442.27576-1-water.zhangjiantao@huawei.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.29.85.105] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemi500025.china.huawei.com (7.221.188.170) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The interrupts already minus 1 in pci_epc_set_msix() according to pcie specification. So we must add 1 otherwise data corruption will happen. Signed-off-by: Jiantao Zhang Signed-off-by: Jianrong Zhang --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 2 +- drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index b8b655d4047e..ff608c46b8ac 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -310,7 +310,7 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u= 8 fn, u8 vfn, =20 /* Set PBA BAR and offset. BAR must match MSIX BAR */ reg =3D cap + PCI_MSIX_PBA; - val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + val =3D (offset + ((interrupts + 1) * PCI_MSIX_ENTRY_SIZE)) | bir; cdns_pcie_ep_fn_writel(pcie, fn, reg, val); =20 return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index f9182f8d552f..3d078ebe2517 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -417,7 +417,7 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 = func_no, u8 vfunc_no, dw_pcie_writel_dbi(pci, reg, val); =20 reg =3D ep_func->msix_cap + func_offset + PCI_MSIX_PBA; - val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + val =3D (offset + ((interrupts + 1) * PCI_MSIX_ENTRY_SIZE)) | bir; dw_pcie_writel_dbi(pci, reg, val); =20 dw_pcie_dbi_ro_wr_dis(pci); --=20 2.17.1