From nobody Mon Feb 9 23:44:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3FE0C77B73 for ; Tue, 30 May 2023 17:00:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233114AbjE3RAJ (ORCPT ); Tue, 30 May 2023 13:00:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232564AbjE3Q71 (ORCPT ); Tue, 30 May 2023 12:59:27 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D275193; Tue, 30 May 2023 09:59:12 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34UGx1kT125895; Tue, 30 May 2023 11:59:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685465941; bh=M8yKFjYPPDyz2yVGZg9w6f96sWSL3buCffjH1Mn5M8s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y1qLPnaF9c6weceg/j2iQ3aL4HsNNuSbHyclvJNRiSgKi6wPfqx//bUBTQdF3bHiH EJb4e5DyZvaiJOYbA6CJE/6Yu/4iDCZ0ys2pSpak+ST3It+mitlr9QbtLkOa2sYLkj EsWdDchgGrqEOdzr+FmiuU6sXENkge8QvuDyjcmo= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34UGx12V087491 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 May 2023 11:59:01 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 30 May 2023 11:59:01 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 30 May 2023 11:59:01 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34UGx1Po102754; Tue, 30 May 2023 11:59:01 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring CC: , , , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , Udit Kumar , Nitin Yadav , Andrew Davis Subject: [PATCH 6/7] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy Date: Tue, 30 May 2023 11:58:59 -0500 Message-ID: <20230530165900.47502-7-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230530165900.47502-1-nm@ti.com> References: <20230530165900.47502-1-nm@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. In addition MCU island has it's own secure proxy for usecases involving the MCU micro controllers. These are in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the nodes for use with bootloaders and firmware that require these communication paths which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since these instances do not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon --- New patch .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..b75057c49731 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ chipid@43000014 { reg =3D <0x00 0x43000014 0x00 0x4>; }; =20 + secure_proxy_sa3: mailbox@43600000 { + compatible =3D "ti,am654-secure-proxy"; + #mbox-cells =3D <1>; + reg-names =3D "target_data", "rt", "scfg"; + reg =3D <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status =3D "disabled"; + }; + mcu_ram: sram@41c00000 { compatible =3D "mmio-sram"; reg =3D <0x00 0x41c00000 0x00 0x100000>; @@ -280,6 +295,21 @@ mcu_udmap: dma-controller@285c0000 { }; }; =20 + secure_proxy_mcu: mailbox@2a480000 { + compatible =3D "ti,am654-secure-proxy"; + #mbox-cells =3D <1>; + reg-names =3D "target_data", "rt", "scfg"; + reg =3D <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status =3D "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible =3D "ti,j721e-cpsw-nuss"; #address-cells =3D <2>; --=20 2.40.0