From nobody Sun Feb 8 20:52:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37721C7EE2C for ; Tue, 30 May 2023 11:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232034AbjE3LoE (ORCPT ); Tue, 30 May 2023 07:44:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232031AbjE3Lnj (ORCPT ); Tue, 30 May 2023 07:43:39 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 109F7184 for ; Tue, 30 May 2023 04:43:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685447002; x=1716983002; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=YeT6YYfsU+EDG4nhTRFaSzhnjKPDKCvTrH+jCnce9So=; b=UXf9oN4T/HFIde4YRlzQ82sM9+UVRn1yuXoeennLgaassDgVPfMF8kuw wbU/bkmEZ7/CtFQfMz65nqrQplfpr5GvedD+JGJVTCuHWKGPD3F5Oy+Yz aYzbCDfSpXcUclm5FlQclysXK3TxqRhQKoOpmpmk73g35zLaduqDBeQIU wE8dUDU8ueY/tl828F2thNS3WcnV2l+pqWqZDHd1MS5OvjgfA5SxdMxl0 SpYchDMHvVcwYxa32LmdjFP9BnnosAXqv6GNQKo6OVdOsOKsneXply+nb L6dns5ZZJOi020WL+0EvMYh3wG7osbczDJsISL/ImD3jSDBPLc+PhOjmM A==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="383145355" X-IronPort-AV: E=Sophos;i="6.00,204,1681196400"; d="scan'208";a="383145355" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 04:43:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="700588706" X-IronPort-AV: E=Sophos;i="6.00,204,1681196400"; d="scan'208";a="700588706" Received: from black.fi.intel.com (HELO black.fi.intel.com.) ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 30 May 2023 04:43:05 -0700 From: Alexander Shishkin To: linux-kernel@vger.kernel.org, x86@kernel.org, Andy Lutomirski , Dave Hansen , Ravi Shankar , Tony Luck , Sohil Mehta , Paul Lai Subject: [PATCH v2 04/12] x86/cpu: Enable LASS during CPU initialization Date: Tue, 30 May 2023 14:42:39 +0300 Message-Id: <20230530114247.21821-5-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230530114247.21821-1-alexander.shishkin@linux.intel.com> References: <20230530114247.21821-1-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sohil Mehta Being a security feature, enable LASS by default if the platform supports it. Signed-off-by: Sohil Mehta --- arch/x86/kernel/cpu/common.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 80710a68ef7d..315cc67ba93a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -413,6 +413,12 @@ static __always_inline void setup_umip(struct cpuinfo_= x86 *c) cr4_clear_bits(X86_CR4_UMIP); } =20 +static __always_inline void setup_lass(struct cpuinfo_x86 *c) +{ + if (cpu_feature_enabled(X86_FEATURE_LASS)) + cr4_set_bits(X86_CR4_LASS); +} + /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | @@ -1859,6 +1865,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) setup_smep(c); setup_smap(c); setup_umip(c); + setup_lass(c); =20 /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { --=20 2.39.2