From nobody Mon Feb 9 00:53:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5E53C77B73 for ; Tue, 30 May 2023 11:44:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231597AbjE3Loj (ORCPT ); Tue, 30 May 2023 07:44:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbjE3Lny (ORCPT ); Tue, 30 May 2023 07:43:54 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABAD1114 for ; Tue, 30 May 2023 04:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685447028; x=1716983028; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fuR9qvQ94ZrjBMln22ybuTxen7mUs7UOMBAmFKJPRd4=; b=CzYZiatXillWh7c2WpvGmGX9s1Y2pWPVGRjdNhO3VRunwljkt5YrBdRE Juk27X+ebc8VDFDG6ZKGm1Hv825vDCmjNzCKThanXgDR4+eGD/pMGSBHq RXfeJUQY5rIrA+DlNrsWSZT5Jya38dFMccf3E9Ik0MaiyE6nwX8bi1DHe 0rAXIwUUDraq1rscvxkQRdn8cpmxPOd3+DKhVf1BFzLBNLuvWCtztTk9N U+IZXO5WgsWJmIgG+BWrX2+MnrPTkjv9CNEmx5Zf96q782UgtEL38FxqG oHa03y7Z8s2zUjEYCcbAQp8upmkKFtz/wvigh+WbwOUXVOwJzUYNadHWh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="383145407" X-IronPort-AV: E=Sophos;i="6.00,204,1681196400"; d="scan'208";a="383145407" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 04:43:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="700588776" X-IronPort-AV: E=Sophos;i="6.00,204,1681196400"; d="scan'208";a="700588776" Received: from black.fi.intel.com (HELO black.fi.intel.com.) ([10.237.72.28]) by orsmga007.jf.intel.com with ESMTP; 30 May 2023 04:43:23 -0700 From: Alexander Shishkin To: linux-kernel@vger.kernel.org, x86@kernel.org, Andy Lutomirski , Dave Hansen , Ravi Shankar , Tony Luck , Sohil Mehta , Paul Lai Cc: Yian Chen Subject: [PATCH v2 11/12] x86/cpu: Set LASS CR4 bit as pinning sensitive Date: Tue, 30 May 2023 14:42:46 +0300 Message-Id: <20230530114247.21821-12-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230530114247.21821-1-alexander.shishkin@linux.intel.com> References: <20230530114247.21821-1-alexander.shishkin@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yian Chen Security features such as LASS are not expected to be disabled once initialized. Add LASS to the CR4 pinned mask. Signed-off-by: Yian Chen Reviewed-by: Tony Luck --- arch/x86/kernel/cpu/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f26c56fe9963..9ddc19c8832d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -422,7 +422,7 @@ static __always_inline void setup_lass(struct cpuinfo_x= 86 *c) /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask =3D X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | - X86_CR4_FSGSBASE | X86_CR4_CET; + X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_LASS; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; =20 --=20 2.39.2