From nobody Tue Feb 10 01:59:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBEB6C7EE2F for ; Mon, 29 May 2023 17:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229666AbjE2RZT (ORCPT ); Mon, 29 May 2023 13:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229580AbjE2RZB (ORCPT ); Mon, 29 May 2023 13:25:01 -0400 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1EF64DE for ; Mon, 29 May 2023 10:24:54 -0700 (PDT) Received: from loongson.cn (unknown [10.20.42.43]) by gateway (Coremail) with SMTP id _____8BxFvHm33RkR0oCAA--.5355S3; Tue, 30 May 2023 01:24:54 +0800 (CST) Received: from openarena.loongson.cn (unknown [10.20.42.43]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxMuXk33RkhkV_AA--.9919S8; Tue, 30 May 2023 01:24:53 +0800 (CST) From: Sui Jingfeng To: Lucas Stach , Russell King , Christian Gmeiner , David Airlie , Daniel Vetter Cc: linux-kernel@vger.kernel.org, etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, loongson-kernel@lists.loongnix.cn Subject: [PATCH v5 6/6] drm/etnaviv: allow usperspace create cached coherent bo Date: Tue, 30 May 2023 01:24:52 +0800 Message-Id: <20230529172452.2148819-7-suijingfeng@loongson.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529172452.2148819-1-suijingfeng@loongson.cn> References: <20230529172452.2148819-1-suijingfeng@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8CxMuXk33RkhkV_AA--.9919S8 X-CM-SenderInfo: xvxlyxpqjiv03j6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjvJXoWxXF4fGryfAF4UZFyUZFykAFb_yoWrKFWUpF Z3AFyYkrW0v3yDK34xAFn8Za43Gw12gFZ2k3sxtwn09w45tF42qr95KFZ8Crn8Jr1fGry3 tw1Dtry5K3WUArJanT9S1TB71UUUUj7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b68YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_JFv_Jw1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8Jr0_Cr1UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2kKe7AKxVWUAVWUtwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zV CFFI0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVW3AVW8Xw1lYx0E x4A2jsIE14v26F4j6r4UJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc7 CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l 4IxYO2xFxVAFwI0_JF0_Jw1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxV WUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAF wI0_tr0E3s1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2 IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26F4j6r4UJwCI42IY6I8E87Iv6xkF7I0E14v2 6r4UJVWxJrUvcSsGvfC2KfnxnUUI43ZEXa7IU1uyxJUUUUU== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" cached system RAM is coherent on loongson CPUs, and the GPU and DC allways snoop the CPU's cache. write-combine caching property is not suitiable for us. Signed-off-by: Sui Jingfeng --- drivers/gpu/drm/etnaviv/etnaviv_drv.c | 2 +- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 22 +++++++++++++++++++-- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 9 ++++++++- include/uapi/drm/etnaviv_drm.h | 11 ++++++----- 4 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnavi= v/etnaviv_drv.c index 7ff795c5cc79..3a86d1211ca5 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -275,7 +275,7 @@ static int etnaviv_ioctl_gem_new(struct drm_device *dev= , void *data, struct drm_etnaviv_gem_new *args =3D data; =20 if (args->flags & ~(ETNA_BO_CACHED | ETNA_BO_WC | ETNA_BO_UNCACHED | - ETNA_BO_FORCE_MMU)) + ETNA_BO_CACHED_COHERENT | ETNA_BO_FORCE_MMU)) return -EINVAL; =20 return etnaviv_gem_new_handle(dev, file, args->size, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnavi= v/etnaviv_gem.c index b5f73502e3dd..d8b559bd33d3 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -343,6 +343,7 @@ void *etnaviv_gem_vmap(struct drm_gem_object *obj) static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj) { struct page **pages; + pgprot_t prot; =20 lockdep_assert_held(&obj->lock); =20 @@ -350,8 +351,20 @@ static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_= object *obj) if (IS_ERR(pages)) return NULL; =20 - return vmap(pages, obj->base.size >> PAGE_SHIFT, - VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + switch (obj->flags) { + case ETNA_BO_CACHED_COHERENT: + case ETNA_BO_CACHED: + prot =3D PAGE_KERNEL; + break; + case ETNA_BO_UNCACHED: + prot =3D pgprot_noncached(PAGE_KERNEL); + break; + case ETNA_BO_WC: + default: + prot =3D pgprot_writecombine(PAGE_KERNEL); + } + + return vmap(pages, obj->base.size >> PAGE_SHIFT, VM_MAP, prot); } =20 static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op) @@ -545,6 +558,7 @@ static const struct drm_gem_object_funcs etnaviv_gem_ob= ject_funcs =3D { static int etnaviv_gem_new_impl(struct drm_device *dev, u32 size, u32 flag= s, const struct etnaviv_gem_ops *ops, struct drm_gem_object **obj) { + struct etnaviv_drm_private *priv =3D dev->dev_private; struct etnaviv_gem_object *etnaviv_obj; unsigned sz =3D sizeof(*etnaviv_obj); bool valid =3D true; @@ -555,6 +569,10 @@ static int etnaviv_gem_new_impl(struct drm_device *dev= , u32 size, u32 flags, case ETNA_BO_CACHED: case ETNA_BO_WC: break; + case ETNA_BO_CACHED_COHERENT: + if (priv->has_cached_coherent) + break; + fallthrough; default: valid =3D false; } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/= etnaviv/etnaviv_gem_prime.c index 3524b5811682..671d91d8f1c6 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -112,11 +112,18 @@ static const struct etnaviv_gem_ops etnaviv_gem_prime= _ops =3D { struct drm_gem_object *etnaviv_gem_prime_import_sg_table(struct drm_device= *dev, struct dma_buf_attachment *attach, struct sg_table *sgt) { + struct etnaviv_drm_private *priv =3D dev->dev_private; struct etnaviv_gem_object *etnaviv_obj; size_t size =3D PAGE_ALIGN(attach->dmabuf->size); + u32 cache_flags; int ret, npages; =20 - ret =3D etnaviv_gem_new_private(dev, size, ETNA_BO_WC, + if (priv->has_cached_coherent) + cache_flags =3D ETNA_BO_CACHED_COHERENT; + else + cache_flags =3D ETNA_BO_WC; + + ret =3D etnaviv_gem_new_private(dev, size, cache_flags, &etnaviv_gem_prime_ops, &etnaviv_obj); if (ret < 0) return ERR_PTR(ret); diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h index af024d90453d..474b0db286de 100644 --- a/include/uapi/drm/etnaviv_drm.h +++ b/include/uapi/drm/etnaviv_drm.h @@ -90,13 +90,14 @@ struct drm_etnaviv_param { * GEM buffers: */ =20 -#define ETNA_BO_CACHE_MASK 0x000f0000 +#define ETNA_BO_CACHE_MASK 0x000f0000 /* cache modes */ -#define ETNA_BO_CACHED 0x00010000 -#define ETNA_BO_WC 0x00020000 -#define ETNA_BO_UNCACHED 0x00040000 +#define ETNA_BO_CACHED 0x00010000 +#define ETNA_BO_WC 0x00020000 +#define ETNA_BO_UNCACHED 0x00040000 +#define ETNA_BO_CACHED_COHERENT 0x00080000 /* map flags */ -#define ETNA_BO_FORCE_MMU 0x00100000 +#define ETNA_BO_FORCE_MMU 0x00100000 =20 struct drm_etnaviv_gem_new { __u64 size; /* in */ --=20 2.25.1