From nobody Fri Sep 20 20:29:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97615C7EE23 for ; Mon, 29 May 2023 16:46:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229665AbjE2QqU (ORCPT ); Mon, 29 May 2023 12:46:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229554AbjE2QqQ (ORCPT ); Mon, 29 May 2023 12:46:16 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD85DB5 for ; Mon, 29 May 2023 09:46:12 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5148ebc4b89so4691807a12.3 for ; Mon, 29 May 2023 09:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685378771; x=1687970771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NxiLnH0M50rO/qW7JX7iQtyXgKtx4AkJoJmCH1LebW4=; b=PibI7ffA9bBX6+x+JjrVc/w2AtIj2KQz9bHSi7VttnfkI2ZPnN5if7C07dvBLWSW2d weRes3Hd1QPpQcvo3POp/tvrkp2oIEdReemvYsYG9FbVbg3mldjfY3IMDDhToLEWzyAL yTxOybUXSpRIbqPJ5nuXrpHQHzXv/z1yDltXM9OHI/BxWELLgVTcXvUvGSSB8WnO44dB AOl62/fqCQkXB57zIEgAMOlXnNN4CC2SjZIKaLuiCleZqTQESdLi1DSWxGpfz8uW7qkY 2pcQIk2OIeXZS6kstrpadwun7XKLtMaAXFewu8LlghyYhPzzI3TPkUjZVsRSuu5EB1pT xqvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685378771; x=1687970771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NxiLnH0M50rO/qW7JX7iQtyXgKtx4AkJoJmCH1LebW4=; b=RNWXHggp3ladOH/O5Glol2x9pdICkaQShXVx/w2AU1fJtydQ85popuNM6iZNi81UEh oFYGDykofissMziVpHsc5zs5LBSc/buSyMjHosQufJllFxGb1RWfidoIy1elPwLAWpZI YFRONYARa3gcED33kLy/lcGP6VxB8TAYdnilechNA66EepCLSb44ABXYGKReJWlUuGDk 2a4kV3nstQ92smQbtCj+oT+yqr1a3dk3vEa+H5zOdz/O4uChgygD7GdHewWaCpn2NW7V IHnve91covS0tsi9ggyiyCgDC6cWUvCuwL1bICCD0EYmPH+w7FOd7ex1axT1lyLRG/tV kEYQ== X-Gm-Message-State: AC+VfDwW1ejmb/7Br3PcnZZU4u1/ggSPf8LU/vMl9AY9KMq4xz7vRM/G ZvmfhBTvAIPEjIbrZc7jhxK27g== X-Google-Smtp-Source: ACHHUZ5gNCbXtMLfCqjRJ0nH0WPEiGrvsb5IpPrrSsXe98TatjsMehNONAcxpuek1O7918b3E4G+Kg== X-Received: by 2002:aa7:c317:0:b0:514:a0a7:7e7f with SMTP id l23-20020aa7c317000000b00514a0a77e7fmr223165edq.2.1685378771160; Mon, 29 May 2023 09:46:11 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id f4-20020aa7d844000000b0050d89daaa70sm3248578eds.2.2023.05.29.09.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 09:46:10 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192 Date: Mon, 29 May 2023 18:46:01 +0200 Message-ID: <20230529164605.3552619-2-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230529164605.3552619-1-bero@baylibre.com> References: <20230529164605.3552619-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add LVTS thermal controller definition for MT8192. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger --- .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/= dt-bindings/thermal/mediatek,lvts-thermal.h index 8fa5a46675c46..5e9eb62174268 100644 --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h @@ -26,4 +26,23 @@ #define MT8195_AP_CAM0 15 #define MT8195_AP_CAM1 16 =20 +#define MT8192_MCU_BIG_CPU0 0 +#define MT8192_MCU_BIG_CPU1 1 +#define MT8192_MCU_BIG_CPU2 2 +#define MT8192_MCU_BIG_CPU3 3 +#define MT8192_MCU_LITTLE_CPU0 4 +#define MT8192_MCU_LITTLE_CPU1 5 +#define MT8192_MCU_LITTLE_CPU2 6 +#define MT8192_MCU_LITTLE_CPU3 7 + +#define MT8192_AP_VPU0 8 +#define MT8192_AP_VPU1 9 +#define MT8192_AP_GPU0 10 +#define MT8192_AP_GPU1 11 +#define MT8192_AP_INFRA 12 +#define MT8192_AP_CAM 13 +#define MT8192_AP_MD0 14 +#define MT8192_AP_MD1 15 +#define MT8192_AP_MD2 16 + #endif /* __MEDIATEK_LVTS_DT_H */ --=20 2.41.0.rc2 From nobody Fri Sep 20 20:29:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97AE0C77B7A for ; Mon, 29 May 2023 16:46:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229504AbjE2QqY (ORCPT ); Mon, 29 May 2023 12:46:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229580AbjE2QqR (ORCPT ); Mon, 29 May 2023 12:46:17 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A620CD for ; Mon, 29 May 2023 09:46:14 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-96fbc74fbf1so649481066b.1 for ; Mon, 29 May 2023 09:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685378773; x=1687970773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GZ1Pw000YHwunl4UOYUIH6XIIpBvLCqm0y/k6ZseuYk=; b=deTEIU+pyD3V5mnx/rrEaGu+++V8NuthSZVyNy3qg7qAW7v1bdiAuHp1Ykv4wUMdak sEITqWIa0GT/2rqYOvugqqALSSRd0RVUjiefeGQVIw0wLoa8e+hwbyx+2w1oNF//W7Un BXuQN9qcPNRjHieND/XpY8yaVCXqjH/bMXGpEm8E/v6SQuK2JCOB0KFrRcLdU/v7pTEj EI/mw2e4EWrFO1ixiI2qRQFfaNcig/KQNRdwTN6CbqtiM5EDCUzq8/hCPOICPWOAq9tw 8Q6Ityc22xe4ekw1DhjSIKE7tu0Jvyv+2v80prncLc1QuPfo6T8PloejnKRJqziKOLJj KE8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685378773; x=1687970773; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GZ1Pw000YHwunl4UOYUIH6XIIpBvLCqm0y/k6ZseuYk=; b=TX0f2jAoxldgRm6+ROGu+4vOA/sbuCJonJZRDmDK82fphoPsFLO+L8AHlKo16IuVSV LoMVUGurNJ6XOqe/a3PpwFHpqZctGmp6IIEtIyqdYTliG1aBSDeXG9MOgiJKZWL36RUm LXM/3QESqTEq1XdU2KInz5S62gnqVi3T7df4iq0VDP8vdQzWjYzSuukSVVKDLBtfKQME 0VqI/Vlcis7M6DuvWqATrCn+qcnxFjvGFusNa1q0ToenfH8zAazcAi2Yox7xUAxwhEjx 4gasDxG9jo3TUzxq/+jZmhK3AL+Il9laHY8romdRmPbzliqylecr0/jPB4mKdpoqBNb8 BpwA== X-Gm-Message-State: AC+VfDzLFM5G2FfJzxiXbDJDoHfm5mTJHeq3dSDzkiqbI5Fqml+to1wE sFKDdzh6yTA8osZ0ylTL+EzDhw== X-Google-Smtp-Source: ACHHUZ57TCu1nzyJyjSvhGgSy6JPiAeD/WueOUQpFY775HM6nWCxEeV9TIa9C/uSHQQiugl0GYTgpw== X-Received: by 2002:a17:907:6093:b0:965:6075:d100 with SMTP id ht19-20020a170907609300b009656075d100mr14795453ejc.39.1685378772810; Mon, 29 May 2023 09:46:12 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id f4-20020aa7d844000000b0050d89daaa70sm3248578eds.2.2023.05.29.09.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 09:46:12 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Date: Mon, 29 May 2023 18:46:02 +0200 Message-ID: <20230529164605.3552619-3-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230529164605.3552619-1-bero@baylibre.com> References: <20230529164605.3552619-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add suspend and resume support to LVTS driver. Signed-off-by: Balsam CHIHI Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger --- drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index d0a3f95b7884b..5ea8a9d569ea6 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev) return 0; } =20 +static int lvts_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct lvts_domain *lvts_td; + int i; + + lvts_td =3D platform_get_drvdata(pdev); + + for (i =3D 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); + + clk_disable_unprepare(lvts_td->clk); + + return 0; +} + +static int lvts_resume(struct platform_device *pdev) +{ + struct lvts_domain *lvts_td; + int i, ret; + + lvts_td =3D platform_get_drvdata(pdev); + + ret =3D clk_prepare_enable(lvts_td->clk); + if (ret) + return ret; + + for (i =3D 0; i < lvts_td->num_lvts_ctrl; i++) + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); + + return 0; +} + static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] =3D { { .cal_offset =3D { 0x04, 0x07 }, @@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match); static struct platform_driver lvts_driver =3D { .probe =3D lvts_probe, .remove =3D lvts_remove, + .suspend =3D lvts_suspend, + .resume =3D lvts_resume, .driver =3D { .name =3D "mtk-lvts-thermal", .of_match_table =3D lvts_of_match, --=20 2.41.0.rc2 From nobody Fri Sep 20 20:29:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76644C7EE23 for ; Mon, 29 May 2023 16:46:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229677AbjE2Qq0 (ORCPT ); Mon, 29 May 2023 12:46:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229615AbjE2QqS (ORCPT ); Mon, 29 May 2023 12:46:18 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9BF5D2 for ; Mon, 29 May 2023 09:46:15 -0700 (PDT) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5147f7d045bso4700355a12.2 for ; Mon, 29 May 2023 09:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20221208.gappssmtp.com; s=20221208; t=1685378774; x=1687970774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=okJUfe+J2lktOzbTBoR7fCmJ4uPpfts4ISVsUrRsL8s=; b=1Ct2HKvKxppmAt3WslN5ekIsk3Ti5wkXJOaYEQq4Aqt1ERIO+MObGuoSun48zPGh/6 1+m/UleVx1iF3cYfEcRmNIgR066/IowWPZtaQS73P2R8nzqD3wLZ1a7zsWmMR1nwOEsb NAjC+KmybjL1aIg1F7Z71bk9K/dYnaMKn7/anAKmtrlzLDCLvtRoXhcG0c40sUHLsxao dniqD+yL17nHxVLMVG2nFyEA1NRsIn1pTVDDZ1cKhlJ4T4f1MiYP2M6qkD9g3YSU/mn9 kvPm/6f/iZj18nLqnLV3C0sHVfTg5xj1kuK21BxiRmSqblaqObGIXqYEoiw/iatpwrDE 59Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685378774; x=1687970774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=okJUfe+J2lktOzbTBoR7fCmJ4uPpfts4ISVsUrRsL8s=; b=ZJHYYq/l7288qDNMPSxhRmzUuq1bFeNwtk+d5g2fV/RQql6SseEJ58RVk3GKJ8vxgp pRtc+ftop7qm0gZcaDYZ/4kqi3Qlq94zNSoPIqL1a4c5p/544CCXPYCLZXL6wC4vL0vA c7EejsPEzR9KMKtWna5RAZu9kYWirUp3uPD7fyCmRMlKUTEZ7ONm04iMZwBAcI5oYOXT hNPOtzwsYFIGX3TulflsYeT3B/0n+gwQPb+vt4PgJKxyaXhsD35n2ZJTCZKCxmLwWLW4 CbDGsUBnItkRghLnYPJos3s/D62WZsaxTmqS8El3zjRWyu1hKVOxLNqauKFffCtrb9kP Sidw== X-Gm-Message-State: AC+VfDzuufdrQ5VqgcoRkysu4ql/CETaXRD3Nj4TJQMI0vroFguTXSGo egAi/5yLFDB0QVcRIE/iTNL6zw== X-Google-Smtp-Source: ACHHUZ4MOIYTHTGclDNGhT7EA/gcBVTkBZq3YDK2pAqHCZjwGgo+m2IybXiQCUxUe0jTf8EK3KJtfQ== X-Received: by 2002:a50:fc0a:0:b0:510:f3a6:d50 with SMTP id i10-20020a50fc0a000000b00510f3a60d50mr195454edr.36.1685378774115; Mon, 29 May 2023 09:46:14 -0700 (PDT) Received: from ph18.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id f4-20020aa7d844000000b0050d89daaa70sm3248578eds.2.2023.05.29.09.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 09:46:13 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Date: Mon, 29 May 2023 18:46:03 +0200 Message-ID: <20230529164605.3552619-4-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230529164605.3552619-1-bero@baylibre.com> References: <20230529164605.3552619-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add LVTS Driver support for MT8192. Co-developed-by : N=C3=ADcolas F. R. A. Prado Signed-off-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: Bernhard Rosenkr=C3=A4nzer Reviewed-by: Matthias Brugger --- drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index 5ea8a9d569ea6..d5e5214784ece 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -80,6 +80,7 @@ #define LVTS_MSR_FILTERED_MODE 1 =20 #define LVTS_HW_SHUTDOWN_MT8195 105000 +#define LVTS_HW_SHUTDOWN_MT8192 105000 =20 static int golden_temp =3D LVTS_GOLDEN_TEMP_DEFAULT; static int coeff_b =3D LVTS_COEFF_B; @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_da= ta_ctrl[] =3D { } }; =20 +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] =3D { + { + .cal_offset =3D { 0x04, 0x08 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU0 }, + { .dt_id =3D MT8192_MCU_BIG_CPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset =3D { 0x0c, 0x10 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_BIG_CPU2 }, + { .dt_id =3D MT8192_MCU_BIG_CPU3 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + }, + { + .cal_offset =3D { 0x14, 0x18, 0x1c, 0x20 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_MCU_LITTLE_CPU0 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU1 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU2 }, + { .dt_id =3D MT8192_MCU_LITTLE_CPU3 } + }, + .num_lvts_sensor =3D 4, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + .mode =3D LVTS_MSR_FILTERED_MODE, + } +}; + +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] =3D { + { + .cal_offset =3D { 0x24, 0x28 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_VPU0 }, + { .dt_id =3D MT8192_AP_VPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x0, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x2c, 0x30 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_GPU0 }, + { .dt_id =3D MT8192_AP_GPU1 } + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x100, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x34, 0x38 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_INFRA }, + { .dt_id =3D MT8192_AP_CAM }, + }, + .num_lvts_sensor =3D 2, + .offset =3D 0x200, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + }, + { + .cal_offset =3D { 0x3c, 0x40, 0x44 }, + .lvts_sensor =3D { + { .dt_id =3D MT8192_AP_MD0 }, + { .dt_id =3D MT8192_AP_MD1 }, + { .dt_id =3D MT8192_AP_MD2 } + }, + .num_lvts_sensor =3D 3, + .offset =3D 0x300, + .hw_tshut_temp =3D LVTS_HW_SHUTDOWN_MT8192, + } +}; + static const struct lvts_data mt8195_lvts_mcu_data =3D { .lvts_ctrl =3D mt8195_lvts_mcu_data_ctrl, .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = =3D { .num_lvts_ctrl =3D ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), }; =20 +static const struct lvts_data mt8192_lvts_mcu_data =3D { + .lvts_ctrl =3D mt8192_lvts_mcu_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), +}; + +static const struct lvts_data mt8192_lvts_ap_data =3D { + .lvts_ctrl =3D mt8192_lvts_ap_data_ctrl, + .num_lvts_ctrl =3D ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8195-lvts-mcu", .data =3D &mt8195_lvts_mcu_= data }, { .compatible =3D "mediatek,mt8195-lvts-ap", .data =3D &mt8195_lvts_ap_da= ta }, + { .compatible =3D "mediatek,mt8192-lvts-mcu", .data =3D &mt8192_lvts_mcu_= data }, + { .compatible =3D "mediatek,mt8192-lvts-ap", .data =3D &mt8192_lvts_ap_da= ta }, {}, }; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id f4-20020aa7d844000000b0050d89daaa70sm3248578eds.2.2023.05.29.09.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 09:46:15 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Date: Mon, 29 May 2023 18:46:04 +0200 Message-ID: <20230529164605.3552619-5-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230529164605.3552619-1-bero@baylibre.com> References: <20230529164605.3552619-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Add thermal nodes and thermal zones for the mt8192. The mt8192 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado [bero@baylibre.com: cosmetic changes] Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++ 1 file changed, 454 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts= /mediatek/mt8192.dtsi index 5c30caf740265..330c5bb4ebc85 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -14,6 +14,8 @@ #include #include #include +#include +#include =20 / { compatible =3D "mediatek,mt8192"; @@ -71,6 +73,7 @@ cpu0: cpu@0 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu1: cpu@100 { @@ -88,6 +91,7 @@ cpu1: cpu@100 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu2: cpu@200 { @@ -105,6 +109,7 @@ cpu2: cpu@200 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu3: cpu@300 { @@ -122,6 +127,7 @@ cpu3: cpu@300 { d-cache-sets =3D <128>; next-level-cache =3D <&l2_0>; capacity-dmips-mhz =3D <530>; + #cooling-cells =3D <2>; }; =20 cpu4: cpu@400 { @@ -139,6 +145,7 @@ cpu4: cpu@400 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu5: cpu@500 { @@ -156,6 +163,7 @@ cpu5: cpu@500 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu6: cpu@600 { @@ -173,6 +181,7 @@ cpu6: cpu@600 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu7: cpu@700 { @@ -190,6 +199,7 @@ cpu7: cpu@700 { d-cache-sets =3D <256>; next-level-cache =3D <&l2_1>; capacity-dmips-mhz =3D <1024>; + #cooling-cells =3D <2>; }; =20 cpu-map { @@ -771,6 +781,17 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts_ap: thermal-sensor@1100b000 { + compatible =3D "mediatek,mt8192-lvts-ap"; + reg =3D <0 0x1100b000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + pwm0: pwm@1100e000 { compatible =3D "mediatek,mt8183-disp-pwm"; reg =3D <0 0x1100e000 0 0x1000>; @@ -1097,6 +1118,17 @@ nor_flash: spi@11234000 { status =3D "disabled"; }; =20 + lvts_mcu: thermal-sensor@11278000 { + compatible =3D "mediatek,mt8192-lvts-mcu"; + reg =3D <0 0x11278000 0 0x1000>; + interrupts =3D ; + clocks =3D <&infracfg CLK_INFRA_THERM>; + resets =3D <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1>; + nvmem-cell-names =3D "lvts-calib-data-1"; + #thermal-sensor-cells =3D <1>; + }; + efuse: efuse@11c10000 { compatible =3D "mediatek,mt8192-efuse", "mediatek,efuse"; reg =3D <0 0x11c10000 0 0x1000>; @@ -1823,4 +1855,426 @@ larb2: larb@1f002000 { power-domains =3D <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU0>; + + trips { + cpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu0_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU1>; + + trips { + cpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu1_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU2>; + + trips { + cpu2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu2_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_LITTLE_CPU3>; + + trips { + cpu3_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu3_alert>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU0>; + + trips { + cpu4_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu4_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu5-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU1>; + + trips { + cpu5_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu5_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu6-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU2>; + + trips { + cpu6_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu6_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu7-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_mcu MT8192_MCU_BIG_CPU3>; + + trips { + cpu7_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu7_alert>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + vpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU0>; + + trips { + vpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + vpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_VPU1>; + + trips { + vpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + vpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU0>; + + trips { + gpu0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_GPU1>; + + trips { + gpu1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + gpu1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + infra-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_INFRA>; + + trips { + infra_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + infra_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + cam-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_CAM>; + + trips { + cam_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cam_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md0-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD0>; + + trips { + md0_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md0_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md1-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD1>; + + trips { + md1_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md1_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + + md2-thermal { + polling-delay =3D <1000>; + polling-delay-passive =3D <250>; + thermal-sensors =3D <&lvts_ap MT8192_AP_MD2>; + + trips { + md2_alert: trip-alert { + temperature =3D <85000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + md2_crit: trip-crit { + temperature =3D <100000>; + hysteresis =3D <2000>; + type =3D "critical"; + }; + }; + }; + }; }; --=20 2.41.0.rc2 From nobody Fri Sep 20 20:29:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6040DC7EE23 for ; Mon, 29 May 2023 16:46:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229668AbjE2Qqf (ORCPT ); Mon, 29 May 2023 12:46:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229662AbjE2QqU (ORCPT ); Mon, 29 May 2023 12:46:20 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AD77B5 for ; Mon, 29 May 2023 09:46:18 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-5147dce372eso4999100a12.0 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id f4-20020aa7d844000000b0050d89daaa70sm3248578eds.2.2023.05.29.09.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 May 2023 09:46:16 -0700 (PDT) From: =?UTF-8?q?Bernhard=20Rosenkr=C3=A4nzer?= To: daniel.lezcano@linaro.org, angelogioacchino.delregno@collabora.com, rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, rdunlap@infradead.org, ye.xingchen@zte.com.cn, p.zabel@pengutronix.de Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, wenst@chromium.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, abailon@baylibre.com, amergnat@baylibre.com, khilman@baylibre.com Subject: [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Date: Mon, 29 May 2023 18:46:05 +0200 Message-ID: <20230529164605.3552619-6-bero@baylibre.com> X-Mailer: git-send-email 2.41.0.rc2 In-Reply-To: <20230529164605.3552619-1-bero@baylibre.com> References: <20230529164605.3552619-1-bero@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Balsam CHIHI Update LVTS calibration data documentation for mt8192 and mt8195. Signed-off-by: Balsam CHIHI Reviewed-by: N=C3=ADcolas F. R. A. Prado [bero@baylibre.com: Fix issues pointed out by N=C3=ADcolas F. R. A. Prado <= nfraprado@collabora.com>] Signed-off-by: Bernhard Rosenkr=C3=A4nzer --- drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/medi= atek/lvts_thermal.c index d5e5214784ece..9185d02003633 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -531,7 +531,8 @@ static int lvts_sensor_init(struct device *dev, struct = lvts_ctrl *lvts_ctrl, * The efuse blob values follows the sensor enumeration per thermal * controller. The decoding of the stream is as follow: * - * stream index map for MCU Domain : + * MT8195 : + * Stream index map for MCU Domain mt8195 : * * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 @@ -542,7 +543,7 @@ static int lvts_sensor_init(struct device *dev, struct = lvts_ctrl *lvts_ctrl, * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----se= nsor#6-----> <-----sensor#7-----> * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | = 0x1D | 0x1E | 0x1F | 0x20 | 0x21 * - * stream index map for AP Domain : + * Stream index map for AP Domain mt8195 : * * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A @@ -556,6 +557,32 @@ static int lvts_sensor_init(struct device *dev, struct= lvts_ctrl *lvts_ctrl, * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 * + * MT8192 : + * Stream index map for MCU Domain mt8192 : + * + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> + * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | = 0x0B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 + * + * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-= ----> <-----sensor#7-----> + * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | = 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 + * + * Stream index map for AP Domain mt8192 : + * + * <-----sensor#0-----> <-----sensor#1-----> + * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B + * + * <-----sensor#2-----> <-----sensor#3-----> + * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 + * + * <-----sensor#4-----> <-----sensor#5-----> + * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B + * + * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-= ----> + * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | = 0x46 | 0x47 + * * The data description gives the offset of the calibration data in * this bytes stream for each sensor. */ --=20 2.41.0.rc2