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Mon, 29 May 2023 06:55:15 -0700 From: Peter De Schrijver To: Peter De Schrijver , , , CC: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joe Perches , , , , Krzysztof Kozlowski , Thierry Reding Subject: [PATCH v5 1/5] dt-bindings: mailbox: tegra: Document Tegra264 HSP Date: Mon, 29 May 2023 16:50:43 +0300 Message-ID: <20230529135044.2746339-2-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com> References: <20230529135044.2746339-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT017:EE_|BL1PR12MB5708:EE_ X-MS-Office365-Filtering-Correlation-Id: 794a9bf0-3c74-4d0d-6fb1-08db604c5b93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SghPGzXuc/LScqoEHyur2I02b2IXWJLkPUfjB0PQ8IrhQJTqTy/GI2gctFNWz7wOzjx0OSE+s9HYWqaOS969sp31jPq73ZBMBV00ES41sTdJgUKdy3Yapydo8ddgHP8ZcTSA4jxHhhea07WTnzx2tWdYmz78gM9re+ni4lSZ6wlnmma3vvYZ6GAQ5xInPhXC9y7ikzUHhZcxuJ9fK/gqymyAi13NktzUOBYwSCU6v1gtRYSAdyziz+o2rRM63iZoxaatQ7X/qKGHo/81HCBG41opZs6fQk2iWPAZ+EIONnmBkBfAW1yclKejKKWCarj2jWrUA/TuNW7McUt+R3YC7n8WAO7T4bcBzWELlCxnhJ0WE8ZD6PdbXR0LsTEcBMlitKSFDqIRFU/Ty4yjV1cY+ne+cJMfOo0k1f04tBNmSFDm/V46gfSW3y83kkrVS/dO2dGcfxHogBTEbBeaTiKRn1PrLDNK13hklrK34p0XEJwA/3AzOfYre+LDWJRFIZ/VldPPgAuSXA98O4D5KImS4dcKBAVvHaDvK4goYAWLL0YQqPLiNa1BFzVuTxmocIgSOigVxOsmS7p89Nd7ZEBcSztpXEG6T8rs15D5rEPJld6cNqNcJCss1Vjykk/Gd3OB1uRMB7n+OTQQDGADf+uissY//W38Y199/AZysgjyibfduAAzeRG9SxXuyN6FTTjzzy+f54Yi4XOudpyEdUvI4B/Ng6wSrVUBxvrL4tcmRWNUKX4+EPQGScVMZt0mdDVB X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199021)(36840700001)(46966006)(40470700004)(40460700003)(478600001)(70586007)(70206006)(110136005)(54906003)(6636002)(4326008)(316002)(36756003)(86362001)(83380400001)(47076005)(36860700001)(1076003)(26005)(336012)(426003)(186003)(107886003)(5660300002)(41300700001)(82310400005)(8936002)(8676002)(7416002)(15650500001)(2906002)(7696005)(6666004)(40480700001)(2616005)(356005)(82740400003)(7636003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:55:27.2133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 794a9bf0-3c74-4d0d-6fb1-08db604c5b93 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5708 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the compatible string for the HSP block found on the Tegra264 SoC. The HSP block in Tegra264 is not register compatible with the one in Tegra194 or Tegra234 hence there is no fallback compatibility string. Acked-by: Krzysztof Kozlowski Acked-by: Thierry Reding Signed-off-by: Peter De Schrijver --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.= yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index a3e87516d637..2d14fc948999 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -66,6 +66,7 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - const: nvidia,tegra264-hsp - items: - const: nvidia,tegra234-hsp - const: nvidia,tegra194-hsp --=20 2.34.1 From nobody Sun Feb 8 00:35:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53755C77B7A for ; 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Mon, 29 May 2023 06:55:41 -0700 From: Peter De Schrijver To: Peter De Schrijver , , , CC: Jassi Brar , Krzysztof Kozlowski , Conor Dooley , "Joe Perches" , , , Thierry Reding Subject: [PATCH v5 2/5] mailbox: tegra: add support for Tegra264 Date: Mon, 29 May 2023 16:50:45 +0300 Message-ID: <20230529135044.2746339-3-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com> References: <20230529135044.2746339-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT116:EE_|SN7PR12MB7953:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bc6f0d4-e358-4d8f-47db-08db604c6d4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: evNg9xH10tM0c8xfmDpaf+yWZyyM9S9qnSSlmYiW7geu/hE7yA4GCwZwPM+LGngeB/PLMKXRHwov5hrFtR8mYqul8FrTNN8RYvSi+AFYGTkVTOYVr4nyZot8lpenf9M30nzQuUJDv6syOT6htdl7KBpTtGQxNwnGYzx/+QckrDR8VfI0kpldjw5GOXNjlLzRmQvFZ+2SOi54rQBt0YIyWpUY8RQg8NOH2SlJuXvbGPw+jpMXnccihWk4kvTX67IN2ScbeuLyJXSJF9rFi8VUOvVylMoPCs+7ZsIbGsIECtW5Uz3Ion9Hhl6zmY/PvTp/jWV9vF7YPRr2biXEkMTkbz+rBX4maTh4/Es8Y9zdfBnhIwF5FciP0cNizJ1W+zR2uoiwYncuD4Yk4ceImjv6mIyxzWwKfzGSqAj5tX2C0Ks5w9DTdv/FVylkAbdu+OtTlZ4wL4MYSFFOrRdwlyA+gayfklN87ChVvSp+sB1dPF5VKjcIevIINu6hGNCFNGkiBtzN4ulcKwLpZzOQAnWmfk35vnzxqezWIaQExCFhbZD59sVzCw052U3NgQ78s1ffG+zKqchYNwBCXCtI5pUXio1mIAoxMjVoXmCJpJLX5lZXZw7umJleFFz+zbj1dzzLufo1rg6loABq4EB6Kedws+a9YEn6WMaNXaVHyuBPTedzN6QN8lf1F83Tl6b2Fk/6WYgos3yhXcBNwK4dQUy6MJKfoW+54aEVbh6DG0ZwazZCxWHKGCTCPrfSujnVtDdj X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(136003)(39850400004)(451199021)(40470700004)(46966006)(36840700001)(2906002)(186003)(15650500001)(1076003)(36860700001)(107886003)(5660300002)(82740400003)(8676002)(8936002)(54906003)(478600001)(110136005)(356005)(7636003)(47076005)(336012)(83380400001)(26005)(2616005)(426003)(86362001)(7696005)(82310400005)(41300700001)(316002)(70206006)(70586007)(36756003)(6636002)(40460700003)(4326008)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:55:56.8991 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bc6f0d4-e358-4d8f-47db-08db604c6d4c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT116.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7953 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Stefan Kristiansson Tegra264 has a slightly different doorbell register layout than previous chips. Acked-by: Thierry Reding Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- drivers/mailbox/tegra-hsp.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 573481e436f5..7f98e7436d94 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -97,6 +97,7 @@ struct tegra_hsp_soc { const struct tegra_hsp_db_map *map; bool has_per_mb_ie; bool has_128_bit_mb; + unsigned int reg_stride; }; =20 struct tegra_hsp { @@ -279,7 +280,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const = char *name, return ERR_PTR(-ENOMEM); =20 offset =3D (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; - offset +=3D index * 0x100; + offset +=3D index * hsp->soc->reg_stride; =20 db->channel.regs =3D hsp->regs + offset; db->channel.hsp =3D hsp; @@ -916,24 +917,35 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D false, .has_128_bit_mb =3D false, + .reg_stride =3D 0x100, }; =20 static const struct tegra_hsp_soc tegra194_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D true, .has_128_bit_mb =3D false, + .reg_stride =3D 0x100, }; =20 static const struct tegra_hsp_soc tegra234_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D false, .has_128_bit_mb =3D true, + .reg_stride =3D 0x100, +}; + +static const struct tegra_hsp_soc tegra264_hsp_soc =3D { + .map =3D tegra186_hsp_db_map, + .has_per_mb_ie =3D false, + .has_128_bit_mb =3D true, + .reg_stride =3D 0x1000, }; =20 static const struct of_device_id tegra_hsp_match[] =3D { { .compatible =3D "nvidia,tegra186-hsp", .data =3D &tegra186_hsp_soc }, { .compatible =3D "nvidia,tegra194-hsp", .data =3D &tegra194_hsp_soc }, { .compatible =3D "nvidia,tegra234-hsp", .data =3D &tegra234_hsp_soc }, + { .compatible =3D "nvidia,tegra264-hsp", .data =3D &tegra264_hsp_soc }, { } }; =20 --=20 2.34.1 From nobody Sun Feb 8 00:35:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97145C77B7A for ; Mon, 29 May 2023 13:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229807AbjE2N7g (ORCPT ); Mon, 29 May 2023 09:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230146AbjE2N7W (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:57:57.3973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f4418cf-4a07-4561-7738-08db604cb51c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8851 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add bindings for DRAM MRQ GSC support. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Reviewed-by: Conor Dooley --- .../nvidia,tegra264-bpmp-shmem.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidi= a,tegra264-bpmp-shmem.yaml diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra= 264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvi= dia,tegra264-bpmp-shmem.yaml new file mode 100644 index 000000000000..f9b2f0fdc282 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpm= p-shmem.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-sh= mem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra CPU-NS - BPMP IPC reserved memory + +maintainers: + - Peter De Schrijver + +description: | + Define a memory region used for communication between CPU-NS and BPMP. + Typically this node is created by the bootloader as the physical address + has to be known to both CPU-NS and BPMP for correct IPC operation. + The memory region is defined using a child node under /reserved-memory. + The sub-node is named shmem@
. + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: nvidia,tegra264-bpmp-shmem + + reg: + description: The physical address and size of the shared SDRAM region + +unevaluatedProperties: false + +required: + - compatible + - reg + - no-map + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + dram_cpu_bpmp_mail: shmem@f1be0000 { + compatible =3D "nvidia,tegra264-bpmp-shmem"; + reg =3D <0x0 0xf1be0000 0x0 0x2000>; + no-map; + }; + }; +... --=20 2.34.1 From nobody Sun Feb 8 00:35:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7C30C7EE33 for ; Mon, 29 May 2023 14:00:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230138AbjE2OAS (ORCPT ); Mon, 29 May 2023 10:00:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230189AbjE2N7o (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:58:26.2529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d95b816-2c2a-4649-52d8-08db604cc648 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8176 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Reviewed-by: Conor Dooley --- .../firmware/nvidia,tegra186-bpmp.yaml | 39 ++++++++++++++++--- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpm= p.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.ya= ml index 833c07f1685c..c43d17f6e96b 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -57,8 +57,11 @@ description: | "#address-cells" or "#size-cells" property. =20 The shared memory area for the IPC TX and RX between CPU and BPMP are - predefined and work on top of sysram, which is an SRAM inside the - chip. See ".../sram/sram.yaml" for the bindings. + predefined and work on top of either sysram, which is an SRAM inside the + chip, or in normal SDRAM. + See ".../sram/sram.yaml" for the bindings for the SRAM case. + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for + the SDRAM case. =20 properties: compatible: @@ -81,6 +84,11 @@ properties: minItems: 2 maxItems: 2 =20 + memory-region: + description: phandle to reserved memory region used for IPC between + CPU-NS and BPMP. + maxItems: 1 + "#clock-cells": const: 1 =20 @@ -115,10 +123,15 @@ properties: =20 additionalProperties: false =20 +oneOf: + - required: + - memory-region + - required: + - shmem + required: - compatible - mboxes - - shmem - "#clock-cells" - "#power-domain-cells" - "#reset-cells" @@ -165,8 +178,7 @@ examples: <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names =3D "read", "write", "dma-mem", "dma-write"; iommus =3D <&smmu TEGRA186_SID_BPMP>; - mboxes =3D <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; + mboxes =3D <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_B= PMP>; shmem =3D <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells =3D <1>; #power-domain-cells =3D <1>; @@ -184,3 +196,20 @@ examples: #thermal-sensor-cells =3D <1>; }; }; + + - | + #include + + bpmp { + compatible =3D "nvidia,tegra186-bpmp"; + interconnects =3D <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names =3D "read", "write", "dma-mem", "dma-write"; + mboxes =3D <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_B= PMP>; + memory-region =3D <&dram_cpu_bpmp_mail>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + }; --=20 2.34.1 From nobody Sun Feb 8 00:35:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14FCFC7EE2E for ; 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Mon, 29 May 2023 06:58:34 -0700 From: Peter De Schrijver To: Peter De Schrijver , , , CC: Jassi Brar , Krzysztof Kozlowski , Conor Dooley , "Joe Perches" , , Subject: [PATCH v5 5/5] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs Date: Mon, 29 May 2023 16:50:51 +0300 Message-ID: <20230529135044.2746339-6-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230529135044.2746339-1-pdeschrijver@nvidia.com> References: <20230529135044.2746339-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT068:EE_|SA1PR12MB7127:EE_ X-MS-Office365-Filtering-Correlation-Id: e38a3554-e74f-4fdc-f751-08db604cd34b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gEoc+3i1PHsb3IXSwwnrq/ilqGd9+l8Ls5Z4o74sOvikKyaYBN0jLBYkz7NrwvsjxHFtyhFxTlqFkQ7LLYqCviwi07mYdd6Re/8mtyaJ9vDvCIbmZuGF9mXNJTdUoZDrShTdRwCUn79EHdA5X6/ye1Z5rkkO7H24fjNrGua3wXVGxpSCYGs62vGqGMCPE/Krg38XuJ9d0z+RjK7sWP8lBEuU0Le2fT0OkayzwVU/rJ0gupjGuvO6dtoIrIA4mo5ypzJCTgxGUILiWWF/RPEUy1UxoXG+gmCWyY7ahufTLVBSch5DyQhcIVpbazpfHqXHsS0C1cUlOuQXqokR3ipdp5NADma+QzE4mihhaP1mDgcFs/GD8rqKCd52cXQjjyTKyyTAlENN8ep+OGuakyyWnz+ea5+jZiuG162zmVYvdPCE9JbOEJAhZ0Y7q1/nG9QCOv7QBjTwycmmRNgipkWHcR6P0/iOiJRO+Ocp5yZuhCYeC6a32xTzlZEWHunmfKVSs9D4I5KxWPB2YHZUVi4tA2KfJm2DLSzLsvZd065Z0kQcckWHjaiejbb7oJmzfHVWgeZujNuNQJ8YuIv4Oe7tBNoTUZ/HZkE90VJGsmissqPcV5YgSNW/7k1qUsX2EkSThgcO3QrVhENmT78r0iJ+RMtVHZX0sZjbU/bn56jevTUhaA7OJ010UGmYpGBazmcymzuy+D+MQsY0OwPXqxiINba015Xqowjo7aEOE/zO8xf8L4sUw9ttxoOrGVGXjriI X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230028)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(336012)(426003)(478600001)(83380400001)(40460700003)(36860700001)(40480700001)(47076005)(5660300002)(186003)(6636002)(4326008)(86362001)(7696005)(8676002)(8936002)(2906002)(82310400005)(41300700001)(316002)(6666004)(82740400003)(7636003)(356005)(1076003)(26005)(70586007)(70206006)(2616005)(54906003)(110136005)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2023 13:58:48.0246 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e38a3554-e74f-4fdc-f751-08db604cd34b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT068.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7127 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement support for DRAM MRQ GSCs. Signed-off-by: Peter De Schrijver --- drivers/firmware/tegra/bpmp-tegra186.c | 232 ++++++++++++++++++------- drivers/firmware/tegra/bpmp.c | 4 +- 2 files changed, 168 insertions(+), 68 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-tegra186.c b/drivers/firmware/tegr= a/bpmp-tegra186.c index 2e26199041cd..d1c1af793b6f 100644 --- a/drivers/firmware/tegra/bpmp-tegra186.c +++ b/drivers/firmware/tegra/bpmp-tegra186.c @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include =20 #include @@ -13,12 +15,22 @@ =20 #include "bpmp-private.h" =20 +/* Discriminating enum for the union below */ +enum tegra_bpmp_mem_type { TEGRA_INVALID, TEGRA_SRAM, TEGRA_DRAM }; struct tegra186_bpmp { struct tegra_bpmp *parent; =20 + enum tegra_bpmp_mem_type type; struct { - struct gen_pool *pool; - void __iomem *virt; + union { + struct { + void __iomem *virt; + struct gen_pool *pool; + } sram; + struct { + void *virt; + } dram; + }; dma_addr_t phys; } tx, rx; =20 @@ -26,6 +38,7 @@ struct tegra186_bpmp { struct mbox_client client; struct mbox_chan *channel; } mbox; + }; =20 static inline struct tegra_bpmp * @@ -118,8 +131,17 @@ static int tegra186_bpmp_channel_init(struct tegra_bpm= p_channel *channel, queue_size =3D tegra_ivc_total_queue_size(message_size); offset =3D queue_size * index; =20 - iosys_map_set_vaddr_iomem(&rx, priv->rx.virt + offset); - iosys_map_set_vaddr_iomem(&tx, priv->tx.virt + offset); + if (priv->type =3D=3D TEGRA_SRAM) { + iosys_map_set_vaddr_iomem(&rx, priv->rx.sram.virt + offset); + iosys_map_set_vaddr_iomem(&tx, priv->tx.sram.virt + offset); + } else if (priv->type =3D=3D TEGRA_DRAM) { + iosys_map_set_vaddr(&rx, priv->rx.dram.virt + offset); + iosys_map_set_vaddr(&tx, priv->tx.dram.virt + offset); + } else { + dev_err(bpmp->dev, "Inconsistent state %d of priv->type detected in %s\n= ", + priv->type, __func__); + return -EINVAL; + } =20 err =3D tegra_ivc_init(channel->ivc, NULL, &rx, priv->rx.phys + offset, &= tx, priv->tx.phys + offset, 1, message_size, tegra186_bpmp_ivc_notify, @@ -158,54 +180,135 @@ static void mbox_handle_rx(struct mbox_client *clien= t, void *data) tegra_bpmp_handle_rx(bpmp); } =20 -static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +static void tegra186_bpmp_teardown_channels(struct tegra_bpmp *bpmp) { - struct tegra186_bpmp *priv; - unsigned int i; - int err; + size_t i; + struct tegra186_bpmp *priv =3D bpmp->priv; =20 - priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; + for (i =3D 0; i < bpmp->threaded.count; i++) { + if (!bpmp->threaded_channels[i].bpmp) + continue; =20 - bpmp->priv =3D priv; - priv->parent =3D bpmp; + tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); + } =20 - priv->tx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); - if (!priv->tx.pool) { + tegra186_bpmp_channel_cleanup(bpmp->rx_channel); + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + + if (priv->type =3D=3D TEGRA_SRAM) { + gen_pool_free(priv->tx.sram.pool, (unsigned long)priv->tx.sram.virt, 409= 6); + gen_pool_free(priv->rx.sram.pool, (unsigned long)priv->rx.sram.virt, 409= 6); + } else if (priv->type =3D=3D TEGRA_DRAM) { + memunmap(priv->tx.dram.virt); + } +} + +static int tegra186_bpmp_sram_init(struct tegra_bpmp *bpmp) +{ + int err; + struct tegra186_bpmp *priv =3D bpmp->priv; + + priv->tx.sram.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 0); + if (!priv->tx.sram.pool) { dev_err(bpmp->dev, "TX shmem pool not found\n"); return -EPROBE_DEFER; } =20 - priv->tx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->tx.pool, 4096,= &priv->tx.phys); - if (!priv->tx.virt) { + priv->tx.sram.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->tx.sram.p= ool, 4096, + &priv->tx.phys); + if (!priv->tx.sram.virt) { dev_err(bpmp->dev, "failed to allocate from TX pool\n"); return -ENOMEM; } =20 - priv->rx.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); - if (!priv->rx.pool) { + priv->rx.sram.pool =3D of_gen_pool_get(bpmp->dev->of_node, "shmem", 1); + if (!priv->rx.sram.pool) { dev_err(bpmp->dev, "RX shmem pool not found\n"); err =3D -EPROBE_DEFER; goto free_tx; } =20 - priv->rx.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->rx.pool, 4096,= &priv->rx.phys); - if (!priv->rx.virt) { + priv->rx.sram.virt =3D (void __iomem *)gen_pool_dma_alloc(priv->rx.sram.p= ool, 4096, + &priv->rx.phys); + if (!priv->rx.sram.virt) { dev_err(bpmp->dev, "failed to allocate from RX pool\n"); err =3D -ENOMEM; goto free_tx; } =20 + priv->type =3D TEGRA_SRAM; + + return 0; + +free_tx: + gen_pool_free(priv->tx.sram.pool, (unsigned long)priv->tx.sram.virt, 4096= ); + + return err; +} + +static int tegra186_bpmp_dram_init(struct tegra_bpmp *bpmp) +{ + int err; + resource_size_t size; + struct resource res; + struct device_node *np; + struct tegra186_bpmp *priv =3D bpmp->priv; + + np =3D of_parse_phandle(bpmp->dev->of_node, "memory-region", 0); + if (!np) + return -ENOENT; + + err =3D of_address_to_resource(np, 0, &res); + if (err) { + dev_warn(bpmp->dev, "Parsing memory region returned: %d\n", err); + return -EINVAL; + } + + size =3D resource_size(&res); + if (size < SZ_8K) { + dev_warn(bpmp->dev, "DRAM region must be larger than 8 KiB\n"); + return -EINVAL; + } + + priv->tx.phys =3D res.start; + priv->rx.phys =3D res.start + SZ_4K; + + priv->tx.dram.virt =3D memremap(priv->tx.phys, size, MEMREMAP_WC); + if (priv->tx.dram.virt =3D=3D NULL) { + dev_warn(bpmp->dev, "DRAM region mapping failed\n"); + return -EINVAL; + } + priv->rx.dram.virt =3D priv->tx.dram.virt + SZ_4K; + priv->type =3D TEGRA_DRAM; + + return 0; +} + +static int tegra186_bpmp_setup_channels(struct tegra_bpmp *bpmp) +{ + int err; + size_t i; + struct tegra186_bpmp *priv =3D bpmp->priv; + + priv->type =3D TEGRA_INVALID; + + err =3D tegra186_bpmp_dram_init(bpmp); + if (err =3D=3D -ENOENT) + err =3D tegra186_bpmp_sram_init(bpmp); + if (err < 0) + return err; + err =3D tegra186_bpmp_channel_init(bpmp->tx_channel, bpmp, bpmp->soc->channels.cpu_tx.offset); if (err < 0) - goto free_rx; + return err; =20 err =3D tegra186_bpmp_channel_init(bpmp->rx_channel, bpmp, bpmp->soc->channels.cpu_rx.offset); - if (err < 0) - goto cleanup_tx_channel; + if (err < 0) { + tegra186_bpmp_channel_cleanup(bpmp->tx_channel); + return err; + } =20 for (i =3D 0; i < bpmp->threaded.count; i++) { unsigned int index =3D bpmp->soc->channels.thread.offset + i; @@ -213,9 +316,42 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) err =3D tegra186_bpmp_channel_init(&bpmp->threaded_channels[i], bpmp, index); if (err < 0) - goto cleanup_channels; + break; } =20 + if (err < 0) + tegra186_bpmp_teardown_channels(bpmp); + + return err; +} + +static void tegra186_bpmp_reset_channels(struct tegra_bpmp *bpmp) +{ + size_t i; + + tegra186_bpmp_channel_reset(bpmp->tx_channel); + tegra186_bpmp_channel_reset(bpmp->rx_channel); + + for (i =3D 0; i < bpmp->threaded.count; i++) + tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); +} + +static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) +{ + int err; + struct tegra186_bpmp *priv; + + priv =3D devm_kzalloc(bpmp->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + bpmp->priv =3D priv; + priv->parent =3D bpmp; + + err =3D tegra186_bpmp_setup_channels(bpmp); + if (err < 0) + return err; + /* mbox registration */ priv->mbox.client.dev =3D bpmp->dev; priv->mbox.client.rx_callback =3D mbox_handle_rx; @@ -226,63 +362,27 @@ static int tegra186_bpmp_init(struct tegra_bpmp *bpmp) if (IS_ERR(priv->mbox.channel)) { err =3D PTR_ERR(priv->mbox.channel); dev_err(bpmp->dev, "failed to get HSP mailbox: %d\n", err); - goto cleanup_channels; + tegra186_bpmp_teardown_channels(bpmp); + return err; } =20 - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); =20 return 0; - -cleanup_channels: - for (i =3D 0; i < bpmp->threaded.count; i++) { - if (!bpmp->threaded_channels[i].bpmp) - continue; - - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - } - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); -cleanup_tx_channel: - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); -free_rx: - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); -free_tx: - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); - - return err; } =20 static void tegra186_bpmp_deinit(struct tegra_bpmp *bpmp) { struct tegra186_bpmp *priv =3D bpmp->priv; - unsigned int i; =20 mbox_free_channel(priv->mbox.channel); =20 - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_cleanup(&bpmp->threaded_channels[i]); - - tegra186_bpmp_channel_cleanup(bpmp->rx_channel); - tegra186_bpmp_channel_cleanup(bpmp->tx_channel); - - gen_pool_free(priv->rx.pool, (unsigned long)priv->rx.virt, 4096); - gen_pool_free(priv->tx.pool, (unsigned long)priv->tx.virt, 4096); + tegra186_bpmp_teardown_channels(bpmp); } =20 static int tegra186_bpmp_resume(struct tegra_bpmp *bpmp) { - unsigned int i; - - /* reset message channels */ - tegra186_bpmp_channel_reset(bpmp->tx_channel); - tegra186_bpmp_channel_reset(bpmp->rx_channel); - - for (i =3D 0; i < bpmp->threaded.count; i++) - tegra186_bpmp_channel_reset(&bpmp->threaded_channels[i]); + tegra186_bpmp_reset_channels(bpmp); =20 return 0; } diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 8b5e5daa9fae..17bd3590aaa2 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -735,6 +735,8 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) if (!bpmp->threaded_channels) return -ENOMEM; =20 + platform_set_drvdata(pdev, bpmp); + err =3D bpmp->soc->ops->init(bpmp); if (err < 0) return err; @@ -758,8 +760,6 @@ static int tegra_bpmp_probe(struct platform_device *pde= v) =20 dev_info(&pdev->dev, "firmware: %.*s\n", (int)sizeof(tag), tag); =20 - platform_set_drvdata(pdev, bpmp); - err =3D of_platform_default_populate(pdev->dev.of_node, NULL, &pdev->dev); if (err < 0) goto free_mrq; --=20 2.34.1