From nobody Sun Feb 8 14:41:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 843A0C77B7A for ; Mon, 29 May 2023 10:49:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230117AbjE2Ktf (ORCPT ); Mon, 29 May 2023 06:49:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229505AbjE2Kta (ORCPT ); Mon, 29 May 2023 06:49:30 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A402C2; Mon, 29 May 2023 03:49:29 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34TAnLig010862; Mon, 29 May 2023 05:49:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685357361; bh=CK5eM0NQ5PRib0LLBfl6OQPhUVholArJFu75s4WD1P0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=l6Dj5q7mJgxeD2YHFv5TDpZKOeotC8nOTLowd7YODB0Oa4MttIVCq/J8mnAt8AubN 1u9/ju0ms7PjbZgTXCFtH8KPnz6xA2CF3LCWc4vmvgB00x5LSiuKqXj0UdVQRzQEDs lRBaT0ywxz/5HwrjMPJN+HwBbOSYz5zzenbI/00g= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34TAnLj2007873 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 29 May 2023 05:49:21 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 29 May 2023 05:49:21 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 05:49:20 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34TAnDnn028618; Mon, 29 May 2023 05:49:17 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node Date: Mon, 29 May 2023 16:19:12 +0530 Message-ID: <20230529104913.560045-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529104913.560045-1-s-vadapalli@ti.com> References: <20230529104913.560045-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch. Add devicetree node for it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 6629b2989180..14dfef7b0758 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 { mux-reg-masks =3D <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; =20 + phy_gmii_sel_cpsw: phy@34 { + compatible =3D "ti,am654-phy-gmii-sel"; + reg =3D <0x34 0x4>; + #phy-cells =3D <1>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible =3D "mmio-mux"; reg =3D <0x80 0x10>; @@ -779,6 +785,69 @@ cpts@310d0000 { }; }; =20 + main_cpsw: ethernet@c200000 { + compatible =3D "ti,j721e-cpsw-nuss"; + reg =3D <0x00 0xc200000 0x00 0x200000>; + reg-names =3D "cpsw_nuss"; + ranges =3D <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-coherent; + clocks =3D <&k3_clks 28 28>; + clock-names =3D "fck"; + power-domains =3D <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas =3D <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names =3D "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status =3D "disabled"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw_port1: port@1 { + reg =3D <1>; + ti,mac-only; + label =3D "port1"; + phys =3D <&phy_gmii_sel_cpsw 1>; + status =3D "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible =3D "ti,cpsw-mdio","ti,davinci_mdio"; + reg =3D <0x00 0xf00 0x00 0x100>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&k3_clks 28 28>; + clock-names =3D "fck"; + bus_freq =3D <1000000>; + status =3D "disabled"; + }; + + cpts@3d000 { + compatible =3D "ti,am65-cpts"; + reg =3D <0x00 0x3d000 0x00 0x400>; + clocks =3D <&k3_clks 28 3>; + clock-names =3D "cpts"; + interrupts-extended =3D <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "cpts"; + ti,cpts-ext-ts-inputs =3D <4>; + ti,cpts-periodic-outputs =3D <2>; + }; + }; + usbss0: cdns-usb@4104000 { compatible =3D "ti,j721e-usb"; reg =3D <0x00 0x04104000 0x00 0x100>; --=20 2.25.1 From nobody Sun Feb 8 14:41:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF673C77B7A for ; Mon, 29 May 2023 10:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230521AbjE2Ktm (ORCPT ); Mon, 29 May 2023 06:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229965AbjE2Ktf (ORCPT ); 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Mon, 29 May 2023 05:49:24 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 29 May 2023 05:49:24 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34TAnDno028618; Mon, 29 May 2023 05:49:21 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH 2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI Date: Mon, 29 May 2023 16:19:13 +0530 Message-ID: <20230529104913.560045-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230529104913.560045-1-s-vadapalli@ti.com> References: <20230529104913.560045-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kishon Vijay Abraham I The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI Expansion Board connected to the J7 Common-Proc-Board. Use the overlay to enable this. Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address directly from U-Boot. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 2 + .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index c83c9d772b81..13db9b8dbe1d 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721e-sk.dtb # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-gesi-exp-board.dtbo =20 # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb @@ -49,3 +50,4 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-j721s2-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arc= h/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..9ababfeef904 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common pr= ocessor board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 =3D "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_pins_default: main-cpsw-mdio-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL = */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL = */ + >; + }; +}; + +&exp1 { + p15 { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios =3D <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "EXP_MUX2"; + }; +}; + +&main_cpsw { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rgmii1_pins_default>; +}; + +&main_cpsw_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_cpsw_mdio_pins_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + main_cpsw_phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&main_cpsw_port1 { + status =3D "okay"; + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&main_cpsw_phy0>; +}; --=20 2.25.1