From nobody Sun Feb 8 02:21:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7E98C77B7A for ; Mon, 29 May 2023 08:46:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231617AbjE2Iqg (ORCPT ); Mon, 29 May 2023 04:46:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229512AbjE2Iqa (ORCPT ); Mon, 29 May 2023 04:46:30 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBF0DDD; Mon, 29 May 2023 01:46:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4FC86612FB; Mon, 29 May 2023 08:46:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5F10C433A1; Mon, 29 May 2023 08:46:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685349986; bh=wsZuBhQ5SLsEKjZKGXgBhoZNIyJapcFUehPkUlj6EiA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j2S1tXsReEk+M+YezVb88HqexGfDDwSg0jG4Xm7IWz9GJxDQykX8UDJ7RMo335KSu qr1BzG/CdqRJR9HMirXBHJBhW4zp7ByD0iS7liIXdqAwA7+FxMy0PTo2onNXD7Qebr KidQlNlnSc8pkfRlvPoiDV4onrys2BxWA8oVt+9Hdv8upWgGaa14LXPvTXlL3TkoSe 5db7cqNI1XOUQ3Z2lv/lZhb4uYRzGaYafP5RzQ2R9ItJAtkoUF2hnkzUGb1d2Woys1 zxzSap1QgQYjxyPIyDtS0qh9NkvJ1aWJaXv/p5omAvi2GZJsWxgEhcgcc3D7Rs6YeA +Hh72P0ns3l+g== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, bjorn@kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, paul.walmsley@sifive.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH -next V12 1/3] riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK Date: Mon, 29 May 2023 04:45:58 -0400 Message-Id: <20230529084600.2878130-2-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230529084600.2878130-1-guoren@kernel.org> References: <20230529084600.2878130-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guo Ren Add independent irq stacks for percpu to prevent kernel stack overflows. It is also compatible with VMAP_STACK by arch_alloc_vmap_stack. Tested-by: Jisheng Zhang Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Conor Dooley --- arch/riscv/Kconfig | 7 ++++++ arch/riscv/include/asm/irq_stack.h | 32 +++++++++++++++++++++++++ arch/riscv/include/asm/thread_info.h | 2 ++ arch/riscv/kernel/irq.c | 33 ++++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 35 ++++++++++++++++++++++++++-- 5 files changed, 107 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/include/asm/irq_stack.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa256f2e23c1..44b4c9690f94 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -588,6 +588,13 @@ config FPU =20 If you don't know what to do here, say Y. =20 +config IRQ_STACKS + bool "Independent irq stacks" if EXPERT + default y + select HAVE_IRQ_EXIT_ON_IRQ_STACK + help + Add independent irq stacks for percpu to prevent kernel stack overflows. + endmenu # "Platform type" =20 menu "Kernel features" diff --git a/arch/riscv/include/asm/irq_stack.h b/arch/riscv/include/asm/ir= q_stack.h new file mode 100644 index 000000000000..b0dcee9a3fa2 --- /dev/null +++ b/arch/riscv/include/asm/irq_stack.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _ASM_RISCV_IRQ_STACK_H +#define _ASM_RISCV_IRQ_STACK_H + +#include +#include +#include +#include +#include +#include + +DECLARE_PER_CPU(ulong *, irq_stack_ptr); + +#ifdef CONFIG_VMAP_STACK +/* + * To ensure that VMAP'd stack overflow detection works correctly, all VMA= P'd + * stacks need to have the same alignment. + */ +static inline unsigned long *arch_alloc_vmap_stack(size_t stack_size, int = node) +{ + void *p; + + BUILD_BUG_ON(!IS_ENABLED(CONFIG_VMAP_STACK)); + + p =3D __vmalloc_node(stack_size, THREAD_ALIGN, THREADINFO_GFP, node, + __builtin_return_address(0)); + return kasan_reset_tag(p); +} +#endif /* CONFIG_VMAP_STACK */ + +#endif /* _ASM_RISCV_IRQ_STACK_H */ diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 97e6f65ec176..2f32875276b0 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -40,6 +40,8 @@ #define OVERFLOW_STACK_SIZE SZ_4K #define SHADOW_OVERFLOW_STACK_SIZE (1024) =20 +#define IRQ_STACK_SIZE THREAD_SIZE + #ifndef __ASSEMBLY__ =20 extern long shadow_stack[SHADOW_OVERFLOW_STACK_SIZE / sizeof(long)]; diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index eb9a68a539e6..a1dcf8e43b3c 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -28,6 +28,38 @@ struct fwnode_handle *riscv_get_intc_hwnode(void) } EXPORT_SYMBOL_GPL(riscv_get_intc_hwnode); =20 +#ifdef CONFIG_IRQ_STACKS +#include + +DEFINE_PER_CPU(ulong *, irq_stack_ptr); + +#ifdef CONFIG_VMAP_STACK +static void init_irq_stacks(void) +{ + int cpu; + ulong *p; + + for_each_possible_cpu(cpu) { + p =3D arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu)); + per_cpu(irq_stack_ptr, cpu) =3D p; + } +} +#else +/* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned= . */ +DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack); + +static void init_irq_stacks(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + per_cpu(irq_stack_ptr, cpu) =3D per_cpu(irq_stack, cpu); +} +#endif /* CONFIG_VMAP_STACK */ +#else +static void init_irq_stacks(void) {} +#endif /* CONFIG_IRQ_STACKS */ + int arch_show_interrupts(struct seq_file *p, int prec) { show_ipi_stats(p, prec); @@ -36,6 +68,7 @@ int arch_show_interrupts(struct seq_file *p, int prec) =20 void __init init_IRQ(void) { + init_irq_stacks(); irqchip_init(); if (!handle_arch_irq) panic("No interrupt controller found."); diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 24d309c6ab8d..9e0426cfcc60 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -27,6 +27,7 @@ #include #include #include +#include =20 int show_unhandled_signals =3D 1; =20 @@ -327,16 +328,46 @@ asmlinkage __visible noinstr void do_page_fault(struc= t pt_regs *regs) } #endif =20 -asmlinkage __visible noinstr void do_irq(struct pt_regs *regs) +static void noinstr handle_riscv_irq(struct pt_regs *regs) { struct pt_regs *old_regs; - irqentry_state_t state =3D irqentry_enter(regs); =20 irq_enter_rcu(); old_regs =3D set_irq_regs(regs); handle_arch_irq(regs); set_irq_regs(old_regs); irq_exit_rcu(); +} + +asmlinkage void noinstr do_irq(struct pt_regs *regs) +{ + irqentry_state_t state =3D irqentry_enter(regs); +#ifdef CONFIG_IRQ_STACKS + if (on_thread_stack()) { + ulong *sp =3D per_cpu(irq_stack_ptr, smp_processor_id()) + + IRQ_STACK_SIZE/sizeof(ulong); + __asm__ __volatile( + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" ra, (sp) \n" + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" s0, (sp) \n" + "addi s0, sp, 2*"RISCV_SZPTR "\n" + "move sp, %[sp] \n" + "move a0, %[regs] \n" + "call handle_riscv_irq \n" + "addi sp, s0, -2*"RISCV_SZPTR"\n" + REG_L" s0, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + REG_L" ra, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + : + : [sp] "r" (sp), [regs] "r" (regs) + : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "memory"); + } else +#endif + handle_riscv_irq(regs); =20 irqentry_exit(regs, state); } --=20 2.36.1 From nobody Sun Feb 8 02:21:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98B2AC77B7A for ; Mon, 29 May 2023 08:46:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231648AbjE2Iqu (ORCPT ); Mon, 29 May 2023 04:46:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231612AbjE2Iqn (ORCPT ); Mon, 29 May 2023 04:46:43 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B818102; Mon, 29 May 2023 01:46:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 080C6612FB; Mon, 29 May 2023 08:46:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6B7D3C4339B; Mon, 29 May 2023 08:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685349992; bh=jf544nMnrrkzn5ADVC/f/s+6Ap+dr5yU1BPKr7SBhq4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eDjZXxBrOIUdx5H1DZTFEzfLDMa1t+veVdiUgBDWwZqMjzcdlM6Ek5DC0G0nNdl8f ImhvVBzWx96T6OQWkxfzvp/geEkhoMtDCk22mvh0dN6FDDqNvN8GJBIdYdL/qFVLJq 393Y+zXnIvccrtKjACGF45lrJMQMSM4mtU0oNrCwebKX+UikJ5I6VRLnqAZnXLhpgW sWARuJJg8x4JUHgo+5FJyiOeP5K03W+rGilBRq5BpharrxABq4lgfj8GL3b45f7t04 K1+TBOKtVmyWkMKD5AiJ6rHU9f5mmeFV6v8uLUPztEnUJjg7dwdNX26pHycO3Gq/xy ExopRPRK10RPg== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, bjorn@kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, paul.walmsley@sifive.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH -next V12 2/3] riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK Date: Mon, 29 May 2023 04:45:59 -0400 Message-Id: <20230529084600.2878130-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230529084600.2878130-1-guoren@kernel.org> References: <20230529084600.2878130-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guo Ren Add the HAVE_SOFTIRQ_ON_OWN_STACK feature for the IRQ_STACKS config, and the irq and softirq use the same irq_stack of percpu. Tested-by: Jisheng Zhang Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 6 ++++-- arch/riscv/kernel/irq.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 44b4c9690f94..9567bf5fd5ed 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -589,11 +589,13 @@ config FPU If you don't know what to do here, say Y. =20 config IRQ_STACKS - bool "Independent irq stacks" if EXPERT + bool "Independent irq & softirq stacks" if EXPERT default y select HAVE_IRQ_EXIT_ON_IRQ_STACK + select HAVE_SOFTIRQ_ON_OWN_STACK help - Add independent irq stacks for percpu to prevent kernel stack overflows. + Add independent irq & softirq stacks for percpu to prevent kernel stack + overflows. We may save some memory footprint by disabling IRQ_STACKS. =20 endmenu # "Platform type" =20 diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index a1dcf8e43b3c..d0577cc6a081 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include =20 static struct fwnode_handle *(*__get_intc_node)(void); =20 @@ -56,6 +59,38 @@ static void init_irq_stacks(void) per_cpu(irq_stack_ptr, cpu) =3D per_cpu(irq_stack, cpu); } #endif /* CONFIG_VMAP_STACK */ + +#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK +void do_softirq_own_stack(void) +{ +#ifdef CONFIG_IRQ_STACKS + if (on_thread_stack()) { + ulong *sp =3D per_cpu(irq_stack_ptr, smp_processor_id()) + + IRQ_STACK_SIZE/sizeof(ulong); + __asm__ __volatile( + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" ra, (sp) \n" + "addi sp, sp, -"RISCV_SZPTR "\n" + REG_S" s0, (sp) \n" + "addi s0, sp, 2*"RISCV_SZPTR "\n" + "move sp, %[sp] \n" + "call __do_softirq \n" + "addi sp, s0, -2*"RISCV_SZPTR"\n" + REG_L" s0, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + REG_L" ra, (sp) \n" + "addi sp, sp, "RISCV_SZPTR "\n" + : + : [sp] "r" (sp) + : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "memory"); + } else +#endif + __do_softirq(); +} +#endif /* CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK */ + #else static void init_irq_stacks(void) {} #endif /* CONFIG_IRQ_STACKS */ --=20 2.36.1 From nobody Sun Feb 8 02:21:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3B16C77B7A for ; Mon, 29 May 2023 08:46:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231672AbjE2Iq4 (ORCPT ); Mon, 29 May 2023 04:46:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231634AbjE2Iqw (ORCPT ); Mon, 29 May 2023 04:46:52 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A20F110; Mon, 29 May 2023 01:46:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AC7B76142D; Mon, 29 May 2023 08:46:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25966C433D2; Mon, 29 May 2023 08:46:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685349998; bh=pWzn7wo88vvYCHCgitlDzyBp4bmFmsyhuqUhKxMt8uc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=go44EOeN3HCIMumIdRYVxxfdiB8ceIrb1h2GOkJGsvb0XgdX9T8j52X+WA4MaSTGk KCUxijiy+h9l8kehiVFSui4vuFOS581B1I2Rsp8nmclq2iIlsXTPFAha1hZNpn0E40 jSxE3HMZMwQP/iEX9/UDvirq+GHhaaRQ3ZeV1bsr3ZLE3THWrlcCqWozTViAh7c2kL 9WXWCtbPzruxihqEnH183ai0WN3av7oMCXQ3pvtZWzP6/Yvzi2Lpchw3IczTsxj8gB 6F+gnPgNPA+PhXzcYxM48602eZkWqyPCr6HgWKn6WAodNs/RJdQ60HSRIrrLjZwJbu bMNixPzLjFo3g== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, bjorn@kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, andy.chiu@sifive.com, paul.walmsley@sifive.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [PATCH -next V12 3/3] riscv: stack: Add config of thread stack size Date: Mon, 29 May 2023 04:46:00 -0400 Message-Id: <20230529084600.2878130-4-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230529084600.2878130-1-guoren@kernel.org> References: <20230529084600.2878130-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Guo Ren The commit 0cac21b02ba5 ("riscv: use 16KB kernel stack on 64-bit") increases the thread size mandatory, but some scenarios, such as D1 with a small memory footprint, would suffer from that. After independent irq stack support, let's give users a choice to determine their custom stack size. Link: https://lore.kernel.org/linux-riscv/5f6e6c39-b846-4392-b468-02202404d= e28@www.fastmail.com/ Suggested-by: Arnd Bergmann Tested-by: Jisheng Zhang Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/include/asm/thread_info.h | 12 +----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9567bf5fd5ed..e82be82882fd 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -597,6 +597,16 @@ config IRQ_STACKS Add independent irq & softirq stacks for percpu to prevent kernel stack overflows. We may save some memory footprint by disabling IRQ_STACKS. =20 +config THREAD_SIZE_ORDER + int "Kernel stack size (in power-of-two numbers of page size)" if VMAP_ST= ACK && EXPERT + range 0 4 + default 1 if 32BIT && !KASAN + default 3 if 64BIT && KASAN + default 2 + help + Specify the Pages of thread stack size (from 4KB to 64KB), which also + affects irq stack size, which is equal to thread stack size. + endmenu # "Platform type" =20 menu "Kernel features" diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/= thread_info.h index 2f32875276b0..1833beb00489 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -11,18 +11,8 @@ #include #include =20 -#ifdef CONFIG_KASAN -#define KASAN_STACK_ORDER 1 -#else -#define KASAN_STACK_ORDER 0 -#endif - /* thread information allocation */ -#ifdef CONFIG_64BIT -#define THREAD_SIZE_ORDER (2 + KASAN_STACK_ORDER) -#else -#define THREAD_SIZE_ORDER (1 + KASAN_STACK_ORDER) -#endif +#define THREAD_SIZE_ORDER CONFIG_THREAD_SIZE_ORDER #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) =20 /* --=20 2.36.1