From nobody Mon Feb 9 06:31:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3808AC77B7E for ; Sat, 27 May 2023 05:47:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231207AbjE0Frd (ORCPT ); Sat, 27 May 2023 01:47:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231173AbjE0Frb (ORCPT ); Sat, 27 May 2023 01:47:31 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BCAC12A for ; Fri, 26 May 2023 22:47:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A991660EF4 for ; Sat, 27 May 2023 05:47:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 031ECC433D2; Sat, 27 May 2023 05:47:26 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier , Bjorn Helgaas Cc: linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 1/2] genirq/msi, platform-msi: Adjust return value of msi_domain_prepare_irqs() Date: Sat, 27 May 2023 13:46:32 +0800 Message-Id: <20230527054633.704916-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230527054633.704916-1-chenhuacai@loongson.cn> References: <20230527054633.704916-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adjust the return value semanteme of msi_domain_prepare_irqs(), which allows us to modify the input nvec by overriding the msi_domain_ops:: msi_prepare(). This is necessary for the later patch. Before: 0 on success, others on error. After: =3D 0: Success; > 0: The modified nvec; < 0: Error code. Callers are also updated. Signed-off-by: Huacai Chen --- drivers/base/platform-msi.c | 2 +- kernel/irq/msi.c | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c index f37ad34c80ec..e4a517c144e7 100644 --- a/drivers/base/platform-msi.c +++ b/drivers/base/platform-msi.c @@ -298,7 +298,7 @@ __platform_msi_create_device_domain(struct device *dev, =20 platform_msi_set_proxy_dev(&data->arg); err =3D msi_domain_prepare_irqs(domain->parent, dev, nvec, &data->arg); - if (err) + if (err < 0) goto free_domain; =20 return domain; diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index 7a97bcb086bf..d151936aec05 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1058,6 +1058,12 @@ bool msi_match_device_irq_domain(struct device *dev,= unsigned int domid, return ret; } =20 +/* + * Return Val: + * =3D 0: Success; + * > 0: The modified nvec; + * < 0: Error code. + */ int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev, int nvec, msi_alloc_info_t *arg) { @@ -1260,8 +1266,10 @@ static int __msi_domain_alloc_irqs(struct device *de= v, struct irq_domain *domain int i, ret, virq; =20 ret =3D msi_domain_prepare_irqs(domain, dev, ctrl->nirqs, &arg); - if (ret) + if (ret < 0) return ret; + if (ret > 0) + ctrl->nirqs =3D ret; =20 /* * This flag is set by the PCI layer as we need to activate --=20 2.39.1 From nobody Mon Feb 9 06:31:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A6B7C77B7E for ; Sat, 27 May 2023 05:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231250AbjE0Fr6 (ORCPT ); Sat, 27 May 2023 01:47:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231216AbjE0Fr4 (ORCPT ); Sat, 27 May 2023 01:47:56 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15AB2114 for ; Fri, 26 May 2023 22:47:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9E0D560F27 for ; Sat, 27 May 2023 05:47:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57772C433D2; Sat, 27 May 2023 05:47:51 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier , Bjorn Helgaas Cc: linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen , Juxin Gao Subject: [PATCH 2/2] irqchip/loongson-pch-msi: Add machanism to limit msi allocation Date: Sat, 27 May 2023 13:46:33 +0800 Message-Id: <20230527054633.704916-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230527054633.704916-1-chenhuacai@loongson.cn> References: <20230527054633.704916-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Loongson machines can have as many as 256 logical cpus, but the maximum of msi vectors in one irqchip is also 256 (practically that is less than 256, because pch-pic consumes some of them). Even on a 64-core machine, 256 irqs can be easily exhausted if there are several NICs (NICs usually allocate msi irqs depending on the number of online cpus). So we want to limit the msi allocation. In this patch we add a machanism to limit msi allocation: 1, Modify input "nvec" by overriding the msi_domain_ops::msi_prepare(); 2, The default limit is 256, which is compatible with the old behavior; 3, Add a cmdline parameter "loongson_msi_limit=3Dxxx" to control the limit. Signed-off-by: Juxin Gao Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-msi.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-l= oongson-pch-msi.c index 6e1e1f011bb2..85e2e3468b8c 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -85,9 +85,36 @@ static void pch_msi_compose_msi_msg(struct irq_data *dat= a, msg->data =3D data->hwirq; } =20 +#define DEFAULT_MSI_LIMITS 256 + +static int pch_msi_limits =3D DEFAULT_MSI_LIMITS; + +static int __init pch_msi_limit(char *str) +{ + get_option(&str, &pch_msi_limits); + + if (pch_msi_limits <=3D 0) + pch_msi_limits =3D DEFAULT_MSI_LIMITS; + + return 0; +} + +early_param("loongson_msi_limit", pch_msi_limit); + +static int pch_msi_prepare(struct irq_domain *domain, struct device *dev, = int nvec, msi_alloc_info_t *arg) +{ + memset(arg, 0, sizeof(*arg)); + return clamp_val(nvec, 0, pch_msi_limits); +} + +static struct msi_domain_ops pch_msi_ops =3D { + .msi_prepare =3D pch_msi_prepare, +}; + static struct msi_domain_info pch_msi_domain_info =3D { .flags =3D MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, + .ops =3D &pch_msi_ops, .chip =3D &pch_msi_irq_chip, }; =20 --=20 2.39.1