From nobody Mon Feb 9 17:21:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56FDEC7EE2C for ; Fri, 26 May 2023 17:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242343AbjEZRLf (ORCPT ); Fri, 26 May 2023 13:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242472AbjEZRL2 (ORCPT ); Fri, 26 May 2023 13:11:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DA64E53 for ; Fri, 26 May 2023 10:11:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C57CC651BE for ; Fri, 26 May 2023 17:11:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D085CC433EF; Fri, 26 May 2023 17:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121078; bh=Bs4Qhmx5NZ+yKonQ7Rt09UyM8af1mOtvP1M80X6S4jQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q9Y1UXMhi4qK29CeyQI19Humy4yTmrqCpAopNGt1S+1XcaeUKmnORESujrBqXEfd3 qvyiSgkK20sTmXgyHEJccjGyXnZ17e5PF7iLp92CC0yT0Z/JZf7UIbIvqs2eUcTEaF e//NjVYc1BMFIG/OE0/ik7wg3p8J1EIBIQXxrTR967X4dGzAEc5H2hrn8Sj+3pChl5 eF9S4qczAXnpMMxQYG0TdNBYrdEFdNDfMgLkRoSUisfE2yVc9fVNi6CfoPwMQD8SLi i3ZmM+sElibCVv5j5oilGTXSrslQ3Or1mpAVnl8L7S9vaNgFA513T/J2wz7eAGGBBe tcEgUMrGrAGiA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Date: Sat, 27 May 2023 00:59:56 +0800 Message-Id: <20230526165958.908-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will soon take different actions by checking the HW is noncoherent or not, I.E ZICBOM/ERRATA_THEAD_CMO or not. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/thead/errata.c | 19 +++++++++++-------- arch/riscv/include/asm/cacheflush.h | 4 ++-- arch/riscv/kernel/setup.c | 6 +++++- arch/riscv/mm/dma-noncoherent.c | 10 ++++++---- 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index be84b14f0118..c192b80a5166 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage, static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO)) - return false; - - if (arch_id !=3D 0 || impid !=3D 0) - return false; + bool cmo; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return false; =20 + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) && + (arch_id =3D=3D 0 && impid =3D=3D 0)) + cmo =3D true; + else + cmo =3D false; + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { - riscv_cbom_block_size =3D L1_CACHE_BYTES; - riscv_noncoherent_supported(); + if (cmo) + riscv_cbom_block_size =3D L1_CACHE_BYTES; + riscv_noncoherent_supported(cmo); } =20 - return true; + return cmo; } =20 static bool errata_probe_pmu(unsigned int stage, diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index 8091b8bf4883..9d056c9b625a 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size; void riscv_init_cbo_blocksizes(void); =20 #ifdef CONFIG_RISCV_DMA_NONCOHERENT -void riscv_noncoherent_supported(void); +void riscv_noncoherent_supported(bool cmo); #else -static inline void riscv_noncoherent_supported(void) {} +static inline void riscv_noncoherent_supported(bool cmo) {} #endif =20 /* diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..565f3e20169b 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -264,6 +264,7 @@ static void __init parse_dtb(void) =20 void __init setup_arch(char **cmdline_p) { + bool cmo; parse_dtb(); setup_initial_init_mm(_stext, _etext, _edata, _end); =20 @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p) apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) - riscv_noncoherent_supported(); + cmo =3D true; + else + cmo =3D false; + riscv_noncoherent_supported(cmo); } =20 static int __init topology_init(void) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index d51a75864e53..0e172e2b4751 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base= , u64 size, dev->dma_coherent =3D coherent; } =20 -void riscv_noncoherent_supported(void) +void riscv_noncoherent_supported(bool cmo) { - WARN(!riscv_cbom_block_size, - "Non-coherent DMA support enabled without a block size\n"); - noncoherent_supported =3D true; + if (cmo) { + WARN(!riscv_cbom_block_size, + "Non-coherent DMA support enabled without a block size\n"); + noncoherent_supported =3D true; + } } --=20 2.40.1