From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B3CE6C7EE2E for ; Fri, 26 May 2023 17:11:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236220AbjEZRLY (ORCPT ); Fri, 26 May 2023 13:11:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242302AbjEZRLQ (ORCPT ); Fri, 26 May 2023 13:11:16 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 006171B1 for ; Fri, 26 May 2023 10:11:13 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 57227650CE for ; Fri, 26 May 2023 17:11:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 64C85C43446; Fri, 26 May 2023 17:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121072; bh=N+SE5apBHJdpc4kl5LVsR83pASoe466MUuKqmk4qCmY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dy9f79qlz416EP/3kBixmbxtEXL1AKGqFraAcnWqIMmty/VaLIObcEn4i3SO2uOV5 QkhwCRgI/Oay6bicOxByimULBFgUFw4j6xneFP+fsk11XbUZMlDS3mNrTjpUoqqqTz DPwGGmjWeRBgtFzQ9ouzXuhtXZ9Y46W8C6ObVWRrOdxmxoX7UOcfV9J0b5bErkxuxC ppNttvMssdEoz7kRbhRyYN6bZlp+UYB42+BkQAbnz1U92W3qY73ZMyiDf8+iCahGwg LLej5KAh21kHUwffCZrId0f8ZlWjsdXRsPwBaepbd0kjN2eSX6TmWWJEi/Am3Jq5P5 BklHbdj0qYrUw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 1/6] riscv: errata: thead: only set cbom size & noncoherent during boot Date: Sat, 27 May 2023 00:59:53 +0800 Message-Id: <20230526165958.908-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CBOM size and whether the HW is noncoherent is known and determined during booting and won't change after that. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/errata/thead/errata.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index c259dc925ec1..be84b14f0118 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -45,8 +45,11 @@ static bool errata_probe_cmo(unsigned int stage, if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return false; =20 - riscv_cbom_block_size =3D L1_CACHE_BYTES; - riscv_noncoherent_supported(); + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { + riscv_cbom_block_size =3D L1_CACHE_BYTES; + riscv_noncoherent_supported(); + } + return true; } =20 --=20 2.40.1 From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEF79C7EE2C for ; Fri, 26 May 2023 17:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229910AbjEZRL2 (ORCPT ); Fri, 26 May 2023 13:11:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242337AbjEZRLS (ORCPT ); Fri, 26 May 2023 13:11:18 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 926F8E55 for ; Fri, 26 May 2023 10:11:15 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 29AB261648 for ; Fri, 26 May 2023 17:11:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 374DBC433D2; Fri, 26 May 2023 17:11:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121074; bh=xGXWKrOp0g9viGaeP46hlIuMnd4eCZ7qokxGpnJ/fzc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=inb6fwAeTMyK2wSbEr0nuGmmPotGctpAFAas68FOu4FXw2az1r0gk6rZbi+5aV0h5 m4OTi/vkC0xVo5GTCgTkRkG73mXt852HxHcds0NLIr1prkeDvnwR35p44PQEvIl6cy yiSGbH8nOzCslfwRqUU068U0GxfMvlzcryYaJZugLD0oW6QzFdR4E6aOzmTF8JuRDS 2E4BuuxBKV+OGh4lFzfjSK7OfQQmJG6g09pKeZsR9d5KkR2MBKUakQsKttJ8oqYShU j0wk75Exd01x45Uaxs8towiqvb/su72IxbpAqoT33JD5OogB3dtjS4/aCddv+IDty7 ib60VxxrBdFdw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 2/6] riscv: mm: mark CBO relate initialization funcs as __init Date: Sat, 27 May 2023 00:59:54 +0800 Message-Id: <20230526165958.908-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The two functions cbo_get_block_size() and riscv_init_cbo_blocksizes() are only called during booting, mark them as __init. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/mm/cacheflush.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fca532ddf3ec..fbc59b3f69f2 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -104,9 +104,9 @@ EXPORT_SYMBOL_GPL(riscv_cbom_block_size); unsigned int riscv_cboz_block_size; EXPORT_SYMBOL_GPL(riscv_cboz_block_size); =20 -static void cbo_get_block_size(struct device_node *node, - const char *name, u32 *block_size, - unsigned long *first_hartid) +static void __init cbo_get_block_size(struct device_node *node, + const char *name, u32 *block_size, + unsigned long *first_hartid) { unsigned long hartid; u32 val; @@ -126,7 +126,7 @@ static void cbo_get_block_size(struct device_node *node, } } =20 -void riscv_init_cbo_blocksizes(void) +void __init riscv_init_cbo_blocksizes(void) { unsigned long cbom_hartid, cboz_hartid; u32 cbom_block_size =3D 0, cboz_block_size =3D 0; --=20 2.40.1 From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC6D2C77B7A for ; Fri, 26 May 2023 17:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242381AbjEZRLc (ORCPT ); Fri, 26 May 2023 13:11:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242406AbjEZRLY (ORCPT ); Fri, 26 May 2023 13:11:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03B6F1B7 for ; Fri, 26 May 2023 10:11:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F0A276519D for ; Fri, 26 May 2023 17:11:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09AA0C4339B; Fri, 26 May 2023 17:11:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121076; bh=EFBwhFd9h5qljpxdSxEUl1LBAOZbrYHCRzIQKTfr4Eo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqSdc9yjds0qBut4705CgMnspNEGuyhW+e1aoMQmGPboAeGFMDVvjfNAGTjvZCgZv CyuYU9rrIt276VNDMQ4RkYntlG86VMvrqucBi6vr9aM+tc8munbsrRU0TZpnlEXrxc UGbQiDbl21o6r6XyAlFF1w10ARU6M7vWRz3B2aYMqI5DQUtHVw/A/DH9hNaGuGnefq O6dfGs+cFxuthKDzH5KyY70wbvnLgHdK9ilEpFIxbOUNcSZfn3hMsTYojY3Ejmoy6I Y241nSqbxB7/nDNx99+A1sYt/6FtGfU2htL7glI0+OfpQ/GhvsPp02cit4tp7RJgfa 7kyyc8Qnzh61Q== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 3/6] riscv: mm: mark noncoherent_supported as __ro_after_init Date: Sat, 27 May 2023 00:59:55 +0800 Message-Id: <20230526165958.908-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The noncoherent_supported indicates whether the HW is coherent or not, it won't change after booting, mark it as __ro_after_init. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/mm/dma-noncoherent.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index d919efab6eba..d51a75864e53 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -10,7 +10,7 @@ #include #include =20 -static bool noncoherent_supported; +static bool noncoherent_supported __ro_after_init; =20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) --=20 2.40.1 From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56FDEC7EE2C for ; Fri, 26 May 2023 17:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242343AbjEZRLf (ORCPT ); Fri, 26 May 2023 13:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242472AbjEZRL2 (ORCPT ); Fri, 26 May 2023 13:11:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DA64E53 for ; Fri, 26 May 2023 10:11:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C57CC651BE for ; Fri, 26 May 2023 17:11:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D085CC433EF; Fri, 26 May 2023 17:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121078; bh=Bs4Qhmx5NZ+yKonQ7Rt09UyM8af1mOtvP1M80X6S4jQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q9Y1UXMhi4qK29CeyQI19Humy4yTmrqCpAopNGt1S+1XcaeUKmnORESujrBqXEfd3 qvyiSgkK20sTmXgyHEJccjGyXnZ17e5PF7iLp92CC0yT0Z/JZf7UIbIvqs2eUcTEaF e//NjVYc1BMFIG/OE0/ik7wg3p8J1EIBIQXxrTR967X4dGzAEc5H2hrn8Sj+3pChl5 eF9S4qczAXnpMMxQYG0TdNBYrdEFdNDfMgLkRoSUisfE2yVc9fVNi6CfoPwMQD8SLi i3ZmM+sElibCVv5j5oilGTXSrslQ3Or1mpAVnl8L7S9vaNgFA513T/J2wz7eAGGBBe tcEgUMrGrAGiA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 4/6] riscv: mm: pass noncoherent or not to riscv_noncoherent_supported() Date: Sat, 27 May 2023 00:59:56 +0800 Message-Id: <20230526165958.908-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will soon take different actions by checking the HW is noncoherent or not, I.E ZICBOM/ERRATA_THEAD_CMO or not. Signed-off-by: Jisheng Zhang --- arch/riscv/errata/thead/errata.c | 19 +++++++++++-------- arch/riscv/include/asm/cacheflush.h | 4 ++-- arch/riscv/kernel/setup.c | 6 +++++- arch/riscv/mm/dma-noncoherent.c | 10 ++++++---- 4 files changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index be84b14f0118..c192b80a5166 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -36,21 +36,24 @@ static bool errata_probe_pbmt(unsigned int stage, static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, unsigned long impid) { - if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO)) - return false; - - if (arch_id !=3D 0 || impid !=3D 0) - return false; + bool cmo; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return false; =20 + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO) && + (arch_id =3D=3D 0 && impid =3D=3D 0)) + cmo =3D true; + else + cmo =3D false; + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT) { - riscv_cbom_block_size =3D L1_CACHE_BYTES; - riscv_noncoherent_supported(); + if (cmo) + riscv_cbom_block_size =3D L1_CACHE_BYTES; + riscv_noncoherent_supported(cmo); } =20 - return true; + return cmo; } =20 static bool errata_probe_pmu(unsigned int stage, diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index 8091b8bf4883..9d056c9b625a 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -54,9 +54,9 @@ extern unsigned int riscv_cboz_block_size; void riscv_init_cbo_blocksizes(void); =20 #ifdef CONFIG_RISCV_DMA_NONCOHERENT -void riscv_noncoherent_supported(void); +void riscv_noncoherent_supported(bool cmo); #else -static inline void riscv_noncoherent_supported(void) {} +static inline void riscv_noncoherent_supported(bool cmo) {} #endif =20 /* diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..565f3e20169b 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -264,6 +264,7 @@ static void __init parse_dtb(void) =20 void __init setup_arch(char **cmdline_p) { + bool cmo; parse_dtb(); setup_initial_init_mm(_stext, _etext, _edata, _end); =20 @@ -298,7 +299,10 @@ void __init setup_arch(char **cmdline_p) apply_boot_alternatives(); if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) - riscv_noncoherent_supported(); + cmo =3D true; + else + cmo =3D false; + riscv_noncoherent_supported(cmo); } =20 static int __init topology_init(void) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index d51a75864e53..0e172e2b4751 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -72,9 +72,11 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base= , u64 size, dev->dma_coherent =3D coherent; } =20 -void riscv_noncoherent_supported(void) +void riscv_noncoherent_supported(bool cmo) { - WARN(!riscv_cbom_block_size, - "Non-coherent DMA support enabled without a block size\n"); - noncoherent_supported =3D true; + if (cmo) { + WARN(!riscv_cbom_block_size, + "Non-coherent DMA support enabled without a block size\n"); + noncoherent_supported =3D true; + } } --=20 2.40.1 From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 526CAC7EE23 for ; Fri, 26 May 2023 17:11:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242494AbjEZRLk (ORCPT ); Fri, 26 May 2023 13:11:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242402AbjEZRLd (ORCPT ); Fri, 26 May 2023 13:11:33 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26B3CE69 for ; Fri, 26 May 2023 10:11:21 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 946E1651C0 for ; Fri, 26 May 2023 17:11:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A24CEC4339B; Fri, 26 May 2023 17:11:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121080; bh=NqqasUnRMBLReOmJzfWs5pvHZNoT/9CPsg7U+dgQNHM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=r/6CXpeHNUGKQyClLnumeEU4WdVQ0v8ClQth1L1b9KGS6C8PaXWnAEiR3wZEqunEe cGvry/QwoEgYKFwdE6S8D1CGMT2AjnhMLomwpNTHxqHqz7PTBH6FIsdHxo2jmlgqf+ qLP5vdpNAIi+DOzIkcmlS2R4bjuP+MRaxFYqNkx1GEzi0zQevkg4NTpWn6DQ45QHT9 3dLnTe/tGy8xVoyoyrza3W+r6aRDTIEkIC6CmBceFxj6vLrBxT18saM1slxX4wBf4/ t0zQj1LjdVjwjm71EnF8EI7PHZpb2r+/UGueBe7pDY561UJ77DVEJs7DT+aGbhRtgx WSD1FXf35HPGQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 5/6] riscv: allow kmalloc() caches aligned to the smallest value Date: Sat, 27 May 2023 00:59:57 +0800 Message-Id: <20230526165958.908-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=3Dy. To support unified kernel Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus it brings some bad effects to for coherent platforms: Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and kmalloc-8 slab caches don't exist any more, they are replaced with either kmalloc-128 or kmalloc-64. Secondly, larger than necessary kmalloc aligned allocations results in unnecessary cache/TLB pressure. This issue also exists on arm64 platforms. From last year, Catalin tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage in various drivers with ARCH_DMA_MINALIGN etc. One fact we can make use of for riscv: if the CPU doesn't support ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on Catalin's work and above fact, we can easily solve the kmalloc align issue for riscv: we can override dma_get_cache_alignment(), then let it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know the underlying HW neither supports ZICBOM nor supports T-HEAD CMO. So what about if the CPU supports ZICBOM and T-HEAD CMO, but all the devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the kmalloc minimum alignment, nothing changed in this case. This case can be improved in the future. After this patch, a simple test of booting to a small buildroot rootfs on qemu shows: kmalloc-96 5041 5041 96 ... kmalloc-64 9606 9606 64 ... kmalloc-32 5128 5128 32 ... kmalloc-16 7682 7682 16 ... kmalloc-8 10246 10246 8 ... So we save about 1268KB memory. The saving will be much larger in normal OS env on real HW platforms. [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1= -catalin.marinas@arm.com/ Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/cache.h | 14 ++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index d3036df23ccb..2174fe7bac9a 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -13,6 +13,7 @@ =20 #ifdef CONFIG_RISCV_DMA_NONCOHERENT #define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#define ARCH_KMALLOC_MINALIGN (8) #endif =20 /* @@ -23,4 +24,17 @@ #define ARCH_SLAB_MINALIGN 16 #endif =20 +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_RISCV_DMA_NONCOHERENT +extern int dma_cache_alignment; +#define dma_get_cache_alignment dma_get_cache_alignment +static inline int dma_get_cache_alignment(void) +{ + return dma_cache_alignment; +} +#endif + +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_RISCV_CACHE_H */ diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index 0e172e2b4751..21b553c299db 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -11,6 +11,8 @@ #include =20 static bool noncoherent_supported __ro_after_init; +int dma_cache_alignment __ro_after_init =3D ARCH_DMA_MINALIGN; +EXPORT_SYMBOL(dma_cache_alignment); =20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, enum dma_data_direction dir) @@ -78,5 +80,7 @@ void riscv_noncoherent_supported(bool cmo) WARN(!riscv_cbom_block_size, "Non-coherent DMA support enabled without a block size\n"); noncoherent_supported =3D true; + } else { + dma_cache_alignment =3D 1; } } --=20 2.40.1 From nobody Mon Feb 9 05:38:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB9B7C77B7A for ; Fri, 26 May 2023 17:11:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242511AbjEZRLv (ORCPT ); Fri, 26 May 2023 13:11:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242500AbjEZRLk (ORCPT ); Fri, 26 May 2023 13:11:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 462C1E7F for ; Fri, 26 May 2023 10:11:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 65FE661648 for ; Fri, 26 May 2023 17:11:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73D6FC433EF; Fri, 26 May 2023 17:11:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1685121081; bh=Sb+M48Kvrrwe56O2VNb3Wy6c5mOmMps4uXhVYIYGrVA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bNCXjNb4yjDWVmK8nVob+9hyyY8G6hAJF9rkXgE10A1fmr6dPhyHr82KyXokkoJMh vhYiAMlsJ3rYifkJ0MND8EjH8qski6jZNSGf0igixo1rRawZRSqTIMCAjQ2CT9Puva 9XQTDnC0qD1sU1xQtsN9fHq+BwgScWu+AH510ELfxQhyEvuNEH/PfSoKs/CKXEftJD 4Dahcxl81zim9vpr11kdsU6Wcn2yDzsWmbUWvP1nlzU+KniHqHflKWRRPBiOZVdzoc rNsdUj2cRzxWT/HPUhfPbzbFfSIX1tsT0m2qYe6IGpOBWH1FwFTq3cAp99q2kOeYgM CZTuJ2IuA1tSA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Catalin Marinas Subject: [PATCH 6/6] riscv: enable DMA_BOUNCE_UNALIGNED_KMALLOC for !dma_coherent Date: Sat, 27 May 2023 00:59:58 +0800 Message-Id: <20230526165958.908-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230526165958.908-1-jszhang@kernel.org> References: <20230526165958.908-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the DMA bouncing of unaligned kmalloc() buffers now in place, enable it for riscv when RISCV_DMA_NONCOHERENT=3Dy to allow the kmalloc-{8,16,32,96} caches. Since RV32 doesn't enable SWIOTLB yet, and I didn't see any dma noncoherent RV32 platforms in the mainline, so skip RV32 now by only enabling DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB is available. Once we see such requirement on RV32, we can enable it then. NOTE: we didn't force to create the swiotlb buffer even when the end of RAM is within the 32-bit physical address range. That's to say: For RV64 with > 4GB memory, the feature is enabled. For RV64 with <=3D 4GB memory, the feature isn't enabled by default. We rely on users to pass "swiotlb=3Dmmnn,force" where mmnn is the Number of I/O TLB slabs, see kernel-parameters.txt for details. Tested on Sipeed Lichee Pi 4A with 8GB DDR and Sipeed M1S BL808 Dock board. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b958f67f9a12..14f030cd6357 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -260,6 +260,7 @@ config RISCV_DMA_NONCOHERENT select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE select DMA_DIRECT_REMAP + select DMA_BOUNCE_UNALIGNED_KMALLOC if SWIOTLB =20 config AS_HAS_INSN def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$= (comma) zero) --=20 2.40.1