From nobody Mon Feb 9 17:58:23 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96BD4C77B73 for ; Fri, 26 May 2023 15:23:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244096AbjEZPXV (ORCPT ); Fri, 26 May 2023 11:23:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244076AbjEZPXO (ORCPT ); Fri, 26 May 2023 11:23:14 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03553187; Fri, 26 May 2023 08:23:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685114589; x=1716650589; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qrgla/+2XOvTx0c45l7lux957CyaIb6rgNHr3CTEZUM=; b=dhTDAP9/YjQ+PeRmC9tUaBfZfVJh6AHAkss1dDWby8fmBzQOGtjY/MAb /mgdHeDj4VGkZ8V3DaweaM8LRQSqV86WIW/tHbMi9vdREwOojxEa5wITL /3KtN5lThHLJ/sNTjLRY4eWwexNFTD7S3zwg5Hs3X/q4ortTfwgGLD+03 VnsXWPtLppFJOEeGEyih1OLgYsGGvftmhuX69wuM9CkEaoEKO7gzz5YLR OXhMGRXbIKa0GQYda4UH9yi+slXlhPSnAZJBA9ZJgDlTLjXU2lrMJvR6l Wg/yxtBkxSwZUJLwyF1SrP3KCVVycOIcwkp2V/YusrPgHfzqeBaxHCJ/5 A==; X-IronPort-AV: E=Sophos;i="6.00,194,1681196400"; d="scan'208";a="154119493" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 May 2023 08:23:09 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 26 May 2023 08:23:07 -0700 Received: from CHE-LT-I17164LX.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 26 May 2023 08:23:03 -0700 From: Parthiban Veerasooran To: , , , , , , , , , CC: , , , , "Parthiban Veerasooran" Subject: [PATCH net-next v4 5/6] net: phy: microchip_t1s: remove unnecessary interrupts disabling code Date: Fri, 26 May 2023 20:53:47 +0530 Message-ID: <20230526152348.70781-6-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230526152348.70781-1-Parthiban.Veerasooran@microchip.com> References: <20230526152348.70781-1-Parthiban.Veerasooran@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org By default, except Reset Complete interrupt in the Interrupt Mask 2 Register all other interrupts are disabled/masked. As Reset Complete status is already handled, it doesn't make sense to disable it. Reviewed-by: Ram=C3=B3n Nordin Rodriguez Tested-by: Ram=C3=B3n Nordin Rodriguez Reviewed-by: Andrew Lunn Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 0ecef87e5882..bcfcec56a6c7 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -12,8 +12,6 @@ =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 =20 -#define LAN867X_REG_IRQ_1_CTL 0x001C -#define LAN867X_REG_IRQ_2_CTL 0x001D #define LAN867X_REG_STS2 0x0019 =20 #define LAN867x_RESET_COMPLETE_STS BIT(11) @@ -89,17 +87,7 @@ static int lan867x_revb1_config_init(struct phy_device *= phydev) return err; } =20 - /* None of the interrupts in the lan867x phy seem relevant. - * Other phys inspect the link status and call phy_trigger_machine - * in the interrupt handler. - * This phy does not support link status, and thus has no interrupt - * for it either. - * So we'll just disable all interrupts on the chip. - */ - err =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_IRQ_1_CTL, 0xFF= FF); - if (err !=3D 0) - return err; - return phy_write_mmd(phydev, MDIO_MMD_VEND2, LAN867X_REG_IRQ_2_CTL, 0xFFF= F); + return 0; } =20 static int lan867x_read_status(struct phy_device *phydev) --=20 2.34.1