From nobody Sat Dec 14 19:41:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97562C7EE23 for ; Fri, 26 May 2023 10:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243222AbjEZKKC (ORCPT ); Fri, 26 May 2023 06:10:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243302AbjEZKJv (ORCPT ); Fri, 26 May 2023 06:09:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80BCA9E; Fri, 26 May 2023 03:09:49 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34Q7pe3o016141; Fri, 26 May 2023 10:09:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=AKvtVm6MJmk1pLBpig8S6VxmOPROgoFdc6sKOL7sKAQ=; b=JQ2tCr1KsQxLrhmeF+UNub1qw+RlFiRpL+IyqswDHSVpVKFBuAJh6SYJ2CFXeio6VPOA 9eUv3hNxRu0o8wOGvNlJxwz9jY21CRbFX0zxEqggBBptpU8z816YWl/UUnbZD8cc8A6e Viub1JhiNUp4l4JbKm7tbgrulMDskGioC1O6Qwi2stDYvjvhNGaiiUz+oXHDszfWldKU 7s0NtGdoX71Y/dN2Z04hBXdYmpQp9lAhyUwxzrSQue57Jeq4y03ctaCISvhPRLqtruHr Pza3igUaA5hr9oRdnRyYPLa2bRptU9fVNpSm0A+QbUJVCMCGsHVeh5P6L26K59BEI5Eg cA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qtq28geyd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 10:09:34 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34QA8x0V006651 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 10:08:59 GMT Received: from hazha-gv.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 03:08:53 -0700 From: Hao Zhang To: Suzuki K Poulose , Mike Leach , Leo Yan , James Clark , Alexander Shishkin , Mathieu Poirier , Konrad Dybcio , "Rob Herring" , Krzysztof Kozlowski , Andy Gross , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Jonathan Corbet CC: Hao Zhang , Greg Kroah-Hartman , , , , , Tingwei Zhang , Jinlong Mao , Yuanfang Zhang , Tao Zhang , Trilok Soni , , Bjorn Andersson , Subject: [PATCH v5 1/3] Coresight: Add coresight dummy driver Date: Fri, 26 May 2023 18:07:51 +0800 Message-ID: <20230526100753.34581-2-quic_hazha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526100753.34581-1-quic_hazha@quicinc.com> References: <20230526100753.34581-1-quic_hazha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LFvz6PUgpZ9qZ5b8GDMPJYfFFMVkLdKj X-Proofpoint-ORIG-GUID: LFvz6PUgpZ9qZ5b8GDMPJYfFFMVkLdKj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_01,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260088 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Coresight devices that kernel don't have permission to access or configure. For these devices, a dummy driver is needed to register them as Coresight devices. The module may also be used to define components that may not have any programming interfaces (e.g, static links), so that paths can = be created in the driver. It provides Coresight API for operations on dummy devices, such as enabling and disabling them. It also provides the Coresight dummy sink/source paths for debugging. Signed-off-by: Hao Zhang --- drivers/hwtracing/coresight/Kconfig | 11 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-dummy.c | 163 ++++++++++++++++++ include/linux/coresight.h | 1 + 4 files changed, 176 insertions(+) create mode 100644 drivers/hwtracing/coresight/coresight-dummy.c diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index 2b5bbfffbc4f..06f0a7594169 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -236,4 +236,15 @@ config CORESIGHT_TPDA =20 To compile this driver as a module, choose M here: the module will be called coresight-tpda. + +config CORESIGHT_DUMMY + tristate "Dummy driver support" + help + Enables support for dummy driver. Dummy driver can be used for + CoreSight sources/sinks that are owned and configured by some + other subsystem and use Linux drivers to configure rest of trace + path. + + To compile this driver as a module, choose M here: the module will be + called coresight-dummy. endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 33bcc3f7b8ae..995d3b2c76df 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_CORESIGHT_TPDA) +=3D coresight-tpda.o coresight-cti-y :=3D coresight-cti-core.o coresight-cti-platform.o \ coresight-cti-sysfs.o obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o +obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o diff --git a/drivers/hwtracing/coresight/coresight-dummy.c b/drivers/hwtrac= ing/coresight/coresight-dummy.c new file mode 100644 index 000000000000..42125b7a0f39 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-dummy.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +struct dummy_drvdata { + struct device *dev; + struct coresight_device *csdev; +}; + +DEFINE_CORESIGHT_DEVLIST(source_devs, "dummy_source"); +DEFINE_CORESIGHT_DEVLIST(sink_devs, "dummy_sink"); + +static int dummy_source_enable(struct coresight_device *csdev, + struct perf_event *event, u32 mode) +{ + dev_dbg(csdev->dev.parent, "Dummy source enabled\n"); + + return 0; +} + +static void dummy_source_disable(struct coresight_device *csdev, + struct perf_event *event) +{ + dev_dbg(csdev->dev.parent, "Dummy source disabled\n"); +} + +static int dummy_sink_enable(struct coresight_device *csdev, u32 mode, + void *data) +{ + dev_dbg(csdev->dev.parent, "Dummy sink enabled\n"); + + return 0; +} + +static int dummy_sink_disable(struct coresight_device *csdev) +{ + dev_dbg(csdev->dev.parent, "Dummy sink disabled\n"); + + return 0; +} + +static const struct coresight_ops_source dummy_source_ops =3D { + .enable =3D dummy_source_enable, + .disable =3D dummy_source_disable, +}; + +static const struct coresight_ops dummy_source_cs_ops =3D { + .source_ops =3D &dummy_source_ops, +}; + +static const struct coresight_ops_sink dummy_sink_ops =3D { + .enable =3D dummy_sink_enable, + .disable =3D dummy_sink_disable, +}; + +static const struct coresight_ops dummy_sink_cs_ops =3D { + .sink_ops =3D &dummy_sink_ops, +}; + +static int dummy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + struct coresight_platform_data *pdata; + struct dummy_drvdata *drvdata; + struct coresight_desc desc =3D { 0 }; + + if (of_device_is_compatible(node, "arm,coresight-dummy-source")) { + + desc.name =3D coresight_alloc_device_name(&source_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_SOURCE; + desc.subtype.source_subtype =3D + CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS; + desc.ops =3D &dummy_source_cs_ops; + } else if (of_device_is_compatible(node, "arm,coresight-dummy-sink")) { + desc.name =3D coresight_alloc_device_name(&sink_devs, dev); + if (!desc.name) + return -ENOMEM; + + desc.type =3D CORESIGHT_DEV_TYPE_SINK; + desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_DUMMY; + desc.ops =3D &dummy_sink_cs_ops; + } else { + dev_err(dev, "Device type not set\n"); + return -EINVAL; + } + + pdata =3D coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + pdev->dev.platform_data =3D pdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + desc.pdata =3D pdev->dev.platform_data; + desc.dev =3D &pdev->dev; + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + pm_runtime_enable(dev); + dev_dbg(dev, "Dummy device initialized\n"); + + return 0; +} + +static int dummy_remove(struct platform_device *pdev) +{ + struct dummy_drvdata *drvdata =3D platform_get_drvdata(pdev); + struct device *dev =3D &pdev->dev; + + pm_runtime_disable(dev); + coresight_unregister(drvdata->csdev); + return 0; +} + +static const struct of_device_id dummy_match[] =3D { + {.compatible =3D "arm,coresight-dummy-source"}, + {.compatible =3D "arm,coresight-dummy-sink"}, + {}, +}; + +static struct platform_driver dummy_driver =3D { + .probe =3D dummy_probe, + .remove =3D dummy_remove, + .driver =3D { + .name =3D "coresight-dummy", + .of_match_table =3D dummy_match, + }, +}; + +static int __init dummy_init(void) +{ + return platform_driver_register(&dummy_driver); +} +module_init(dummy_init); + +static void __exit dummy_exit(void) +{ + platform_driver_unregister(&dummy_driver); +} +module_exit(dummy_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("CoreSight dummy driver"); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index f19a47b9bb5a..6db4b49751cf 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -45,6 +45,7 @@ enum coresight_dev_type { }; =20 enum coresight_dev_subtype_sink { + CORESIGHT_DEV_SUBTYPE_SINK_DUMMY, CORESIGHT_DEV_SUBTYPE_SINK_PORT, CORESIGHT_DEV_SUBTYPE_SINK_BUFFER, CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM, --=20 2.17.1 From nobody Sat Dec 14 19:41:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62FBBC77B7C for ; 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charset="utf-8" This patch add support for Coresight dummy source and dummy sink trace. Signed-off-by: Hao Zhang --- .../arm/arm,coresight-dummy-sink.yaml | 73 +++++++++++++++++++ .../arm/arm,coresight-dummy-source.yaml | 71 ++++++++++++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dum= my-sink.yaml create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dum= my-source.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink= .yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml new file mode 100644 index 000000000000..cb78cfa56702 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Dummy sink component + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a parti= cular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flo= ws + through the intermediate links connecting the source to the currently se= lected + sink. + + The Coresight dummy sink component is for the specific coresight sink de= vices + kernel don't have permission to access or configure, e.g., CoreSight EUD= on + Qualcomm platforms. It is a mini-USB hub implemented to support the USB-= based + debug and trace capabilities. For this device, a dummy driver is needed = to + register it as Coresight sink device in kernel side, so that path can be + created in the driver. Then the trace flow would be transferred to EUD v= ia + coresight link of AP processor. It provides Coresight API for operations= on + dummy source devices, such as enabling and disabling them. It also provi= des + the Coresight dummy source paths for debugging. + + The primary use case of the coresight dummy sink is to build path in ker= nel + side for dummy sink component. + +maintainers: + - Mike Leach + - Suzuki K Poulose + - James Clark + - Mao Jinlong + - Hao Zhang + +properties: + compatible: + enum: + - arm,coresight-dummy-sink + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Input connection from the Coresight Trace bus to + dummy sink, such as Embedded USB debugger(EUD). + + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - in-ports + +additionalProperties: false + +examples: + # Minimum dummy sink definition. Dummy sink connect to coresight replica= tor. + - | + sink { + compatible =3D "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in_replicator_swao: endpoint { + remote-endpoint =3D <&replicator_swao_out_eud>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sour= ce.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.= yaml new file mode 100644 index 000000000000..5fedaed49a1f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Dummy source component + +description: | + CoreSight components are compliant with the ARM CoreSight architecture + specification and can be connected in various topologies to suit a parti= cular + SoCs tracing needs. These trace components can generally be classified as + sinks, links and sources. Trace data produced by one or more sources flo= ws + through the intermediate links connecting the source to the currently se= lected + sink. + + The Coresight dummy source component is for the specific coresight source + devices kernel don't have permission to access or configure. For some SO= Cs, + there would be Coresight source trace components on sub-processor which + are conneted to AP processor via debug bus. For these devices, a dummy d= river + is needed to register them as Coresight source devices, so that paths ca= n be + created in the driver. It provides Coresight API for operations on dummy + source devices, such as enabling and disabling them. It also provides the + Coresight dummy source paths for debugging. + + The primary use case of the coresight dummy source is to build path in k= ernel + side for dummy source component. + +maintainers: + - Mike Leach + - Suzuki K Poulose + - James Clark + - Mao Jinlong + - Hao Zhang + +properties: + compatible: + enum: + - arm,coresight-dummy-source + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port: + description: Output connection from the source to Coresight + Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - out-ports + +additionalProperties: false + +examples: + # Minimum dummy source definition. Dummy source connect to coresight fun= nel. + - | + source { + compatible =3D "arm,coresight-dummy-source"; + + out-ports { + port { + dummy_riscv_out_funnel_swao: endpoint { + remote-endpoint =3D <&funnel_swao_in_dummy_riscv>; + }; + }; + }; + }; + +... --=20 2.17.1 From nobody Sat Dec 14 19:41:29 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF9FC7EE43 for ; Fri, 26 May 2023 10:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243274AbjEZKJx (ORCPT ); Fri, 26 May 2023 06:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243223AbjEZKJo (ORCPT ); Fri, 26 May 2023 06:09:44 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585B5E7; Fri, 26 May 2023 03:09:42 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34Q9c4L3002992; Fri, 26 May 2023 10:09:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=927t+Jc3BbVATY+uT8tywu3mTWnUFfdwEVcCWZY9YDk=; b=WA2UKZgAnSUcjgtf88laz+SxYLmgl4Ziu4QMmrgPsctbnlpR34PhW9kY/qeSBrfCfIJt 79YZRfcFSnGa5uhtFwQxqOKdg7PTMPtly4+G3RyUDyxkBB9xauMNppEZ9ttv7B3W8F8b OjAKRtkoC87lqlvu5oIkEQHxZApJQsCAa7Ld+qIniZ7CXfqZU69PdstlkKO6AAYeETai XZjlkNjK8XdGJg8zeGLj81vuF1gugNZRaR6EBKatmPFJMlepE+cEsi3AaxEGbQZzG+86 +rywbzuNtegLtH9K+uSKAmFk7sd534NSJFKdi9VOXxhLKInXYQbauPrtyIr5sqRBAnyU DA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qt27n35br-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 10:09:28 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34QA9ITk001304 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 10:09:18 GMT Received: from hazha-gv.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 03:09:12 -0700 From: Hao Zhang To: Suzuki K Poulose , Mike Leach , Leo Yan , James Clark , Alexander Shishkin , Mathieu Poirier , Konrad Dybcio , "Rob Herring" , Krzysztof Kozlowski , Andy Gross , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Jonathan Corbet CC: Hao Zhang , Greg Kroah-Hartman , , , , , Tingwei Zhang , Jinlong Mao , Yuanfang Zhang , Tao Zhang , Trilok Soni , , Bjorn Andersson , Subject: [PATCH v5 3/3] Documentation: trace: Add documentation for Coresight Dummy Trace Date: Fri, 26 May 2023 18:07:53 +0800 Message-ID: <20230526100753.34581-4-quic_hazha@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526100753.34581-1-quic_hazha@quicinc.com> References: <20230526100753.34581-1-quic_hazha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: BIKqSiad5Hb8lLy5TtcQ7omTW-4K6x1i X-Proofpoint-GUID: BIKqSiad5Hb8lLy5TtcQ7omTW-4K6x1i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_01,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxlogscore=959 adultscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 mlxscore=0 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260088 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation for Coresight Dummy Trace under trace/coresight. Signed-off-by: Hao Zhang Reviewed-by: Bagas Sanjaya --- .../trace/coresight/coresight-dummy.rst | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-dummy.rst diff --git a/Documentation/trace/coresight/coresight-dummy.rst b/Documentat= ion/trace/coresight/coresight-dummy.rst new file mode 100644 index 000000000000..f0a92669288b --- /dev/null +++ b/Documentation/trace/coresight/coresight-dummy.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +Coresight Dummy Trace Module +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + + :Author: Hao Zhang + :Date: May 2023 + +Introduction +------------ + +The Coresight dummy trace module is for the specific devices that kernel d= on't +have permission to access or configure, e.g., CoreSight TPDMs on Qualcomm +platforms. For these devices, a dummy driver is needed to register them as +Coresight devices. The module may also be used to define components that m= ay +not have any programming interfaces (e.g, static links), so that paths can= be +created in the driver. It provides Coresight API for operations on dummy +devices, such as enabling and disabling them. It also provides the Coresig= ht +dummy sink/source paths for debugging. + +Config details +-------------- + +There are two types of nodes, dummy sink and dummy source. These nodes +are available at ``/sys/bus/coresight/devices``. + +Example output:: + + $ ls -l /sys/bus/coresight/devices | grep dummy + dummy_sink0 -> ../../../devices/platform/soc@0/soc@0:sink/dummy_sink0 + dummy_source0 -> ../../../devices/platform/soc@0/soc@0:source/dummy_so= urce0 --=20 2.17.1