From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F081C77B7E for ; Fri, 26 May 2023 03:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241012AbjEZDGW (ORCPT ); Thu, 25 May 2023 23:06:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235650AbjEZDGP (ORCPT ); Thu, 25 May 2023 23:06:15 -0400 Received: from mail-io1-xd34.google.com (mail-io1-xd34.google.com [IPv6:2607:f8b0:4864:20::d34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E32C2BB; Thu, 25 May 2023 20:06:09 -0700 (PDT) Received: by mail-io1-xd34.google.com with SMTP id ca18e2360f4ac-76c64ddee11so9265539f.2; Thu, 25 May 2023 20:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685070369; x=1687662369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8gw0CRtIoRWw5+nsdaAXlUMcoZo2DLr2IRepPmh2VeQ=; b=NtRKOR/Me1Z5FnrSxi9vVagn5h3wQ3ZwbKKrljr40C7z4CF+3YPD+NQq1HUvwXknEW 4TKzqYVfx9OvCf3ePAcvMWcQEHUodJQp4v+eZj40MwBqU2TwqvWWp1MgOy+TOH3+cgqH Y17fkWmNzB3WLZ1UEfc5CvZfajlHavZjoUEe7WukX7UEqKYOQy7OpJq+up486fGO5PDx J66OGfGqbBqj/S6YA6riqo1pMJIs+IGD8vmBcc54uzYQvSc8zf+0XlGP9q598L5t4kgB aX0UEYB34hNqmgsll1qnKMfMnx6lJzIvMasIjrwqnzxwSlXsNrAuQVLjmr/HsRTX89KA XjNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685070369; x=1687662369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gw0CRtIoRWw5+nsdaAXlUMcoZo2DLr2IRepPmh2VeQ=; b=JEgXgzaJ+UIFTXJkIsVuvLgccct8u66wZIEytcrsif0Mx49bODOf1cUJkl1XJs3EF1 SRxpt4MuKlZmFHY9mL02yLR/kceHHKDZehcZK6VLNP2gVGS40DXnTRddCL2uNxgNrS+o MmZ286vX8KVQ3fYYWZZqxWwErNSzM+E4MW/Y8VUn7gm1G64x4b/wUNHsm6zDHZAtcYVq hOvi1k/NPtAtFgwyIkIti2/iV3pKtZvGnkhMuvvseuoa3Z280oi65ES+lkuszNE9vqw/ ON3zcrYEf95t6xD2azzT0pX8P5r4hxFKavckkNosA1GPU2vZcqQs0ytAMrfLAV8aUJ2Y nY6Q== X-Gm-Message-State: AC+VfDxH6baJBzuanuL2yYyd1ZNbPEHGuljH1RgEQvW1XMM3ibzLdbmq 1Qpwl87bf1xn+W5N+lFBI8Y= X-Google-Smtp-Source: ACHHUZ6GkELdVgPi053XuuJ2+kQeNR6sc1xeRmEfacaJ7/znjChK/RBvWLTh4C2qQYai5DtGyl+vqg== X-Received: by 2002:a6b:f212:0:b0:76c:2759:5cbe with SMTP id q18-20020a6bf212000000b0076c27595cbemr117920ioh.4.1685070369117; Thu, 25 May 2023 20:06:09 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:3dd9:3f6c:9922:6420]) by smtp.gmail.com with ESMTPSA id i2-20020a5e8502000000b007702f55116fsm363189ioj.38.2023.05.25.20.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 20:06:08 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Inki Dae , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 1/7] drm: bridge: samsung-dsim: fix blanking packet size calculation Date: Thu, 25 May 2023 22:05:53 -0500 Message-Id: <20230526030559.326566-2-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lucas Stach Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 0f3f6846beea..a2d1eaf0ed1c 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -881,17 +881,29 @@ static void samsung_dsim_set_display_mode(struct sams= ung_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; + int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; + int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + + /* remove packet overhead when possible */ + hfp =3D max(hfp - 6, 0); + hbp =3D max(hbp - 6, 0); + hsa =3D max(hsa - 6, 0); + + dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", + hfp, hbp, hsa); + reg =3D DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); =20 - reg =3D DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg =3D DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); =20 reg =3D DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA(hsa); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg =3D DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B3F5C7EE29 for ; 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Thu, 25 May 2023 20:06:11 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:3dd9:3f6c:9922:6420]) by smtp.gmail.com with ESMTPSA id i2-20020a5e8502000000b007702f55116fsm363189ioj.38.2023.05.25.20.06.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 20:06:10 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Inki Dae , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 2/7] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Date: Thu, 25 May 2023 22:05:54 -0500 Message-Id: <20230526030559.326566-3-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano suppo= rt") Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index a2d1eaf0ed1c..ead922c3ce9f 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -407,6 +407,9 @@ static const struct samsung_dsim_driver_data exynos3_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data =3D { @@ -420,6 +423,9 @@ static const struct samsung_dsim_driver_data exynos4_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data =3D { @@ -431,6 +437,9 @@ static const struct samsung_dsim_driver_data exynos5_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = =3D { @@ -443,6 +452,9 @@ static const struct samsung_dsim_driver_data exynos5433= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5433_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = =3D { @@ -455,6 +467,9 @@ static const struct samsung_dsim_driver_data exynos5422= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5422_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data =3D { @@ -471,6 +486,9 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { */ .pll_p_offset =3D 14, .reg_values =3D imx8mm_dsim_reg_values, + .m_min =3D 64, + .m_max =3D 1023, + .min_freq =3D 1050, }; =20 static const struct samsung_dsim_driver_data * @@ -549,12 +567,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct= samsung_dsim *dsi, tmp =3D (u64)fout * (_p << _s); do_div(tmp, fin); _m =3D tmp; - if (_m < 41 || _m > 125) + if (_m < driver_data->m_min || _m > driver_data->m_max) continue; =20 tmp =3D (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < driver_data->min_freq * MHZ || tmp > driver_data->max_freq * MHZ) continue; =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index 6a37d1e079bf..2c20b9460c9a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -54,11 +54,14 @@ struct samsung_dsim_driver_data { unsigned int has_freqband:1; unsigned int has_clklane_stop:1; unsigned int num_clks; + unsigned int min_freq; unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + u16 m_min; + u16 m_max; }; =20 struct samsung_dsim_host_ops { --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC2CAC77B7E for ; Fri, 26 May 2023 03:06:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240779AbjEZDGk (ORCPT ); Thu, 25 May 2023 23:06:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236000AbjEZDGS (ORCPT ); Thu, 25 May 2023 23:06:18 -0400 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5B16EE; Thu, 25 May 2023 20:06:13 -0700 (PDT) Received: by mail-io1-xd2f.google.com with SMTP id ca18e2360f4ac-775ebe161c5so36749139f.1; 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charset="utf-8" Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Since it can be optional, change the message from an error to dev_info. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index ead922c3ce9f..307f1c20cfb9 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1719,11 +1719,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_= ops =3D { }; =20 static int samsung_dsim_of_read_u32(const struct device_node *np, - const char *propname, u32 *out_value) + const char *propname, u32 *out_value, bool optional) { int ret =3D of_property_read_u32(np, propname, out_value); =20 - if (ret < 0) + if (ret < 0 && !optional) pr_err("%pOF: failed to get '%s' property\n", np, propname); =20 return ret; @@ -1736,19 +1736,27 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) u32 lane_polarities[5] =3D { 0 }; struct device_node *endpoint; int i, nr_lanes, ret; + struct clk *pll_clk; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", - &dsi->pll_clk_rate); - if (ret < 0) - return ret; + &dsi->pll_clk_rate, 1); + /* If it doesn't exist, read it from the clock instead of failing */ + if (ret < 0) { + dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); + pll_clk =3D devm_clk_get(dev, "sclk_mipi"); + if (!IS_ERR(pll_clk)) + dsi->pll_clk_rate =3D clk_get_rate(pll_clk); + else + return PTR_ERR(pll_clk); + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate); + &dsi->burst_clk_rate, 0); if (ret < 0) return ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", - &dsi->esc_clk_rate); + &dsi->esc_clk_rate, 0); if (ret < 0) return ret; =20 --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DF94C77B7E for ; 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Thu, 25 May 2023 20:06:15 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:3dd9:3f6c:9922:6420]) by smtp.gmail.com with ESMTPSA id i2-20020a5e8502000000b007702f55116fsm363189ioj.38.2023.05.25.20.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 20:06:14 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Frieder Schrempf , Chen-Yu Tsai , Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 4/7] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY Date: Thu, 25 May 2023 22:05:56 -0500 Message-Id: <20230526030559.326566-5-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support variable DPHY timings, it's necessary to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config can be used to determine the nominal values for a given resolution and refresh rate. Signed-off-by: Adam Ford Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/bridge/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f076a09afac0..82c68b042444 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -227,6 +227,7 @@ config DRM_SAMSUNG_DSIM select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY help The Samsung MIPI DSIM bridge controller driver. This MIPI DSIM bridge can be found it on Exynos SoCs and --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38CB5C7EE29 for ; Fri, 26 May 2023 03:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234388AbjEZDGp (ORCPT ); Thu, 25 May 2023 23:06:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240695AbjEZDGU (ORCPT ); Thu, 25 May 2023 23:06:20 -0400 Received: from mail-io1-xd30.google.com (mail-io1-xd30.google.com [IPv6:2607:f8b0:4864:20::d30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9C89BB; Thu, 25 May 2023 20:06:17 -0700 (PDT) Received: by mail-io1-xd30.google.com with SMTP id ca18e2360f4ac-77480507360so10014039f.3; Thu, 25 May 2023 20:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1685070377; x=1687662377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iOxHSlFkyb4mwah+dyNQcB4nfGc3lfT3QYX6cJG7ar4=; b=RgTVQrqsqAkkyPqG7wSBAaksSR/tRYcC5r5KOJz3opH6M1G7Ut3Pigop7ABGikNFoG yreUKt1kXcS94DtjgqVj4laiXxCr3UzgGMNvvZK/Kvil7BPjNXpiGDTKNXvh99uMBra7 8WkB00JFZ8FewLZRjflAnUz0TfwWt2H7frtd39gsb6mW+FsoaAtEYXouh7ERLxU3OZDv KHncPCcr1ozUXo52hQpkZyhQOq5oQHJJEq9iLyWCCj74niF0RrEvo6Y5W0XsZa+qyvhZ lN10LL8OSekC5ZtYAX+PYYVxMr1zZdXpvUXFJ2F18HGsjZGSDF8XReiq7uUIL19HIKWl vqjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685070377; x=1687662377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iOxHSlFkyb4mwah+dyNQcB4nfGc3lfT3QYX6cJG7ar4=; b=YgSUtK7C4yJykzsVmJqeL6LWiq1QCA1RCIkFGECK5SAxKTRl5C1MMT1IwEtVm8LTyO 21vWG5SUHFmiuld5i/RvTDIGXCk7njavnQ0VSbohnUaTPJrN4XIzB7ruBlicVshTTTKT lt14jh/1P32v9csJ6v6Y1gbc3uRibrUdFVRwO0idTFR+AETrZg3fTdarUTJCKDMR+STL +j2ET/sCr+auMn/NB2jfVPTRPGMLoMy57hJMpxWFXZqRk1gDuWeyQSpcLfvp2/30OB6H oOzTXtezYRFivMIipDOvv5tRSIW2FaYMuBxwK2gKzRsoR+H+Dcdrh3buzUyWZ3uBfsPP ELQw== X-Gm-Message-State: AC+VfDxYy6G4WKkDmADDDvWfFGLFdCasPqaSYfFzMSJqGJyJv7XQUsAR fPoS5lGISHqfsiIywN4x6NY= X-Google-Smtp-Source: ACHHUZ7W12qiZWPP5+wNKW3hAJIEv7+NyBUAX5t6V+myy39GQrL7duYXFMxnIYsYmeVXxNu7CkwuNg== X-Received: by 2002:a6b:7b02:0:b0:76c:5513:8b00 with SMTP id l2-20020a6b7b02000000b0076c55138b00mr23791iop.21.1685070377124; Thu, 25 May 2023 20:06:17 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:3dd9:3f6c:9922:6420]) by smtp.gmail.com with ESMTPSA id i2-20020a5e8502000000b007702f55116fsm363189ioj.38.2023.05.25.20.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 20:06:16 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Michael Walle , Marek Szyprowski , Jagan Teki , Inki Dae , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 5/7] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Date: Thu, 25 May 2023 22:05:57 -0500 Message-Id: <20230526030559.326566-6-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Michael Walle Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 58 +++++++++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 307f1c20cfb9..41f557fee29a 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -220,6 +220,8 @@ =20 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" =20 +#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000= 000000ULL) + static const char *const clk_names[5] =3D { "bus_clk", "sclk_mipi", @@ -658,6 +660,8 @@ static unsigned long samsung_dsim_set_pll(struct samsun= g_dsim *dsi, reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) =3D=3D 0); =20 + dsi->hs_clock =3D fout; + return fout; } =20 @@ -705,13 +709,47 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; const unsigned int *reg_values =3D driver_data->reg_values; u32 reg; + struct phy_configure_opts_mipi_dphy cfg; + int clk_prepare, lpx, clk_zero, clk_post, clk_trail; + int hs_exit, hs_prepare, hs_zero, hs_trail; + unsigned long long byte_clock =3D dsi->hs_clock / 8; =20 if (driver_data->has_freqband) return; =20 + phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, + dsi->lanes, &cfg); + + /* + * TODO: + * The tech Applications Processor manuals for i.MX8M Mini, Nano, + * and Plus don't state what the definition of the PHYTIMING + * bits are beyond their address and bit position. + * After reviewing NXP's downstream code, it appears + * that the various PHYTIMING registers take the number + * of cycles and use various dividers on them. This + * calculation does not result in an exact match to the + * downstream code, but it is very close to the values + * generated by their lookup table, and it appears + * to sync at a variety of resolutions. If someone + * can get a more accurate mathematical equation needed + * for these registers, this should be updated. + */ + + lpx =3D PS_TO_CYCLE(cfg.lpx, byte_clock); + hs_exit =3D PS_TO_CYCLE(cfg.hs_exit, byte_clock); + clk_prepare =3D PS_TO_CYCLE(cfg.clk_prepare, byte_clock); + clk_zero =3D PS_TO_CYCLE(cfg.clk_zero, byte_clock); + clk_post =3D PS_TO_CYCLE(cfg.clk_post, byte_clock); + clk_trail =3D PS_TO_CYCLE(cfg.clk_trail, byte_clock); + hs_prepare =3D PS_TO_CYCLE(cfg.hs_prepare, byte_clock); + hs_zero =3D PS_TO_CYCLE(cfg.hs_zero, byte_clock); + hs_trail =3D PS_TO_CYCLE(cfg.hs_trail, byte_clock); + /* B D-PHY: D-PHY Master & Slave Analog Block control */ reg =3D reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | reg_values[PHYCTRL_SLEW_UP]; + samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); =20 /* @@ -719,7 +757,9 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_ds= im *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg =3D reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + + reg =3D DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); + samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); =20 /* @@ -735,10 +775,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; + + reg =3D DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | + DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | + DSIM_PHYTIMING1_CLK_POST(clk_post) | + DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); =20 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); =20 @@ -751,8 +792,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_d= sim *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + + reg =3D DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | + DSIM_PHYTIMING2_HS_ZERO(hs_zero) | + DSIM_PHYTIMING2_HS_TRAIL(hs_trail); + samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); } =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index 2c20b9460c9a..05100e91ecb9 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -93,6 +93,7 @@ struct samsung_dsim { =20 u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags; --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04DF5C77B7C for ; Fri, 26 May 2023 03:07:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241849AbjEZDHF (ORCPT ); Thu, 25 May 2023 23:07:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240830AbjEZDGV (ORCPT ); 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Thu, 25 May 2023 20:06:18 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Inki Dae , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marek Vasut , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 6/7] drm: bridge: samsung-dsim: Support non-burst mode Date: Thu, 25 May 2023 22:05:58 -0500 Message-Id: <20230526030559.326566-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 41f557fee29a..99ce2690582b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -667,11 +667,21 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, =20 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk =3D m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk =3D samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->la= nes)); =20 - hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -943,7 +953,7 @@ static void samsung_dsim_set_display_mode(struct samsun= g_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz =3D dsi->hs_clock / 1000 / 8; int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1794,10 +1804,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) return PTR_ERR(pll_clk); } =20 + /* If it doesn't exist, use pixel clock instead of failing */ ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate =3D 0; + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); --=20 2.39.2 From nobody Tue Dec 16 16:38:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 462F8C77B7C for ; Fri, 26 May 2023 03:07:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241424AbjEZDHQ (ORCPT ); Thu, 25 May 2023 23:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231691AbjEZDGi (ORCPT ); Thu, 25 May 2023 23:06:38 -0400 Received: from mail-io1-xd36.google.com (mail-io1-xd36.google.com [IPv6:2607:f8b0:4864:20::d36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE27918D; 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Thu, 25 May 2023 20:06:20 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frieder Schrempf , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V8 7/7] dt-bindings: bridge: samsung-dsim: Make some flags optional Date: Thu, 25 May 2023 22:05:59 -0500 Message-Id: <20230526030559.326566-8-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230526030559.326566-1-aford173@gmail.com> References: <20230526030559.326566-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the event a device is connected to the samsung-dsim controller that doesn't support the burst-clock, the driver is able to get the requested pixel clock from the attached device or bridge. In these instances, the samsung,burst-clock-frequency isn't needed, so remove it from the required list. The pll-clock frequency can be set by the device tree entry for samsung,pll-clock-frequency, but in some cases, the pll-clock may have the same clock rate as sclk_mipi clock. If they are equal, this flag is not needed since the driver will use the sclk_mipi rate as a fallback. Signed-off-by: Adam Ford Reviewed-by: Conor Dooley --- .../bindings/display/bridge/samsung,mipi-dsim.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-= dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-d= sim.yaml index 9f61ebdfefa8..360fea81f4b6 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.ya= ml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.ya= ml @@ -70,7 +70,9 @@ properties: samsung,burst-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: - DSIM high speed burst mode frequency. + DSIM high speed burst mode frequency when connected to devices + that support burst mode. If absent, the driver will use the pixel + clock from the attached device or bridge. =20 samsung,esc-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 @@ -80,7 +82,8 @@ properties: samsung,pll-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: - DSIM oscillator clock frequency. + DSIM oscillator clock frequency. If absent, the driver will + use the clock frequency of sclk_mipi. =20 phys: maxItems: 1 @@ -134,9 +137,7 @@ required: - compatible - interrupts - reg - - samsung,burst-clock-frequency - samsung,esc-clock-frequency - - samsung,pll-clock-frequency =20 allOf: - $ref: ../dsi-controller.yaml# --=20 2.39.2