From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0C4AC7EE29 for ; Thu, 25 May 2023 12:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238970AbjEYMaG (ORCPT ); Thu, 25 May 2023 08:30:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241076AbjEYM3r (ORCPT ); Thu, 25 May 2023 08:29:47 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9138318C for ; Thu, 25 May 2023 05:29:45 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3093a778089so1355615f8f.1 for ; Thu, 25 May 2023 05:29:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685017784; x=1687609784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OuvRuDicrDkTpiapZ9qbY9ea3wcS797f7ELyYZDyHDI=; b=S/JIetgcXgA1A05nAOKXcZ9zKRE/D7BI80rlLZOkS0HH7qzevd2EASNBuHAl1QRiIR Z5rhHStymQH3/wRF4OhUt6QSnpULTb2HcRb8wkpsrB+LNejwEq/aG8b76PGp9BlmRCyI bB/o5CPJIEIm5w7Zj9B1QeasBGCkDOqTJ7Mv21FzZchz+Yi7wI1rt+oEC/UBtLyWWDib G02Dpy8RIJkl2iMLzqkGVXPzKYNFQK93lwIDIy6OSAPlpbScbTzrI77xfWa0NSVCs2/H OuU3PGH6eoqjrv//EsL9ODgMoyF5yuz9oy8dE76ZowSkatjZDetipM9P8q9ckeOBEBYk 9W/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685017784; x=1687609784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OuvRuDicrDkTpiapZ9qbY9ea3wcS797f7ELyYZDyHDI=; b=faTKSS06F5ZbZcKR1GF68N3WUHbaq2VDEmkkW4jPAiMCwjXiDdnbOhfGj8Z/riHwSp UgiLjn6ATVPbCSarbJs6TKPLWj3wa8yF9cmrZwcn0cSfQG7r6O3nfYm71UjjFhp7B0Qp N+m22g7UJAC/KjrwJ5tpYyS4NwrO4kBM17c3DDVvTMZ7ZwfxULbQklCNFb5qKUJJj6oH AjLlNtvyy7/FRQnGlkw7T2i1gjVMqKi2vLgby+0O2fPujXIfpl8NizTavetVyEKV0ys7 Ag6+L59P3Tf+u3MT9rhmWGCDG7QFHP+efuviJXaolBo6ImNWVQ09JscAXB+PjRdP68Kx mneg== X-Gm-Message-State: AC+VfDzS9pmyLsRSb3N0+aN/2kamTSyVIMkTTjyYUL9Vzf7sDjVyErVn kz+t2dmNyuaZqRFP6kZffoyFmw== X-Google-Smtp-Source: ACHHUZ72Waf3mTjj4DxvPqTfbM7OLB4xZcc5SXGEkcYd6A6DCBCK/qW5Y1RBp/H345W+Is77dTJlog== X-Received: by 2002:a5d:61d0:0:b0:306:489b:3c6 with SMTP id q16-20020a5d61d0000000b00306489b03c6mr2000407wrv.58.1685017783888; Thu, 25 May 2023 05:29:43 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id k7-20020adfe3c7000000b003062b2c5255sm1700227wrm.40.2023.05.25.05.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 05:29:43 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 1/6] dt-bindings: clock: Add YAML schemas for LPASSCC and reset on SC8280XP Date: Thu, 25 May 2023 13:29:25 +0100 Message-Id: <20230525122930.17141-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 57 +++++++++++++++++++ .../dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 12 ++++ 2 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-l= passcc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.= yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..08a9ae60a365 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + and reset on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + reg: true + + compatible: + enum: + - qcom,sc8280xp-lpasscc + + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + peripheral loader. + type: boolean + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - qcom,adsp-pil-mode + - '#reset-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@33e0000 { + compatible =3D "qcom,sc8280xp-lpasscc"; + reg =3D <0x033e0000 0x12000>; + qcom,adsp-pil-mode; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt= -bindings/clock/qcom,lpasscc-sc8280xp.h new file mode 100644 index 000000000000..df800ea2741c --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif --=20 2.21.0 From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 409EBC77B7E for ; Thu, 25 May 2023 12:30:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241135AbjEYMaC (ORCPT ); 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Thu, 25 May 2023 05:29:44 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 2/6] dt-bindings: clock: Add YAML schemas for LPASS AUDIOCC and reset on SC8280XP Date: Thu, 25 May 2023 13:29:26 +0100 Message-Id: <20230525122930.17141-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.= yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 08a9ae60a365..0557e74d3c3b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -21,6 +21,7 @@ properties: =20 compatible: enum: + - qcom,sc8280xp-lpassaudiocc - qcom,sc8280xp-lpasscc =20 qcom,adsp-pil-mode: @@ -45,6 +46,16 @@ required: additionalProperties: false =20 examples: + - | + #include + lpass_audiocc: clock-controller@32a9000 { + compatible =3D "qcom,sc8280xp-lpassaudiocc"; + reg =3D <0x032a9000 0x1000>; + qcom,adsp-pil-mode; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + }; + - | #include lpasscc: clock-controller@33e0000 { diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt= -bindings/clock/qcom,lpasscc-sc8280xp.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H =20 +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 =20 --=20 2.21.0 From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF13C87FDC for ; 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Thu, 25 May 2023 05:29:47 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id k7-20020adfe3c7000000b003062b2c5255sm1700227wrm.40.2023.05.25.05.29.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 05:29:46 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 3/6] clk: qcom: Add lpass clock controller driver for SC8280XP Date: Thu, 25 May 2023 13:29:27 +0100 Message-Id: <20230525122930.17141-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the lpass clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- drivers/clk/qcom/Kconfig | 8 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc8280xp.c | 63 +++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 85869e7a9f16..e25993abb519 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -523,6 +523,14 @@ config SC_LPASSCC_7280 Say Y if you want to use the LPASS branch clocks of the LPASS clock controller to reset the LPASS subsystem. =20 +config SC_LPASSCC_8280XP + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" + select SC_GCC_8280XP + help + Support for the LPASS clock controller on SC8280XP devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_LPASS_CORECC_7180 tristate "SC7180 LPASS Core Clock Controller" select SC_GCC_7180 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..1d420e112fae 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SC_GPUCC_7180) +=3D gpucc-sc7180.o obj-$(CONFIG_SC_GPUCC_7280) +=3D gpucc-sc7280.o obj-$(CONFIG_SC_GPUCC_8280XP) +=3D gpucc-sc8280xp.o obj-$(CONFIG_SC_LPASSCC_7280) +=3D lpasscc-sc7280.o +obj-$(CONFIG_SC_LPASSCC_8280XP) +=3D lpasscc-sc8280xp.o obj-$(CONFIG_SC_LPASS_CORECC_7180) +=3D lpasscorecc-sc7180.o obj-$(CONFIG_SC_LPASS_CORECC_7280) +=3D lpasscorecc-sc7280.o lpassaudiocc-= sc7280.o obj-$(CONFIG_SC_MSS_7180) +=3D mss-sc7180.o diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc= -sc8280xp.c new file mode 100644 index 000000000000..547f15d41a9d --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpasscc_sc8280xp_resets[] =3D { + [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xc010, 1 }, +}; + +static struct regmap_config lpasscc_sc8280xp_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-tcsr", + .max_register =3D 0x12000, +}; + +static const struct qcom_cc_desc lpasscc_reset_sc8280xp_desc =3D { + .config =3D &lpasscc_sc8280xp_regmap_config, + .resets =3D lpasscc_sc8280xp_resets, + .num_resets =3D ARRAY_SIZE(lpasscc_sc8280xp_resets), +}; + +static const struct of_device_id lpasscc_sc8280xp_match_table[] =3D { + { + .compatible =3D "qcom,sc8280xp-lpasscc", + .data =3D &lpasscc_reset_sc8280xp_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table); + +static int lpasscc_sc8280xp_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc =3D of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sc8280xp_driver =3D { + .probe =3D lpasscc_sc8280xp_probe, + .driver =3D { + .name =3D "lpasscc-sc8280xp", + .of_match_table =3D lpasscc_sc8280xp_match_table, + }, +}; + +module_platform_driver(lpasscc_sc8280xp_driver); + +MODULE_AUTHOR("Srinivas Kandagatla "); +MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver"); +MODULE_LICENSE("GPL"); --=20 2.21.0 From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84925C77B7E for ; Thu, 25 May 2023 12:30:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241010AbjEYMaI (ORCPT ); Thu, 25 May 2023 08:30:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241155AbjEYM3w (ORCPT ); Thu, 25 May 2023 08:29:52 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED93C18C for ; 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Thu, 25 May 2023 05:29:48 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 4/6] clk: qcom: Add lpass audio clock controller driver for SC8280XP Date: Thu, 25 May 2023 13:29:28 +0100 Message-Id: <20230525122930.17141-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- drivers/clk/qcom/lpasscc-sc8280xp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc= -sc8280xp.c index 547f15d41a9d..60cc3c98d03d 100644 --- a/drivers/clk/qcom/lpasscc-sc8280xp.c +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -14,6 +14,26 @@ #include "common.h" #include "reset.h" =20 +static const struct qcom_reset_map lpass_audiocc_sc8280xp_resets[] =3D { + [LPASS_AUDIO_SWR_RX_CGCR] =3D { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] =3D { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] =3D { 0xd8, 1 }, +}; + +static struct regmap_config lpass_audiocc_sc8280xp_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-audio-csr", + .max_register =3D 0x1000, +}; + +static const struct qcom_cc_desc lpass_audiocc_reset_sc8280xp_desc =3D { + .config =3D &lpass_audiocc_sc8280xp_regmap_config, + .resets =3D lpass_audiocc_sc8280xp_resets, + .num_resets =3D ARRAY_SIZE(lpass_audiocc_sc8280xp_resets), +}; + static const struct qcom_reset_map lpasscc_sc8280xp_resets[] =3D { [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xc010, 1 }, }; @@ -34,6 +54,9 @@ static const struct qcom_cc_desc lpasscc_reset_sc8280xp_d= esc =3D { =20 static const struct of_device_id lpasscc_sc8280xp_match_table[] =3D { { + .compatible =3D "qcom,sc8280xp-lpassaudiocc", + .data =3D &lpass_audiocc_reset_sc8280xp_desc, + }, { .compatible =3D "qcom,sc8280xp-lpasscc", .data =3D &lpasscc_reset_sc8280xp_desc, }, --=20 2.21.0 From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09308C7EE2D for ; Thu, 25 May 2023 12:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241144AbjEYMaK (ORCPT ); Thu, 25 May 2023 08:30:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241034AbjEYM3y (ORCPT ); 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Thu, 25 May 2023 05:29:50 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 5/6] arm64: dts: qcom: sc8280xp: add resets for soundwire controllers Date: Thu, 25 May 2023 13:29:29 +0100 Message-Id: <20230525122930.17141-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Soundwire controllers on sc8280xp needs an explicit reset, add support for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 6730349e34f4..39be2e89ce05 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -2560,6 +2561,8 @@ interrupts =3D ; clocks =3D <&rxmacro>; clock-names =3D "iface"; + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names =3D "swr_audio_cgcr"; label =3D "RX"; =20 qcom,din-ports =3D <0>; @@ -2634,6 +2637,8 @@ interrupts =3D ; clocks =3D <&wsamacro>; clock-names =3D "iface"; + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names =3D "swr_audio_cgcr"; label =3D "WSA"; =20 qcom,din-ports =3D <2>; @@ -2656,6 +2661,14 @@ status =3D "disabled"; }; =20 + lpass_audiocc: clock-controller@32a9000 { + compatible =3D "qcom,sc8280xp-lpassaudiocc"; + reg =3D <0 0x032a9000 0 0x1000>; + qcom,adsp-pil-mode; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + swr2: soundwire-controller@3330000 { compatible =3D "qcom,soundwire-v1.6.0"; reg =3D <0 0x03330000 0 0x2000>; @@ -2665,6 +2678,8 @@ =20 clocks =3D <&txmacro>; clock-names =3D "iface"; + resets =3D <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names =3D "swr_audio_cgcr"; label =3D "TX"; #sound-dai-cells =3D <1>; #address-cells =3D <2>; @@ -2901,6 +2916,14 @@ }; }; =20 + lpasscc: clock-controller@33e0000 { + compatible =3D "qcom,sc8280xp-lpasscc"; + reg =3D <0 0x033e0000 0 0x12000>; + qcom,adsp-pil-mode; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + usb_0_qmpphy: phy@88eb000 { compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; reg =3D <0 0x088eb000 0 0x4000>; --=20 2.21.0 From nobody Mon Feb 9 02:55:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C160C7EE29 for ; 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Thu, 25 May 2023 05:29:53 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id k7-20020adfe3c7000000b003062b2c5255sm1700227wrm.40.2023.05.25.05.29.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 05:29:52 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 6/6] arm64: defconfig: Enable sc828x0xp lpasscc clock controller Date: Thu, 25 May 2023 13:29:30 +0100 Message-Id: <20230525122930.17141-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> References: <20230525122930.17141-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enabled sc828x0xp lpasscc clock controller driver required for X13s laptop. Signed-off-by: Srinivas Kandagatla Reviewed-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 57ceb528426d..95ece45fd0cd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1176,6 +1176,7 @@ CONFIG_SC_GCC_7180=3Dy CONFIG_SC_GCC_7280=3Dy CONFIG_SC_GCC_8180X=3Dy CONFIG_SC_GCC_8280XP=3Dy +CONFIG_SC_LPASSCC_8280XP=3Dm CONFIG_SDM_CAMCC_845=3Dm CONFIG_SDM_GPUCC_845=3Dy CONFIG_SDM_VIDEOCC_845=3Dy --=20 2.21.0