From nobody Sun Feb 8 22:17:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFFEBC7EE2C for ; Thu, 25 May 2023 09:58:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240246AbjEYJ6i (ORCPT ); Thu, 25 May 2023 05:58:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239290AbjEYJ6b (ORCPT ); Thu, 25 May 2023 05:58:31 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8A4DCE47 for ; Thu, 25 May 2023 02:58:28 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 272621042; Thu, 25 May 2023 02:59:13 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B2BEB3F762; Thu, 25 May 2023 02:58:21 -0700 (PDT) From: Suzuki K Poulose To: coresight@lists.linaro.org Cc: mike.leach@linaro.org, linux-arm-kernel@lists.infradead.org, james.clark@arm.com, anshuman.khandual@arm.com, linux-kernel@vger.kernel.org, Suzuki K Poulose , Rob Herring , frowand.list@gmail.com, linux@armlinux.org.uk Subject: [RFC PATCH] coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE Date: Thu, 25 May 2023 10:58:07 +0100 Message-Id: <20230525095807.1379811-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All, This is an RFC patch to allow all ETM4 instances to be detected via AMBA dr= iver without having to add the PIDs to the list. The AMBA driver already supports checking the DEVTYPE and DEVARCH registers for CoreSight components. This p= atch adds a pid,mask value that is bound to match all PIDs (with PIDR2.JEDEC fie= ld mandated to be RA0). With this patch, we wouldn't need to add the PIDs for newer CPUs to be able= to use them. An entry in the device tree is all we need. The only side effect = of this patch is : If a DT description exists for an ETM and the CPU ETM has an erratum, t= he driver may still probe it and use it. But then the DT shouldn't have described it in the first place. Thoughts? Suzuki ---8>--- coresight: etm4x: Match all ETM4 instances based on DEVARCH Instead of adding the PIDs forever to the list for the new CPUs, let us det= ect a component to be ETMv4 based on the CoreSight CID, DEVTYPE=3DPE_TRACE and DEVARCH=3DETMv4. This is already done for some of the ETMs. We can extend t= he PID matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@= arm.com Cc: Anshuman Khandual Cc: Rob Herring Cc: frowand.list@gmail.com Cc: linux@armlinux.org.uk Signed-off-by: Suzuki K Poulose --- .../coresight/coresight-etm4x-core.c | 5 +++++ drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 4c15fae534f3..8a2e24d5686a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] =3D { CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ + /* + * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new + * CPUs to the list here. + */ + CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), {}, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 595ce5862056..72ec36c9232c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); } =20 /* coresight AMBA ID, full UCI structure: id table entry. */ -#define CS_AMBA_UCI_ID(pid, uci_ptr) \ +#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ { \ .id =3D pid, \ - .mask =3D 0x000fffff, \ + .mask =3D m, \ .data =3D (void *)uci_ptr \ } +#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) +/* + * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of t= he + * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use t= hat + * as a match value for blanket matching all devices in the given CoreSight + * device type and architecture. + */ +#define PIDR2_JEDEC BIT(3) +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) +/* + * Match all PIDs in a given CoreSight device type and architecture, defin= ed + * by the uci. + */ +#define CS_AMBA_MATCH_ALL_UCI(uci) \ + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) =20 /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id) --=20 2.34.1