From nobody Fri Sep 20 21:36:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB504C7EE39 for ; Thu, 25 May 2023 07:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238579AbjEYHux (ORCPT ); Thu, 25 May 2023 03:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238327AbjEYHu1 (ORCPT ); Thu, 25 May 2023 03:50:27 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E535DE44; Thu, 25 May 2023 00:50:25 -0700 (PDT) X-UUID: cc77dc7efad011edb20a276fd37b9834-20230525 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+/PT1g6QlwpXN2nAdR0WgUNtqQaT3dNJ82IueyTB+Kg=; b=Wlk3oFP48zfpJ6sZ/7yPdv23r5e/Baqg/bRY5o8em5Oc14/NaTV6SrBpo8HMHEjaGSMv+30L7BEvSgH4KQ1MpFMQTDt0OPlvdPspmHLPgp5Hjouy/IdTSKVz4vcKm81HhUXZnPZv3+PayAbCsFrd3dP4xRYHnyfNBXtzt6Rs9cE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25,REQID:91c0a840-2f9f-4c66-bc80-5c8548da692b,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.25,REQID:91c0a840-2f9f-4c66-bc80-5c8548da692b,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:d5b0ae3,CLOUDID:9f05833c-7aa7-41f3-a6bd-0433bee822f3,B ulkID:230525155021GNV4CWZT,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: cc77dc7efad011edb20a276fd37b9834-20230525 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 950351365; Thu, 25 May 2023 15:50:20 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 25 May 2023 15:50:19 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 25 May 2023 15:50:19 +0800 From: Runyang Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , "Philipp Zabel" , Rob Herring , "Krzysztof Kozlowski" CC: , , , , , Runyang Chen Subject: [PATCH v4 2/2] clk: mediatek: reset: add infra_ao reset support for MT8188 Date: Thu, 25 May 2023 15:50:11 +0800 Message-ID: <20230525075011.7032-3-runyang.chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20230525075011.7032-1-runyang.chen@mediatek.com> References: <20230525075011.7032-1-runyang.chen@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The infra_ao reset is needed for MT8188. - Add mtk_clk_rst_desc for MT8188. - Add register reset controller function for MT8188 infra_ao. - Add infra_ao_idx_map for MT8188. Signed-off-by: Runyang Chen Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202305242320.AZzmINEa-lkp@int= el.com/ Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/media= tek/clk-mt8188-infra_ao.c index a38ddc7b6a88..f590178737cb 100644 --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include =20 @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] =3D { "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), }; =20 +static u16 infra_ao_rst_ofs[] =3D { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static u16 infra_ao_idx_map[] =3D { + [MT8188_INFRA_RST1_THERMAL_MCU_RST] =3D 1 * RST_NR_PER_BANK + 2, + [MT8188_INFRA_RST1_THERMAL_CTRL_RST] =3D 1 * RST_NR_PER_BANK + 4, + [MT8188_INFRA_RST3_PTP_CTRL_RST] =3D 3 * RST_NR_PER_BANK + 5, +}; + +static const struct mtk_clk_rst_desc infra_ao_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D infra_ao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map =3D infra_ao_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), +}; + static const struct mtk_clk_desc infra_ao_desc =3D { .clks =3D infra_ao_clks, .num_clks =3D ARRAY_SIZE(infra_ao_clks), + .rst_desc =3D &infra_ao_rst_desc, }; =20 static const struct of_device_id of_match_clk_mt8188_infra_ao[] =3D { --=20 2.18.0