From nobody Mon Feb 9 05:14:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F390C7EE23 for ; Thu, 25 May 2023 02:50:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236996AbjEYCu3 (ORCPT ); Wed, 24 May 2023 22:50:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236092AbjEYCuY (ORCPT ); Wed, 24 May 2023 22:50:24 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66D221A6 for ; Wed, 24 May 2023 19:50:22 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-25332422531so399185a91.0 for ; Wed, 24 May 2023 19:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20221208.gappssmtp.com; s=20221208; t=1684983022; x=1687575022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RpwfMsZIM/RuZJMwhQTZ2UB3MwnIPR30emTjY22XhF0=; b=KHedM/CVXZ9cf6hNEYMtXSj5ut+e+GcTxZxtBOh30Z1+FpTfqZY2ZS5JSnGqgyu4jP LfQNcV7WR6BpEfrB3/8wrI1u0atJ55Avmi8PcZ3aUOy4EenA1iodx8f4NJzaqAMM/iV1 yx7Otwh6HkJfkziH/B2Bi3pEggtU1xOZsv7KlUZw1YbOIV0ZSBoSTgrMKOqeOoLP+yjt w69nUcVwkYKEoTSS48q+HrqM5Ie1arT1id4cR9EQS+hesBpUDqBSRVhAfgm+aOBdAZzY vrwmUyT6rSotPORsa/bVaYV/mRcp+IpQOpDx8eguuToq1QTUfi4PGRjz4vVmBvv8HSIw hbMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684983022; x=1687575022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RpwfMsZIM/RuZJMwhQTZ2UB3MwnIPR30emTjY22XhF0=; b=D8GAlPtEjcPTsqIcIvs/yzLWR3aH1hFndbU3DGj6xqjCEwx1XTh33YXdTQNNSf8Fpn pyKClazH67y3sMPEZzFydvwE/CuDPQr3sCeO4BPyZuGo6CquByb4TuLTGkLl9a5RzYnh M0rcAsBohrH1qKvSu5SC9wXUe6WlwVsn+enP+sxfusl2HnNi+5Ja82w2DNB0+pEZShIv yKsHOpb+kLEqMZug7IPBZnctwWnVtK6wqqLSnWNmUZJ+lC8d2Q/N85Q7SZHbyjfBB5nF YvHUOMylw0cPKsRhYl+Gtl+cML/7wIlQ4XZdf53gIq/qMWelhGEUvfYOYT/DE75UsATt unug== X-Gm-Message-State: AC+VfDxQCH+qkp4RQYOSG1F2w1xowd34UkncSNsWr8A4fgpT+u1it//m IfCIo0V7GRHdwDFOe7Hawy64xA== X-Google-Smtp-Source: ACHHUZ4WgUyHEalLnXKujv6G0ziF4q8IDMdhMFSyCM3orhs22q3QLabVelnxHkXTjk+bcJBY28stHA== X-Received: by 2002:a17:90b:f91:b0:253:3dd9:79e6 with SMTP id ft17-20020a17090b0f9100b002533dd979e6mr202431pjb.0.1684983021805; Wed, 24 May 2023 19:50:21 -0700 (PDT) Received: from yc.huaqin.com ([101.78.151.214]) by smtp.gmail.com with ESMTPSA id j6-20020a17090a734600b00253239144c5sm171815pjs.42.2023.05.24.19.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 19:50:21 -0700 (PDT) From: Cong Yang To: dianders@chromium.org Cc: airlied@gmail.com, conor+dt@kernel.org, daniel@ffwll.ch, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, hsinyi@google.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, robh+dt@kernel.org, sam@ravnborg.org, Cong Yang , Conor Dooley Subject: [v3 1/4] dt-bindings: display: panel: Add compatible for Starry himax83102-j02 Date: Thu, 25 May 2023 10:49:57 +0800 Message-Id: <20230525025000.3692510-2-yangcong5@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> References: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The STARRY himax83102-j02 is a 10.51" WUXGA TFT LCD panel, which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new compatible with panel specific config. Signed-off-by: Cong Yang Reviewed-by: Douglas Anderson Acked-by: Conor Dooley --- .../devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n= l6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.= yaml index aed55608ebf6..28a7beeb8f92 100644 --- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml @@ -32,6 +32,8 @@ properties: - innolux,hj110iz-01a # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel - starry,2081101qfh032011-53g + # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel + - starry,himax83102-j02 =20 reg: description: the virtual channel number of a DSI peripheral --=20 2.25.1 From nobody Mon Feb 9 05:14:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0771AC7EE23 for ; Thu, 25 May 2023 02:50:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235107AbjEYCuj (ORCPT ); Wed, 24 May 2023 22:50:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49428 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236656AbjEYCud (ORCPT ); Wed, 24 May 2023 22:50:33 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F348C195 for ; Wed, 24 May 2023 19:50:30 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-530638a60e1so944893a12.2 for ; Wed, 24 May 2023 19:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20221208.gappssmtp.com; s=20221208; t=1684983030; x=1687575030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/CJNJchATCPkxIGeEGlUrxEfsyj8dI4b4dLgXJyu4c=; b=seOm5+a0zkAICOxseXsgCreJLCc6VfKJhcd32DS6QV67A1QdhRalgOc2PP97AKW5OY 3BSCawy0DV9VmXmwOfto3ffdGyMj+ZSuQG5tpNLVYuOGw3nImpWBzTJ2bFGQLBtdFAbW Fig/LvpvgBlv+UzufpxNZwvTTYFFpOyYP8izHcx+uHXLOU6m3pKgh9JQcE8sUymHHyn2 wisHbFUIRTmrwhNOIIrsRd3df6+y3BHLaOSiNYUf+wEUslNYPAFbhLo6pLJaIF5rBWiY gWQW5kNmliVIO15V7P56eFTxtCiQ2HRgoCS7Q8W848m8SClAcEIl+wOx76bS8raGYYWX 3pNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684983030; x=1687575030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/CJNJchATCPkxIGeEGlUrxEfsyj8dI4b4dLgXJyu4c=; b=gXcqSy8fBItB4+qrVJ5u6ZJjcr9fxoYcE5ngA1c2IUAps7v3DSuWiZTGY9YuPx2M3h Ohd7lU+wfW9fxPG4n1vR9tgE3YYE9xh8WmJfbwV37S1UQISXKByL1LqSetyqCx7BrcHo LL39mC+8OuhKBZvF/Ap4vcdNpkjIgm242CS5dWau3CnX7yoCg+/2/QvVWm847zowR0WV KPDSGxvqDKV1rkwDKwR5rN1dgkDE/zjrmHgCQrMUvlj6U3podPdJHXw0XoqMazpkgDvL xaowiRyqgHAmXuUcv28bFMj27Gv9OyNTjR7nTblpodPaBcPnTPYFD3aug8y6Pws/2A7V 9xPA== X-Gm-Message-State: AC+VfDw7hVYk23qYvoBZnhRB4kGzhuO6MnCEeV8Pt1AKLzQDq99kkC1D o79GFt8SKdw0VmJSr00kb4ZU6w== X-Google-Smtp-Source: ACHHUZ4d6/xyhbyAIyxkcdJBlTd/wUuPCb4o0kcZrcxRJBYvTpKIVF87ScG2vFtWl15OMyXc3wHufQ== X-Received: by 2002:a05:6a20:72a8:b0:10c:1047:68b9 with SMTP id o40-20020a056a2072a800b0010c104768b9mr11323874pzk.50.1684983030026; Wed, 24 May 2023 19:50:30 -0700 (PDT) Received: from yc.huaqin.com ([101.78.151.214]) by smtp.gmail.com with ESMTPSA id j6-20020a17090a734600b00253239144c5sm171815pjs.42.2023.05.24.19.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 19:50:29 -0700 (PDT) From: Cong Yang To: dianders@chromium.org Cc: airlied@gmail.com, conor+dt@kernel.org, daniel@ffwll.ch, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, hsinyi@google.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, robh+dt@kernel.org, sam@ravnborg.org, Cong Yang , Conor Dooley Subject: [v3 2/4] drm/panel: Support for Starry-himax83102-j02 TDDI MIPI-DSI panel Date: Thu, 25 May 2023 10:49:58 +0800 Message-Id: <20230525025000.3692510-3-yangcong5@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> References: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Starry-himax83102-j02 is a 10.51" WUXGA TFT panel. which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. From the datasheet[1], MIPI needs to keep the LP11 state before the lcm_reset pin is pulled high, so increase lp11_before_reset flag. [1]: https://github.com/HimaxSoftware/Doc/tree/main/Himax_Chipset_Power_Seq= uence Signed-off-by: Cong Yang Reviewed-by: Douglas Anderson Acked-by: Conor Dooley --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index f5a6046f1d19..0772d96e446c 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1301,6 +1301,75 @@ static const struct panel_init_cmd starry_qfh032011_= 53g_init_cmd[] =3D { {}, }; =20 +static const struct panel_init_cmd starry_himax83102_j02_init_cmd[] =3D { + _INIT_DCS_CMD(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), + _INIT_DCS_CMD(0xB1, 0x2C, 0xB5, 0xB5, 0x31, 0xF1, 0x31, 0xD7, 0x2F, 0x36,= 0x36, 0x36, 0x36, 0x1A, 0x8B, 0x11, + 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0x74, 0x33), + _INIT_DCS_CMD(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x72, 0x3C, 0xA3,= 0x03, 0x03, 0x00, 0x00, 0x88, 0xF5), + _INIT_DCS_CMD(0xB4, 0x76, 0x76, 0x76, 0x76, 0x76, 0x76, 0x63, 0x5C, 0x63,= 0x5C, 0x01, 0x9E), + _INIT_DCS_CMD(0xE9, 0xCD), + _INIT_DCS_CMD(0xBA, 0x84), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xBC, 0x1B, 0x04), + _INIT_DCS_CMD(0xBE, 0x20), + _INIT_DCS_CMD(0xBF, 0xFC, 0xC4), + _INIT_DCS_CMD(0xC0, 0x36, 0x36, 0x22, 0x11, 0x22, 0xA0, 0x61, 0x08, 0xF5,= 0x03), + _INIT_DCS_CMD(0xE9, 0xCC), + _INIT_DCS_CMD(0xC7, 0x80), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xE9, 0xC6), + _INIT_DCS_CMD(0xC8, 0x97), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xC9, 0x00, 0x1E, 0x13, 0x88, 0x01), + _INIT_DCS_CMD(0xCB, 0x08, 0x13, 0x07, 0x00, 0x0F, 0x33), + _INIT_DCS_CMD(0xCC, 0x02), + _INIT_DCS_CMD(0xE9, 0xC4), + _INIT_DCS_CMD(0xD0, 0x03), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xD1, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0C, 0xFF), + _INIT_DCS_CMD(0xD2, 0x1F, 0x11, 0x1F), + _INIT_DCS_CMD(0xD3, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08,= 0x37, 0x47, 0x34, 0x3B, 0x12, 0x12, 0x03, + 0x03, 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, = 0x17, 0x94, 0x07, 0x94, 0x00, 0x00), + _INIT_DCS_CMD(0xD5, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,= 0x18, 0x19, 0x19, 0x40, 0x40, 0x1A, 0x1A, + 0x1B, 0x1B, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, = 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1= 8, 0x18, 0x18, 0x18), + _INIT_DCS_CMD(0xD6, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,= 0x18, 0x40, 0x40, 0x19, 0x19, 0x1A, 0x1A, + 0x1B, 0x1B, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, = 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1= 8, 0x18, 0x18, 0x18), + _INIT_DCS_CMD(0xD8, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA,= 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, + 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, = 0xAA, 0xA0, 0xAA, 0xBA, 0xEA, 0xAA, 0xAA, 0xA0), + _INIT_DCS_CMD(0xE0, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, 0x67, 0x6C,= 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, + 0xAB, 0x55, 0x5C, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1E, 0x26, 0x48, 0x61, = 0x67, 0x6C, 0x67, 0x7D, 0x7F, 0x80, 0x8B, 0x87, 0x8F, 0x98, 0xAB, 0xAB, 0x5= 5, 0x5C, 0x68, 0x73), + _INIT_DCS_CMD(0xE7, 0x0E, 0x10, 0x10, 0x21, 0x2B, 0x9A, 0x02, 0x54, 0x9A,= 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 0x02, 0x02, 0x10), + _INIT_DCS_CMD(0xBD, 0x01), + _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11), + _INIT_DCS_CMD(0xCB, 0x86), + _INIT_DCS_CMD(0xD2, 0x3C, 0xFA), + _INIT_DCS_CMD(0xE9, 0xC5), + _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0,= 0x00, 0x00, 0x20, 0x40, 0x50, 0x40), + _INIT_DCS_CMD(0xBD, 0x02), + _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF,= 0xFE, 0xAA, 0xA0), + _INIT_DCS_CMD(0xE7, 0xFE, 0x04, 0xFE, 0x04, 0xFE, 0x04, 0x03, 0x03, 0x03,= 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 0x9E, 0x04, 0x03, 0x02, 0x= 01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00), + _INIT_DCS_CMD(0xBD, 0x03), + _INIT_DCS_CMD(0xE9, 0xC6), + _INIT_DCS_CMD(0xB4, 0x03, 0xFF, 0xF8), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xD8, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA,= 0xA8, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0x= FC, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0xA8, 0x00, 0x00, 0x00, 0x2A, 0xAA, 0x= A8, 0x00, 0x00), + _INIT_DCS_CMD(0xBD, 0x00), + _INIT_DCS_CMD(0xE9, 0xC4), + _INIT_DCS_CMD(0xBA, 0x96), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xBD, 0x01), + _INIT_DCS_CMD(0xE9, 0xC5), + _INIT_DCS_CMD(0xBA, 0x4F), + _INIT_DCS_CMD(0xE9, 0x3F), + _INIT_DCS_CMD(0xBD, 0x00), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(120), + _INIT_DCS_CMD(0x29), + {}, +}; + static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) { return container_of(panel, struct boe_panel, base); @@ -1698,6 +1767,34 @@ static const struct panel_desc starry_qfh032011_53g_= desc =3D { .init_cmds =3D starry_qfh032011_53g_init_cmd, }; =20 +static const struct drm_display_mode starry_himax83102_j02_default_mode = =3D { + .clock =3D 161600, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 40, + .hsync_end =3D 1200 + 40 + 20, + .htotal =3D 1200 + 40 + 20 + 40, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 116, + .vsync_end =3D 1920 + 116 + 8, + .vtotal =3D 1920 + 116 + 8 + 12, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc starry_himax83102_j02_desc =3D { + .modes =3D &starry_himax83102_j02_default_mode, + .bpc =3D 8, + .size =3D { + .width_mm =3D 141, + .height_mm =3D 226, + }, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds =3D starry_himax83102_j02_init_cmd, + .lp11_before_reset =3D true, +}; + static int boe_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -1871,6 +1968,9 @@ static const struct of_device_id boe_of_match[] =3D { { .compatible =3D "starry,2081101qfh032011-53g", .data =3D &starry_qfh032011_53g_desc }, + { .compatible =3D "starry,himax83102-j02", + .data =3D &starry_himax83102_j02_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_of_match); --=20 2.25.1 From nobody Mon Feb 9 05:14:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53ED4C77B73 for ; Thu, 25 May 2023 02:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235700AbjEYCu6 (ORCPT ); Wed, 24 May 2023 22:50:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236074AbjEYCux (ORCPT ); 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Wed, 24 May 2023 19:50:47 -0700 (PDT) From: Cong Yang To: dianders@chromium.org Cc: airlied@gmail.com, conor+dt@kernel.org, daniel@ffwll.ch, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, hsinyi@google.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, robh+dt@kernel.org, sam@ravnborg.org, Cong Yang , Conor Dooley Subject: [v3 3/4] dt-bindings: display: panel: Add compatible for Starry ili9882t Date: Thu, 25 May 2023 10:49:59 +0800 Message-Id: <20230525025000.3692510-4-yangcong5@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> References: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The STARRY ili9882t is a 10.51" WUXGA TFT LCD panel, which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. Hence, we add a new compatible with panel specific config. Signed-off-by: Cong Yang Reviewed-by: Douglas Anderson Acked-by: Conor Dooley --- .../devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-n= l6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.= yaml index 28a7beeb8f92..906ef62709b8 100644 --- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml @@ -34,6 +34,8 @@ properties: - starry,2081101qfh032011-53g # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 + # STARRY ili9882t 10.51" WUXGA TFT LCD panel + - starry,ili9882t =20 reg: description: the virtual channel number of a DSI peripheral --=20 2.25.1 From nobody Mon Feb 9 05:14:27 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABC3FC77B73 for ; Thu, 25 May 2023 02:51:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237838AbjEYCvR (ORCPT ); Wed, 24 May 2023 22:51:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237875AbjEYCvH (ORCPT ); Wed, 24 May 2023 22:51:07 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 883E7194 for ; Wed, 24 May 2023 19:51:05 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-2535d86a41bso697595a91.3 for ; Wed, 24 May 2023 19:51:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=huaqin-corp-partner-google-com.20221208.gappssmtp.com; s=20221208; t=1684983065; x=1687575065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qHM+l0htD69ac0mPAbRuuj3Va/ygqtMKbdcFmiltfRw=; b=VpC0fIQ0eiAREE5F8s/eyu3eTC6lY1hhgQRZA9dHDJb5Jry5DXnoywSoq9OQZj52MU VkIxPzjrfPs/Dd2bmc68ooHZJlr1yg/yKXpiAZkUHDfo+HY7KkLd43s61eQhPdGCAD0y qaZ59JPqbmUUFj+s6i8Jiv02wuA/MeuLskwbvh1CyXiecbawMO4mpous7u7tiH9axCzi zWK1rK3WSo/OdJq3v8ALRdLbBulOGZXdNEm6p0HYeYQVhgGCxzfevAUxGs5Tw2HBYA7x UEZGZZ0IbzDn5k4r0M3f0KFGQDA3juAPeklvJgDoLSSm2D5sh3Ql0n3JprWv9uz9eurF eS+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684983065; x=1687575065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qHM+l0htD69ac0mPAbRuuj3Va/ygqtMKbdcFmiltfRw=; b=NIZem1yTwM0V+ox3YWLLyPUz6+ixudHSmNY5gDSEXF7fLNgv3jYI/HDUoidk/yzAcW 9qCrBUw41TGAg6w6wbtUTsq5sRWjHfiuLasDDkGeXb0FXno+8bHzZwPSMiS92s1TRRaj JS7Pg3gH9fSdZdfu1ktLs20SWcnMeJVYu/rqTypuz15bjmWz32darJ1L+/c1jNf9bfP+ dDJh29/KZ8EQ0nDhULZgaJMkD7TvwOQgyX118SEgcVcr1coWTwqdj8fYmrLpcGw9fuxQ YUWnIjYBIqWMIIZ2L73FdhBxBIbsXDUE1ZYg85Ba34zz4rv1whsQu1NTzkF+pMP6eLba LQ3Q== X-Gm-Message-State: AC+VfDzroYUPrxeZP4xxlLcJVrZHfODKFVwE+PimEqeHaOpVce3eXkHM NtBaa8MhMNsaOJaZuA7CLqLsnQ== X-Google-Smtp-Source: ACHHUZ5fuSPiB51Cq7kZ5u1LxZRgttivlOmsK5lvDP8n53d4ZN90PI8wPe/39455PLhnrWj9WpOBFQ== X-Received: by 2002:a17:90b:3145:b0:247:2152:6391 with SMTP id ip5-20020a17090b314500b0024721526391mr106754pjb.17.1684983065007; Wed, 24 May 2023 19:51:05 -0700 (PDT) Received: from yc.huaqin.com ([101.78.151.214]) by smtp.gmail.com with ESMTPSA id j6-20020a17090a734600b00253239144c5sm171815pjs.42.2023.05.24.19.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 May 2023 19:51:04 -0700 (PDT) From: Cong Yang To: dianders@chromium.org Cc: airlied@gmail.com, conor+dt@kernel.org, daniel@ffwll.ch, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, hsinyi@google.com, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, neil.armstrong@linaro.org, robh+dt@kernel.org, sam@ravnborg.org, Cong Yang , Conor Dooley Subject: [v3 4/4] drm/panel: Support for Starry-ili9882t TDDI MIPI-DSI panel Date: Thu, 25 May 2023 10:50:00 +0800 Message-Id: <20230525025000.3692510-5-yangcong5@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> References: <20230525025000.3692510-1-yangcong5@huaqin.corp-partner.google.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Starry-ili9882 is a 10.51" WUXGA TFT panel. which fits in nicely with the existing panel-boe-tv101wum-nl6 driver. From the datasheet,MIPI need to keep the LP11 state before the lcm_reset pin is pulled high. So add lp11_before_reset flag. Signed-off-by: Cong Yang Reviewed-by: Douglas Anderson Acked-by: Conor Dooley --- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 371 ++++++++++++++++++ 1 file changed, 371 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/d= rm/panel/panel-boe-tv101wum-nl6.c index 0772d96e446c..720b77964fcf 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -1370,6 +1370,346 @@ static const struct panel_init_cmd starry_himax8310= 2_j02_init_cmd[] =3D { {}, }; =20 +static const struct panel_init_cmd starry_ili9882t_init_cmd[] =3D { + _INIT_DELAY_CMD(5), + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x01), + _INIT_DCS_CMD(0x00, 0x42), + _INIT_DCS_CMD(0x01, 0x11), + _INIT_DCS_CMD(0x02, 0x00), + _INIT_DCS_CMD(0x03, 0x00), + + _INIT_DCS_CMD(0x04, 0x01), + _INIT_DCS_CMD(0x05, 0x11), + _INIT_DCS_CMD(0x06, 0x00), + _INIT_DCS_CMD(0x07, 0x00), + + _INIT_DCS_CMD(0x08, 0x80), + _INIT_DCS_CMD(0x09, 0x81), + _INIT_DCS_CMD(0x0A, 0x71), + _INIT_DCS_CMD(0x0B, 0x00), + + _INIT_DCS_CMD(0x0C, 0x00), + _INIT_DCS_CMD(0x0E, 0x1A), + + _INIT_DCS_CMD(0x24, 0x00), + _INIT_DCS_CMD(0x25, 0x00), + _INIT_DCS_CMD(0x26, 0x00), + _INIT_DCS_CMD(0x27, 0x00), + + _INIT_DCS_CMD(0x2C, 0xD4), + _INIT_DCS_CMD(0xB9, 0x40), + + _INIT_DCS_CMD(0xB0, 0x11), + + _INIT_DCS_CMD(0xE6, 0x32), + _INIT_DCS_CMD(0xD1, 0x30), + + _INIT_DCS_CMD(0xD6, 0x55), + + _INIT_DCS_CMD(0xD0, 0x01), + _INIT_DCS_CMD(0xE3, 0x93), + _INIT_DCS_CMD(0xE4, 0x00), + _INIT_DCS_CMD(0xE5, 0x80), + + _INIT_DCS_CMD(0x31, 0x07), + _INIT_DCS_CMD(0x32, 0x07), + _INIT_DCS_CMD(0x33, 0x07), + _INIT_DCS_CMD(0x34, 0x07), + _INIT_DCS_CMD(0x35, 0x07), + _INIT_DCS_CMD(0x36, 0x01), + _INIT_DCS_CMD(0x37, 0x00), + _INIT_DCS_CMD(0x38, 0x28), + _INIT_DCS_CMD(0x39, 0x29), + _INIT_DCS_CMD(0x3A, 0x11), + _INIT_DCS_CMD(0x3B, 0x13), + _INIT_DCS_CMD(0x3C, 0x15), + _INIT_DCS_CMD(0x3D, 0x17), + _INIT_DCS_CMD(0x3E, 0x09), + _INIT_DCS_CMD(0x3F, 0x0D), + _INIT_DCS_CMD(0x40, 0x02), + _INIT_DCS_CMD(0x41, 0x02), + _INIT_DCS_CMD(0x42, 0x02), + _INIT_DCS_CMD(0x43, 0x02), + _INIT_DCS_CMD(0x44, 0x02), + _INIT_DCS_CMD(0x45, 0x02), + _INIT_DCS_CMD(0x46, 0x02), + + _INIT_DCS_CMD(0x47, 0x07), + _INIT_DCS_CMD(0x48, 0x07), + _INIT_DCS_CMD(0x49, 0x07), + _INIT_DCS_CMD(0x4A, 0x07), + _INIT_DCS_CMD(0x4B, 0x07), + _INIT_DCS_CMD(0x4C, 0x01), + _INIT_DCS_CMD(0x4D, 0x00), + _INIT_DCS_CMD(0x4E, 0x28), + _INIT_DCS_CMD(0x4F, 0x29), + _INIT_DCS_CMD(0x50, 0x10), + _INIT_DCS_CMD(0x51, 0x12), + _INIT_DCS_CMD(0x52, 0x14), + _INIT_DCS_CMD(0x53, 0x16), + _INIT_DCS_CMD(0x54, 0x08), + _INIT_DCS_CMD(0x55, 0x0C), + _INIT_DCS_CMD(0x56, 0x02), + _INIT_DCS_CMD(0x57, 0x02), + _INIT_DCS_CMD(0x58, 0x02), + _INIT_DCS_CMD(0x59, 0x02), + _INIT_DCS_CMD(0x5A, 0x02), + _INIT_DCS_CMD(0x5B, 0x02), + _INIT_DCS_CMD(0x5C, 0x02), + + _INIT_DCS_CMD(0x61, 0x07), + _INIT_DCS_CMD(0x62, 0x07), + _INIT_DCS_CMD(0x63, 0x07), + _INIT_DCS_CMD(0x64, 0x07), + _INIT_DCS_CMD(0x65, 0x07), + _INIT_DCS_CMD(0x66, 0x01), + _INIT_DCS_CMD(0x67, 0x00), + _INIT_DCS_CMD(0x68, 0x28), + _INIT_DCS_CMD(0x69, 0x29), + _INIT_DCS_CMD(0x6A, 0x16), + _INIT_DCS_CMD(0x6B, 0x14), + _INIT_DCS_CMD(0x6C, 0x12), + _INIT_DCS_CMD(0x6D, 0x10), + _INIT_DCS_CMD(0x6E, 0x0C), + _INIT_DCS_CMD(0x6F, 0x08), + _INIT_DCS_CMD(0x70, 0x02), + _INIT_DCS_CMD(0x71, 0x02), + _INIT_DCS_CMD(0x72, 0x02), + _INIT_DCS_CMD(0x73, 0x02), + _INIT_DCS_CMD(0x74, 0x02), + _INIT_DCS_CMD(0x75, 0x02), + _INIT_DCS_CMD(0x76, 0x02), + + _INIT_DCS_CMD(0x77, 0x07), + _INIT_DCS_CMD(0x78, 0x07), + _INIT_DCS_CMD(0x79, 0x07), + _INIT_DCS_CMD(0x7A, 0x07), + _INIT_DCS_CMD(0x7B, 0x07), + _INIT_DCS_CMD(0x7C, 0x01), + _INIT_DCS_CMD(0x7D, 0x00), + _INIT_DCS_CMD(0x7E, 0x28), + _INIT_DCS_CMD(0x7F, 0x29), + _INIT_DCS_CMD(0x80, 0x17), + _INIT_DCS_CMD(0x81, 0x15), + _INIT_DCS_CMD(0x82, 0x13), + _INIT_DCS_CMD(0x83, 0x11), + _INIT_DCS_CMD(0x84, 0x0D), + _INIT_DCS_CMD(0x85, 0x09), + _INIT_DCS_CMD(0x86, 0x02), + _INIT_DCS_CMD(0x87, 0x07), + _INIT_DCS_CMD(0x88, 0x07), + _INIT_DCS_CMD(0x89, 0x07), + _INIT_DCS_CMD(0x8A, 0x07), + _INIT_DCS_CMD(0x8B, 0x07), + _INIT_DCS_CMD(0x8C, 0x07), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x02), + _INIT_DCS_CMD(0x29, 0x3A), + _INIT_DCS_CMD(0x2A, 0x3B), + + _INIT_DCS_CMD(0x06, 0x01), + _INIT_DCS_CMD(0x07, 0x01), + _INIT_DCS_CMD(0x08, 0x0C), + _INIT_DCS_CMD(0x09, 0x44), + + _INIT_DCS_CMD(0x3C, 0x0A), + _INIT_DCS_CMD(0x39, 0x11), + _INIT_DCS_CMD(0x3D, 0x00), + _INIT_DCS_CMD(0x3A, 0x0C), + _INIT_DCS_CMD(0x3B, 0x44), + + _INIT_DCS_CMD(0x53, 0x1F), + _INIT_DCS_CMD(0x5E, 0x40), + _INIT_DCS_CMD(0x84, 0x00), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x03), + _INIT_DCS_CMD(0x20, 0x01), + _INIT_DCS_CMD(0x21, 0x3C), + _INIT_DCS_CMD(0x22, 0xFA), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0A), + _INIT_DCS_CMD(0xE0, 0x01), + _INIT_DCS_CMD(0xE2, 0x01), + _INIT_DCS_CMD(0xE5, 0x91), + _INIT_DCS_CMD(0xE6, 0x3C), + _INIT_DCS_CMD(0xE7, 0x00), + _INIT_DCS_CMD(0xE8, 0xFA), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x12), + _INIT_DCS_CMD(0x87, 0x2C), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x05), + _INIT_DCS_CMD(0x73, 0xE5), + _INIT_DCS_CMD(0x7F, 0x6B), + _INIT_DCS_CMD(0x6D, 0xA4), + _INIT_DCS_CMD(0x79, 0x54), + _INIT_DCS_CMD(0x69, 0x97), + _INIT_DCS_CMD(0x6A, 0x97), + _INIT_DCS_CMD(0xA5, 0x3F), + _INIT_DCS_CMD(0x61, 0xDA), + _INIT_DCS_CMD(0xA7, 0xF1), + _INIT_DCS_CMD(0x5F, 0x01), + _INIT_DCS_CMD(0x62, 0x3F), + _INIT_DCS_CMD(0x1D, 0x90), + _INIT_DCS_CMD(0x86, 0x87), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x06), + _INIT_DCS_CMD(0xC0, 0x80), + _INIT_DCS_CMD(0xC1, 0x07), + _INIT_DCS_CMD(0xCA, 0x58), + _INIT_DCS_CMD(0xCB, 0x02), + _INIT_DCS_CMD(0xCE, 0x58), + _INIT_DCS_CMD(0xCF, 0x02), + _INIT_DCS_CMD(0x67, 0x60), + _INIT_DCS_CMD(0x10, 0x00), + _INIT_DCS_CMD(0x92, 0x22), + _INIT_DCS_CMD(0xD3, 0x08), + _INIT_DCS_CMD(0xD6, 0x55), + _INIT_DCS_CMD(0xDC, 0x38), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x08), + _INIT_DCS_CMD(0xE0, 0x00, 0x10, 0x2A, 0x4D, 0x61, 0x56, 0x6A, 0x6E, 0x79,= 0x76, 0x8F, 0x95, 0x98, 0xAE, 0xAA, 0xB2, 0xBB, 0xCE, 0xC6, 0xBD, 0xD5, 0x= E2, 0xE8), + _INIT_DCS_CMD(0xE1, 0x00, 0x10, 0x2A, 0x4D, 0x61, 0x56, 0x6A, 0x6E, 0x79,= 0x76, 0x8F, 0x95, 0x98, 0xAE, 0xAA, 0xB2, 0xBB, 0xCE, 0xC6, 0xBD, 0xD5, 0x= E2, 0xE8), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x04), + _INIT_DCS_CMD(0xBA, 0x81), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0C), + _INIT_DCS_CMD(0x00, 0x02), + _INIT_DCS_CMD(0x01, 0x00), + _INIT_DCS_CMD(0x02, 0x03), + _INIT_DCS_CMD(0x03, 0x01), + _INIT_DCS_CMD(0x04, 0x03), + _INIT_DCS_CMD(0x05, 0x02), + _INIT_DCS_CMD(0x06, 0x04), + _INIT_DCS_CMD(0x07, 0x03), + _INIT_DCS_CMD(0x08, 0x03), + _INIT_DCS_CMD(0x09, 0x04), + _INIT_DCS_CMD(0x0A, 0x04), + _INIT_DCS_CMD(0x0B, 0x05), + _INIT_DCS_CMD(0x0C, 0x04), + _INIT_DCS_CMD(0x0D, 0x06), + _INIT_DCS_CMD(0x0E, 0x05), + _INIT_DCS_CMD(0x0F, 0x07), + _INIT_DCS_CMD(0x10, 0x04), + _INIT_DCS_CMD(0x11, 0x08), + _INIT_DCS_CMD(0x12, 0x05), + _INIT_DCS_CMD(0x13, 0x09), + _INIT_DCS_CMD(0x14, 0x05), + _INIT_DCS_CMD(0x15, 0x0A), + _INIT_DCS_CMD(0x16, 0x06), + _INIT_DCS_CMD(0x17, 0x0B), + _INIT_DCS_CMD(0x18, 0x05), + _INIT_DCS_CMD(0x19, 0x0C), + _INIT_DCS_CMD(0x1A, 0x06), + _INIT_DCS_CMD(0x1B, 0x0D), + _INIT_DCS_CMD(0x1C, 0x06), + _INIT_DCS_CMD(0x1D, 0x0E), + _INIT_DCS_CMD(0x1E, 0x07), + _INIT_DCS_CMD(0x1F, 0x0F), + _INIT_DCS_CMD(0x20, 0x06), + _INIT_DCS_CMD(0x21, 0x10), + _INIT_DCS_CMD(0x22, 0x07), + _INIT_DCS_CMD(0x23, 0x11), + _INIT_DCS_CMD(0x24, 0x07), + _INIT_DCS_CMD(0x25, 0x12), + _INIT_DCS_CMD(0x26, 0x08), + _INIT_DCS_CMD(0x27, 0x13), + _INIT_DCS_CMD(0x28, 0x07), + _INIT_DCS_CMD(0x29, 0x14), + _INIT_DCS_CMD(0x2A, 0x08), + _INIT_DCS_CMD(0x2B, 0x15), + _INIT_DCS_CMD(0x2C, 0x08), + _INIT_DCS_CMD(0x2D, 0x16), + _INIT_DCS_CMD(0x2E, 0x09), + _INIT_DCS_CMD(0x2F, 0x17), + _INIT_DCS_CMD(0x30, 0x08), + _INIT_DCS_CMD(0x31, 0x18), + _INIT_DCS_CMD(0x32, 0x09), + _INIT_DCS_CMD(0x33, 0x19), + _INIT_DCS_CMD(0x34, 0x09), + _INIT_DCS_CMD(0x35, 0x1A), + _INIT_DCS_CMD(0x36, 0x0A), + _INIT_DCS_CMD(0x37, 0x1B), + _INIT_DCS_CMD(0x38, 0x0A), + _INIT_DCS_CMD(0x39, 0x1C), + _INIT_DCS_CMD(0x3A, 0x0A), + _INIT_DCS_CMD(0x3B, 0x1D), + _INIT_DCS_CMD(0x3C, 0x0A), + _INIT_DCS_CMD(0x3D, 0x1E), + _INIT_DCS_CMD(0x3E, 0x0A), + _INIT_DCS_CMD(0x3F, 0x1F), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x04), + _INIT_DCS_CMD(0xBA, 0x01), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0E), + _INIT_DCS_CMD(0x02, 0x0C), + _INIT_DCS_CMD(0x20, 0x10), + _INIT_DCS_CMD(0x25, 0x16), + _INIT_DCS_CMD(0x26, 0xE0), + _INIT_DCS_CMD(0x27, 0x00), + _INIT_DCS_CMD(0x29, 0x71), + _INIT_DCS_CMD(0x2A, 0x46), + _INIT_DCS_CMD(0x2B, 0x1F), + _INIT_DCS_CMD(0x2D, 0xC7), + _INIT_DCS_CMD(0x31, 0x02), + _INIT_DCS_CMD(0x32, 0xDF), + _INIT_DCS_CMD(0x33, 0x5A), + _INIT_DCS_CMD(0x34, 0xC0), + _INIT_DCS_CMD(0x35, 0x5A), + _INIT_DCS_CMD(0x36, 0xC0), + _INIT_DCS_CMD(0x38, 0x65), + _INIT_DCS_CMD(0x80, 0x3E), + _INIT_DCS_CMD(0x81, 0xA0), + _INIT_DCS_CMD(0xB0, 0x01), + _INIT_DCS_CMD(0xB1, 0xCC), + _INIT_DCS_CMD(0xC0, 0x12), + _INIT_DCS_CMD(0xC2, 0xCC), + _INIT_DCS_CMD(0xC3, 0xCC), + _INIT_DCS_CMD(0xC4, 0xCC), + _INIT_DCS_CMD(0xC5, 0xCC), + _INIT_DCS_CMD(0xC6, 0xCC), + _INIT_DCS_CMD(0xC7, 0xCC), + _INIT_DCS_CMD(0xC8, 0xCC), + _INIT_DCS_CMD(0xC9, 0xCC), + _INIT_DCS_CMD(0x30, 0x00), + _INIT_DCS_CMD(0x00, 0x81), + _INIT_DCS_CMD(0x08, 0x02), + _INIT_DCS_CMD(0x09, 0x00), + _INIT_DCS_CMD(0x07, 0x21), + _INIT_DCS_CMD(0x04, 0x10), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x1E), + _INIT_DCS_CMD(0x60, 0x00), + _INIT_DCS_CMD(0x64, 0x00), + _INIT_DCS_CMD(0x6D, 0x00), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x0B), + _INIT_DCS_CMD(0xA6, 0x44), + _INIT_DCS_CMD(0xA7, 0xB6), + _INIT_DCS_CMD(0xA8, 0x03), + _INIT_DCS_CMD(0xA9, 0x03), + _INIT_DCS_CMD(0xAA, 0x51), + _INIT_DCS_CMD(0xAB, 0x51), + _INIT_DCS_CMD(0xAC, 0x04), + _INIT_DCS_CMD(0xBD, 0x92), + _INIT_DCS_CMD(0xBE, 0xA1), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x05), + _INIT_DCS_CMD(0x86, 0x87), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x06), + _INIT_DCS_CMD(0x92, 0x22), + + _INIT_DCS_CMD(0xFF, 0x98, 0x82, 0x00), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(120), + _INIT_DCS_CMD(0x29), + _INIT_DELAY_CMD(20), + {}, +}; + static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) { return container_of(panel, struct boe_panel, base); @@ -1795,6 +2135,34 @@ static const struct panel_desc starry_himax83102_j02= _desc =3D { .lp11_before_reset =3D true, }; =20 +static const struct drm_display_mode starry_ili9882t_default_mode =3D { + .clock =3D 165280, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 32, + .hsync_end =3D 1200 + 32 + 30, + .htotal =3D 1200 + 32 + 30 + 32, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 68, + .vsync_end =3D 1920 + 68 + 2, + .vtotal =3D 1920 + 68 + 2 + 10, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct panel_desc starry_ili9882t_desc =3D { + .modes =3D &starry_ili9882t_default_mode, + .bpc =3D 8, + .size =3D { + .width_mm =3D 141, + .height_mm =3D 226, + }, + .lanes =3D 4, + .format =3D MIPI_DSI_FMT_RGB888, + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds =3D starry_ili9882t_init_cmd, + .lp11_before_reset =3D true, +}; + static int boe_panel_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -1971,6 +2339,9 @@ static const struct of_device_id boe_of_match[] =3D { { .compatible =3D "starry,himax83102-j02", .data =3D &starry_himax83102_j02_desc }, + { .compatible =3D "starry,ili9882t", + .data =3D &starry_ili9882t_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_of_match); --=20 2.25.1