From nobody Mon Feb 9 10:32:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B65D6C77B7A for ; Wed, 24 May 2023 22:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235933AbjEXWUX (ORCPT ); Wed, 24 May 2023 18:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236940AbjEXWTq (ORCPT ); Wed, 24 May 2023 18:19:46 -0400 Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFBCBE4C for ; Wed, 24 May 2023 15:19:23 -0700 (PDT) Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5618857518dso17132357b3.2 for ; Wed, 24 May 2023 15:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1684966757; x=1687558757; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :from:to:cc:subject:date:message-id:reply-to; bh=cjAbWq1xZ7aD31R1h5+Cy8ZSDZyyIBasEI10DVMtL4M=; b=p0AhpgXvZl8O7RhTTMtAr534BDXoiK4d/HxTufbtoGDKujmUAJho6GTXP8kd6FAbKl HVIdVGezNvfTcmbLbZIj2zZRsM4FsEy6iN6IWt+evEgx8S8XI1x1ZtfRltJRmPu30hd2 kkIFB/josxZHZWjTz//UdEi3TZqb4OnOn0EaVu0FhPE27c1gkvWp2B//EcHGDg8e3ThF 18xvAzudf0X9+XnMuE1fC9PiNi2n3flAM7q+czmWCENi/N7vYvEuMdKO9wSmKo2uIPTt qNVxvbOW/fw4VVdd7cR50euAcg7TmYSqKPksPwCwGrzvRiekbPTPwzxLgP+w+CclTopP dvhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684966757; x=1687558757; h=to:from:subject:references:mime-version:message-id:in-reply-to:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cjAbWq1xZ7aD31R1h5+Cy8ZSDZyyIBasEI10DVMtL4M=; b=B2HEvVF87SugB0tv7E2PhWcd17qGCHZ9L8AYF16C9gyndUrmE1HPhwKxhzl6/ukSCv YjQShixkD2ih7MpWYiUDp37iDVGREhMfKPqn/fHs3jvqy6y48H7goAcl3s0sUQVi9fiO +8g4eWF0YKiGl+2f8a/fW0VNnleoAOSgjRQRWlLspoWxeHPLwP3Z8a43MTSryWd8hZpA ie0A35+pkNqGfCoJ6ai1hecTY8QPb6YHXk00WDtwiYOMWu50IxiSb2Z5DYkysibGAhjG U23VZh4E5rxXHlcZ/qiFWAqUWmT/qa4QnpGekDarIO02gvzVhJWFPfkkWaFYIEZya01b v55Q== X-Gm-Message-State: AC+VfDy4CcXXXSSfLnPFoSYVvuBVTDd7IE8J+QUohE//1oT2TCEixfBX fHbgCDTpWG+6V+N5xPWhb1wiyaY6qghE X-Google-Smtp-Source: ACHHUZ7A/zgz61i+jDQae5egqZTZUd2asN0Lc32kLdqF4kB08b2NQcqeXPmsMs8FXQsh8XavrY8B6mFmujRA X-Received: from irogers.svl.corp.google.com ([2620:15c:2d4:203:7aa7:3d2d:76ae:8e96]) (user=irogers job=sendgmr) by 2002:a81:a749:0:b0:565:51b:c6f0 with SMTP id e70-20020a81a749000000b00565051bc6f0mr7187150ywh.6.1684966757019; Wed, 24 May 2023 15:19:17 -0700 (PDT) Date: Wed, 24 May 2023 15:18:14 -0700 In-Reply-To: <20230524221831.1741381-1-irogers@google.com> Message-Id: <20230524221831.1741381-19-irogers@google.com> Mime-Version: 1.0 References: <20230524221831.1741381-1-irogers@google.com> X-Mailer: git-send-email 2.40.1.698.g37aff9b760-goog Subject: [PATCH v3 18/35] perf x86: Iterate hybrid PMUs as core PMUs From: Ian Rogers To: Suzuki K Poulose , Mike Leach , Leo Yan , John Garry , Will Deacon , James Clark , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Kajol Jain , Jing Zhang , Kan Liang , Zhengjun Xing , Ravi Bangoria , Madhavan Srinivasan , Athira Rajeev , Ming Wang , Huacai Chen , Sandipan Das , Dmitrii Dolgov <9erthalion6@gmail.com>, Sean Christopherson , Ali Saidi , Rob Herring , Thomas Richter , Kang Minchul , linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rather than iterating over a separate hybrid list, iterate all PMUs with the hybrid ones having is_core as true. Signed-off-by: Ian Rogers --- tools/perf/arch/x86/tests/hybrid.c | 2 +- tools/perf/arch/x86/util/evlist.c | 25 +++++++++++++++++-------- tools/perf/arch/x86/util/perf_regs.c | 14 ++++++++++---- 3 files changed, 28 insertions(+), 13 deletions(-) diff --git a/tools/perf/arch/x86/tests/hybrid.c b/tools/perf/arch/x86/tests= /hybrid.c index 941a9edfed4e..944bd1b4bab6 100644 --- a/tools/perf/arch/x86/tests/hybrid.c +++ b/tools/perf/arch/x86/tests/hybrid.c @@ -3,7 +3,7 @@ #include "debug.h" #include "evlist.h" #include "evsel.h" -#include "pmu-hybrid.h" +#include "pmu.h" #include "tests/tests.h" =20 static bool test_config(const struct evsel *evsel, __u64 expected_config) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index 1b6065841fb0..03f7eb4cf0a4 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -4,7 +4,6 @@ #include "util/evlist.h" #include "util/parse-events.h" #include "util/event.h" -#include "util/pmu-hybrid.h" #include "topdown.h" #include "evsel.h" =20 @@ -12,9 +11,6 @@ static int ___evlist__add_default_attrs(struct evlist *ev= list, struct perf_event_attr *attrs, size_t nr_attrs) { - struct perf_cpu_map *cpus; - struct evsel *evsel, *n; - struct perf_pmu *pmu; LIST_HEAD(head); size_t i =3D 0; =20 @@ -25,15 +21,24 @@ static int ___evlist__add_default_attrs(struct evlist *= evlist, return evlist__add_attrs(evlist, attrs, nr_attrs); =20 for (i =3D 0; i < nr_attrs; i++) { + struct perf_pmu *pmu =3D NULL; + if (attrs[i].type =3D=3D PERF_TYPE_SOFTWARE) { - evsel =3D evsel__new(attrs + i); + struct evsel *evsel =3D evsel__new(attrs + i); + if (evsel =3D=3D NULL) goto out_delete_partial_list; list_add_tail(&evsel->core.node, &head); continue; } =20 - perf_pmu__for_each_hybrid_pmu(pmu) { + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + struct perf_cpu_map *cpus; + struct evsel *evsel; + + if (!pmu->is_core) + continue; + evsel =3D evsel__new(attrs + i); if (evsel =3D=3D NULL) goto out_delete_partial_list; @@ -51,8 +56,12 @@ static int ___evlist__add_default_attrs(struct evlist *e= vlist, return 0; =20 out_delete_partial_list: - __evlist__for_each_entry_safe(&head, n, evsel) - evsel__delete(evsel); + { + struct evsel *evsel, *n; + + __evlist__for_each_entry_safe(&head, n, evsel) + evsel__delete(evsel); + } return -1; } =20 diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/uti= l/perf_regs.c index 0ed177991ad0..26abc159fc0e 100644 --- a/tools/perf/arch/x86/util/perf_regs.c +++ b/tools/perf/arch/x86/util/perf_regs.c @@ -10,7 +10,6 @@ #include "../../../util/debug.h" #include "../../../util/event.h" #include "../../../util/pmu.h" -#include "../../../util/pmu-hybrid.h" =20 const struct sample_reg sample_reg_masks[] =3D { SMPL_REG(AX, PERF_REG_X86_AX), @@ -286,7 +285,6 @@ uint64_t arch__intr_reg_mask(void) .disabled =3D 1, .exclude_kernel =3D 1, }; - struct perf_pmu *pmu; int fd; /* * In an unnamed union, init it here to build on older gcc versions @@ -294,12 +292,20 @@ uint64_t arch__intr_reg_mask(void) attr.sample_period =3D 1; =20 if (perf_pmu__has_hybrid()) { + struct perf_pmu *pmu =3D NULL; + __u64 type =3D PERF_TYPE_RAW; + /* * The same register set is supported among different hybrid PMUs. * Only check the first available one. */ - pmu =3D list_first_entry(&perf_pmu__hybrid_pmus, typeof(*pmu), hybrid_li= st); - attr.config |=3D (__u64)pmu->type << PERF_PMU_TYPE_SHIFT; + while ((pmu =3D perf_pmu__scan(pmu)) !=3D NULL) { + if (pmu->is_core) { + type =3D pmu->type; + break; + } + } + attr.config |=3D type << PERF_PMU_TYPE_SHIFT; } =20 event_attr_init(&attr); --=20 2.40.1.698.g37aff9b760-goog