From nobody Fri Sep 20 19:15:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0D06C7EE2D for ; Wed, 24 May 2023 13:35:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234211AbjEXNfA (ORCPT ); Wed, 24 May 2023 09:35:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234734AbjEXNe4 (ORCPT ); Wed, 24 May 2023 09:34:56 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F837A7; Wed, 24 May 2023 06:34:54 -0700 (PDT) X-UUID: c02dceaefa3711ed9cb5633481061a41-20230524 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=fR5zPRr6mGaPjBEV+8bAJ+j1tXb4IEd8qsOXLOLPyjY=; b=t14xnmyJBfXUcJ2Bn8YDV08Xtm/wnbQIZT2/tq3OTW3tf09QYb8IfKAImyc0U2XZVJ2DIXV8wnHt6tKkOM23YMSoSlHku6vz2228I9oV0PE2X7zqiye20MQCxVsisRaamZ2QjJBjyytXWQE0Dm91see3P5RBdrHluDj2uZp9b9U=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25,REQID:aabe1478-dc68-42c2-978a-0beeccb32eba,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.25,REQID:aabe1478-dc68-42c2-978a-0beeccb32eba,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:d5b0ae3,CLOUDID:dec43a3c-de1e-4348-bc35-c96f92f1dcbb,B ulkID:2305242134504IWJZQOY,BulkQuantity:0,Recheck:0,SF:28|17|19|48|38|29,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-UUID: c02dceaefa3711ed9cb5633481061a41-20230524 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 899007656; Wed, 24 May 2023 21:34:47 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 24 May 2023 21:34:46 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 24 May 2023 21:34:45 +0800 From: Runyang Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Runyang Chen Subject: [PATCH v3 1/2] dt-bindings: reset: mt8188: add thermal reset control bit Date: Wed, 24 May 2023 21:34:38 +0800 Message-ID: <20230524133439.20659-2-runyang.chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20230524133439.20659-1-runyang.chen@mediatek.com> References: <20230524133439.20659-1-runyang.chen@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To support reset of infra_ao, add the index of infra_ao reset of thermal for MT8188. Signed-off-by: Runyang Chen Acked-by: Conor Dooley --- include/dt-bindings/reset/mt8188-resets.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-binding= s/reset/mt8188-resets.h index 377cdfda82a9..ba9a5e9b8899 100644 --- a/include/dt-bindings/reset/mt8188-resets.h +++ b/include/dt-bindings/reset/mt8188-resets.h @@ -33,4 +33,9 @@ =20 #define MT8188_TOPRGU_SW_RST_NUM 24 =20 +/* INFRA resets */ +#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 +#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 +#define MT8188_INFRA_RST3_PTP_CTRL_RST 2 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ --=20 2.18.0 From nobody Fri Sep 20 19:15:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59B26C77B73 for ; Wed, 24 May 2023 13:35:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234989AbjEXNfE (ORCPT ); Wed, 24 May 2023 09:35:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234687AbjEXNe4 (ORCPT ); Wed, 24 May 2023 09:34:56 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD711A9; Wed, 24 May 2023 06:34:53 -0700 (PDT) X-UUID: c1642426fa3711edb20a276fd37b9834-20230524 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=M2a6rGpawYtAjbZDZaYZUA6WdMNG+Ygqo1pPcfyzz00=; b=PSf+wVWeL56hZv0l9Co/Bof7OZN/mXd5xwNPkjJLpJUFWGMXRlPmn1wEEH/pieIzd3PMhGndUe7ht1R+0VyKoHIaYCJdor7XdImZSRmlpmpLJoCJRJjhbMVSyPb1+GSz4aDpGKchRD6Wf972Fywk4FqAgLPKcSK0tQbTowduYU4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.25,REQID:9fdd8688-ef9f-4a5b-bfc5-3f4abd4a81e3,IP:0,U RL:0,TC:0,Content:-5,EDM:-30,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:-35 X-CID-META: VersionHash:d5b0ae3,CLOUDID:fa1ce7c1-e32c-4c97-918d-fbb3fc224d4e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:2,IP:nil,UR L:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: c1642426fa3711edb20a276fd37b9834-20230524 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 915258689; Wed, 24 May 2023 21:34:49 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 24 May 2023 21:34:48 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 24 May 2023 21:34:47 +0800 From: Runyang Chen To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski CC: , , , , , Runyang Chen Subject: [PATCH v3 2/2] clk: mediatek: reset: add infra_ao reset support for MT8188 Date: Wed, 24 May 2023 21:34:39 +0800 Message-ID: <20230524133439.20659-3-runyang.chen@mediatek.com> X-Mailer: git-send-email 2.9.2 In-Reply-To: <20230524133439.20659-1-runyang.chen@mediatek.com> References: <20230524133439.20659-1-runyang.chen@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The infra_ao reset is needed for MT8188. - Add mtk_clk_rst_desc for MT8188. - Add register reset controller function for MT8188 infra_ao. - Add infra_ao_idx_map for MT8188. Signed-off-by: Runyang Chen --- drivers/clk/mediatek/clk-mt8188-infra_ao.c | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8188-infra_ao.c b/drivers/clk/media= tek/clk-mt8188-infra_ao.c index a38ddc7b6a88..bb53e92144c2 100644 --- a/drivers/clk/mediatek/clk-mt8188-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8188-infra_ao.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include =20 @@ -176,9 +177,32 @@ static const struct mtk_gate infra_ao_clks[] =3D { "infra_ao_aes_msdcfde_0p", "top_aes_msdcfde", 18), }; =20 +static const u16 infra_ao_rst_ofs[] =3D { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static const u16 infra_ao_idx_map[] =3D { + [MT8188_INFRA_RST1_THERMAL_MCU_RST] =3D 1 * RST_NR_PER_BANK + 2, + [MT8188_INFRA_RST1_THERMAL_CTRL_RST] =3D 1 * RST_NR_PER_BANK + 4, + [MT8188_INFRA_RST3_PTP_CTRL_RST] =3D 3 * RST_NR_PER_BANK + 5, +}; + +static const struct mtk_clk_rst_desc infra_ao_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D infra_ao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map =3D infra_ao_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), +}; + static const struct mtk_clk_desc infra_ao_desc =3D { .clks =3D infra_ao_clks, .num_clks =3D ARRAY_SIZE(infra_ao_clks), + .rst_desc =3D &infra_ao_rst_desc, }; =20 static const struct of_device_id of_match_clk_mt8188_infra_ao[] =3D { --=20 2.18.0