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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT108.mail.protection.outlook.com (10.13.175.226) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.30 via Frontend Transport; Tue, 23 May 2023 23:25:35 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 23 May 2023 18:25:33 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v4 14/23] cxl/port: Remove Component Register base address from struct cxl_port Date: Tue, 23 May 2023 18:22:05 -0500 Message-ID: <20230523232214.55282-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523232214.55282-1-terry.bowman@amd.com> References: <20230523232214.55282-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT108:EE_|PH0PR12MB5629:EE_ X-MS-Office365-Filtering-Correlation-Id: 112863d9-ecdb-47db-3853-08db5be50324 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 23:25:35.9994 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 112863d9-ecdb-47db-3853-08db5be50324 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5629 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Robert Richter The Component Register base address @component_reg_phys is no longer used after the rework of the Component Register setup which now uses struct member @comp_map instead. Remove the base address. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/port.c | 4 +--- drivers/cxl/cxl.h | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index db2ba0c886e2..183f9f8548e2 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -615,7 +615,6 @@ static int devm_cxl_link_parent_dport(struct device *ho= st, static struct lock_class_key cxl_port_key; =20 static struct cxl_port *cxl_port_alloc(struct device *uport, - resource_size_t component_reg_phys, struct cxl_dport *parent_dport) { struct cxl_port *port; @@ -665,7 +664,6 @@ static struct cxl_port *cxl_port_alloc(struct device *u= port, } else dev->parent =3D uport; =20 - port->component_reg_phys =3D component_reg_phys; ida_init(&port->decoder_ida); port->hdm_end =3D -1; port->commit_end =3D -1; @@ -724,7 +722,7 @@ static struct cxl_port *__devm_cxl_add_port(struct devi= ce *host, struct device *dev; int rc; =20 - port =3D cxl_port_alloc(uport, component_reg_phys, parent_dport); + port =3D cxl_port_alloc(uport, parent_dport); if (IS_ERR(port)) return port; =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index dc83c1d0396e..4365d46606df 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -556,7 +556,6 @@ struct cxl_dax_region { * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing - * @component_reg_phys: component register capability base address (option= al) * @dead: last ep has been removed, force port re-creation * @depth: How deep this port is relative to the root. depth 0 is the root. * @cdat: Cached CDAT data @@ -576,7 +575,6 @@ struct cxl_port { int nr_dports; int hdm_end; int commit_end; - resource_size_t component_reg_phys; bool dead; unsigned int depth; struct cxl_cdat { --=20 2.34.1