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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT023.mail.protection.outlook.com (10.13.175.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.29 via Frontend Transport; Tue, 23 May 2023 23:25:24 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 23 May 2023 18:25:22 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v4 13/23] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Date: Tue, 23 May 2023 18:22:04 -0500 Message-ID: <20230523232214.55282-14-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523232214.55282-1-terry.bowman@amd.com> References: <20230523232214.55282-1-terry.bowman@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT023:EE_|SA1PR12MB8985:EE_ X-MS-Office365-Filtering-Correlation-Id: db8bfbd1-10a9-417c-82ac-08db5be4fbff X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2023 23:25:24.0148 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db8bfbd1-10a9-417c-82ac-08db5be4fbff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8985 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Robert Richter Now, that the Component Register mappings are stored, use them to enable and map the HDM decoder capabilities. The Component Registers do not need to be probed again for this, remove probing code. The HDM capability applies to Endpoints, USPs and VH Host Bridges. The Endpoint's component register mappings are located in the cxlds and else in the port's structure. Provide a helper function cxl_port_get_comp_map() to locate the mappings depending on the component's type. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron --- drivers/cxl/core/hdm.c | 59 +++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 5abfa9276dac..55b5cb4842ae 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -81,26 +81,6 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhd= m) cxlhdm->interleave_mask |=3D GENMASK(14, 12); } =20 -static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb, - struct cxl_component_regs *regs) -{ - struct cxl_register_map map =3D { - .dev =3D &port->dev, - .resource =3D port->component_reg_phys, - .base =3D crb, - .max_size =3D CXL_COMPONENT_REG_BLOCK_SIZE, - }; - - cxl_probe_component_regs(&port->dev, crb, &map.component_map); - if (!map.component_map.hdm_decoder.valid) { - dev_dbg(&port->dev, "HDM decoder registers not implemented\n"); - /* unique error code to indicate no HDM decoder capability */ - return -ENODEV; - } - - return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM)); -} - static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info) { struct cxl_hdm *cxlhdm; @@ -145,6 +125,22 @@ static bool should_emulate_decoders(struct cxl_endpoin= t_dvsec_info *info) return true; } =20 +struct cxl_register_map *cxl_port_get_comp_map(struct cxl_port *port) +{ + /* + * HDM capability applies to Endpoints, USPs and VH Host + * Bridges. The Endpoint's component register mappings are + * located in the cxlds. + */ + if (is_cxl_endpoint(port)) { + struct cxl_memdev *memdev =3D to_cxl_memdev(port->uport); + + return &memdev->cxlds->comp_map; + } + + return &port->comp_map; +} + /** * devm_cxl_setup_hdm - map HDM decoder component registers * @port: cxl_port to map @@ -155,7 +151,7 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *por= t, { struct device *dev =3D &port->dev; struct cxl_hdm *cxlhdm; - void __iomem *crb; + struct cxl_register_map *comp_map; int rc; =20 cxlhdm =3D devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL); @@ -164,19 +160,24 @@ struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *p= ort, cxlhdm->port =3D port; dev_set_drvdata(dev, cxlhdm); =20 - crb =3D ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE); - if (!crb && info && info->mem_enabled) { - cxlhdm->decoder_count =3D info->ranges; - return cxlhdm; - } else if (!crb) { + comp_map =3D cxl_port_get_comp_map(port); + + if (!comp_map->component_map.hdm_decoder.valid) { + dev_dbg(&port->dev, "HDM decoder registers not found\n"); + if (info && info->mem_enabled) { + cxlhdm->decoder_count =3D info->ranges; + return cxlhdm; + } dev_err(dev, "No component registers mapped\n"); return ERR_PTR(-ENXIO); } =20 - rc =3D map_hdm_decoder_regs(port, crb, &cxlhdm->regs); - iounmap(crb); - if (rc) + rc =3D cxl_map_component_regs(comp_map, &cxlhdm->regs, + BIT(CXL_CM_CAP_CAP_ID_HDM)); + if (rc) { + dev_dbg(dev, "Failed to map HDM capability.\n"); return ERR_PTR(rc); + } =20 parse_hdm_decoder_caps(cxlhdm); if (cxlhdm->decoder_count =3D=3D 0) { --=20 2.34.1