From nobody Wed Sep 10 02:05:46 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57437C7EE29 for ; Tue, 23 May 2023 13:54:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236977AbjEWNyf (ORCPT ); Tue, 23 May 2023 09:54:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237014AbjEWNyP (ORCPT ); Tue, 23 May 2023 09:54:15 -0400 Received: from mx.sberdevices.ru (mx.sberdevices.ru [45.89.227.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15C61184; Tue, 23 May 2023 06:54:09 -0700 (PDT) Received: from s-lin-edge02.sberdevices.ru (localhost [127.0.0.1]) by mx.sberdevices.ru (Postfix) with ESMTP id 659985FD64; Tue, 23 May 2023 16:54:07 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sberdevices.ru; s=mail; t=1684850047; bh=JTXLSfOfMPWexmiuFxtk4kxPaMKBebNuJHldS002HmI=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=MZGaFOKnyMpKtVogIjRwOfbG02Fh9cZxhSKoulEasmkWEuXMVgwQZzJu6iceh883M 6VfTTqxJQw0sfM+A+/HvaWcQqsZ2m5yMjMcK+Hq8kqrkS0JPZAp/Xox0EDBIS9/NNW RRZzpi6FH7OtsEBzb3i8Q+1+sSTZIcgiSp370J4YgYsDNr5oNfcHtMcjfQnizgfhHF FqbbKO5QegHCKkg3NFCcm0NvBZcsCrltcqm/J3mU8QxoQrcs8RxUAg0A860EkT4sSm HMGGZfMzHT2tMwsmGXwkGivTPfS1gQNdi6fENvBBrThFTU6THA1BuE7XX6yLgPBF5c 7vZnxkNg/EIHQ== Received: from S-MS-EXCH01.sberdevices.ru (S-MS-EXCH01.sberdevices.ru [172.16.1.4]) by mx.sberdevices.ru (Postfix) with ESMTP; Tue, 23 May 2023 16:54:07 +0300 (MSK) From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v16 6/6] clk: meson: a1: add Amlogic A1 Peripherals clock controller driver Date: Tue, 23 May 2023 16:53:51 +0300 Message-ID: <20230523135351.19133-7-ddrokosov@sberdevices.ru> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20230523135351.19133-1-ddrokosov@sberdevices.ru> References: <20230523135351.19133-1-ddrokosov@sberdevices.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.16.1.6] X-ClientProxiedBy: S-MS-EXCH02.sberdevices.ru (172.16.1.5) To S-MS-EXCH01.sberdevices.ru (172.16.1.4) X-KSMG-Rule-ID: 4 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Status: not scanned, disabled by settings X-KSMG-AntiSpam-Interceptor-Info: not scanned X-KSMG-AntiPhishing: not scanned, disabled by settings X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 1.1.2.30, bases: 2023/05/23 12:15:00 #21372692 X-KSMG-AntiVirus-Status: Clean, skipped Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce Peripherals clock controller for Amlogic A1 SoC family. A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU, and Audio. This patchset adds support for Amlogic A1 Peripherals clock driver and allows to generate clocks for all A1 SoC peripheral IPs. Signed-off-by: Jian Hu Signed-off-by: Dmitry Rokosov Reviewed-by: Martin Blumenstingl --- drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-peripherals.c | 2243 ++++++++++++++++++++++++++++ drivers/clk/meson/a1-peripherals.h | 113 ++ 4 files changed, 2367 insertions(+) create mode 100644 drivers/clk/meson/a1-peripherals.c create mode 100644 drivers/clk/meson/a1-peripherals.h diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 693c4cf60f27..8ce846fdbe43 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -109,6 +109,16 @@ config COMMON_CLK_A1_PLL device, A1 SoC Family. Say Y if you want A1 PLL clock controller to work. =20 +config COMMON_CLK_A1_PERIPHERALS + tristate "Amlogic A1 SoC Peripherals clock controller support" + depends on ARM64 + select COMMON_CLK_MESON_DUALDIV + select COMMON_CLK_MESON_REGMAP + help + Support for the Peripherals clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 Peripherals clock + controller to work. + config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 2f17f475a48f..d5288662881d 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) +=3D vid-pll-d= iv.o obj-$(CONFIG_COMMON_CLK_AXG) +=3D axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) +=3D axg-audio.o obj-$(CONFIG_COMMON_CLK_A1_PLL) +=3D a1-pll.o +obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) +=3D a1-peripherals.o obj-$(CONFIG_COMMON_CLK_GXBB) +=3D gxbb.o gxbb-aoclk.o obj-$(CONFIG_COMMON_CLK_G12A) +=3D g12a.o g12a-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) +=3D meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c new file mode 100644 index 000000000000..b320134fefeb --- /dev/null +++ b/drivers/clk/meson/a1-peripherals.c @@ -0,0 +1,2243 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#include +#include +#include +#include "a1-peripherals.h" +#include "clk-dualdiv.h" +#include "clk-regmap.h" + +static struct clk_regmap xtal_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "xtal_in", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fixpll_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "fixpll_in", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap usb_phy_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 2, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "usb_phy_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap usb_ctrl_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "usb_ctrl_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap hifipll_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 4, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "hifipll_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap syspll_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 5, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "syspll_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap dds_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_OSCIN_CTRL, + .bit_idx =3D 6, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dds_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap rtc_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static const struct meson_clk_dualdiv_param clk_32k_div_table[] =3D { + { + .dual =3D 1, + .n1 =3D 733, + .m1 =3D 8, + .n2 =3D 732, + .m2 =3D 11, + }, + {} +}; + +static struct clk_regmap rtc_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D RTC_BY_OSCIN_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap rtc_32k_xtal =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D RTC_BY_OSCIN_CTRL1, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "rtc_32k_xtal", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap rtc_32k_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D RTC_CTRL, + .mask =3D 0x3, + .shift =3D 0, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc_32k_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_xtal.hw, + &rtc_32k_div.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +struct clk_regmap rtc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D RTC_BY_OSCIN_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "rtc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &rtc_32k_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static u32 mux_table_sys[] =3D { 0, 1, 2, 3, 7 }; +static const struct clk_parent_data sys_parents[] =3D { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div2" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .hw =3D &rtc.hw }, +}; + +static struct clk_regmap sys_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D mux_table_sys, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sys_b_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D sys_parents, + .num_parents =3D ARRAY_SIZE(sys_parents), + }, +}; + +static struct clk_regmap sys_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SYS_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sys_b_div", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sys_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_b", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sys_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D mux_table_sys, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sys_a_sel", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_data =3D sys_parents, + .num_parents =3D ARRAY_SIZE(sys_parents), + }, +}; + +static struct clk_regmap sys_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SYS_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sys_a_div", + .ops =3D &clk_regmap_divider_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sys_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SYS_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sys_a", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sys =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SYS_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 31, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sys", + .ops =3D &clk_regmap_mux_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sys_a.hw, + &sys_b.hw, + }, + .num_parents =3D 2, + /* + * This clock is used by APB bus which is set in boot ROM code + * and is required by the platform to operate correctly. + * Until the following condition are met, we need this clock to + * be marked as critical: + * a) Mark the clock used by a firmware resource, if possible + * b) CCF has a clock hand-off mechanism to make the sure the + * clock stays on until the proper driver comes along + */ + .flags =3D CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +static u32 mux_table_dsp_ab[] =3D { 0, 1, 2, 3, 4, 7 }; +static const struct clk_parent_data dsp_ab_parent_data[] =3D { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div2", }, + { .fw_name =3D "fclk_div3", }, + { .fw_name =3D "fclk_div5", }, + { .fw_name =3D "hifi_pll", }, + { .hw =3D &rtc.hw }, +}; + +static struct clk_regmap dspa_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D mux_table_dsp_ab, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspa_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D mux_table_dsp_ab, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspa_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D DSPA_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPA_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPA_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspa_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_a.hw, + &dspa_b.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPA_CLK_EN, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspa_en_nic =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPA_CLK_EN, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspa_en_nic", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspa_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPB_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 10, + .table =3D mux_table_dsp_ab, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspb_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D DSPB_CLK_CTRL0, + .shift =3D 0, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPB_CLK_CTRL0, + .bit_idx =3D 13, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspb_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPB_CLK_CTRL0, + .mask =3D 0x7, + .shift =3D 26, + .table =3D mux_table_dsp_ab, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D dsp_ab_parent_data, + .num_parents =3D ARRAY_SIZE(dsp_ab_parent_data), + }, +}; + +static struct clk_regmap dspb_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D DSPB_CLK_CTRL0, + .shift =3D 16, + .width =3D 10, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPB_CLK_CTRL0, + .bit_idx =3D 29, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspb_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DSPB_CLK_CTRL0, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dspb_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_a.hw, + &dspb_b.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_en =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPB_CLK_EN, + .bit_idx =3D 1, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspb_en", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dspb_en_nic =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DSPB_CLK_EN, + .bit_idx =3D 0, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dspb_en_nic", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dspb_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap clk_24m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "24m", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_fixed_factor clk_24m_div2 =3D { + .mult =3D 1, + .div =3D 2, + .hw.init =3D &(struct clk_init_data){ + .name =3D "24m_div2", + .ops =3D &clk_fixed_factor_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &clk_24m.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap clk_12m =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 10, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "12m", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &clk_24m_div2.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2_divn_pre =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D CLK12_24_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div2_divn_pre", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "fclk_div2", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap fclk_div2_divn =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLK12_24_CTRL, + .bit_idx =3D 12, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "fclk_div2_divn", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &fclk_div2_divn_pre.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * the index 2 is sys_pll_div16, it will be implemented in the CPU clock d= river, + * the index 4 is the clock measurement source, it's not supported yet + */ +static u32 gen_table[] =3D { 0, 1, 3, 5, 6, 7, 8 }; +static const struct clk_parent_data gen_parent_data[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &rtc.hw }, + { .fw_name =3D "hifi_pll", }, + { .fw_name =3D "fclk_div2", }, + { .fw_name =3D "fclk_div3", }, + { .fw_name =3D "fclk_div5", }, + { .fw_name =3D "fclk_div7", }, +}; + +static struct clk_regmap gen_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D GEN_CLK_CTRL, + .mask =3D 0xf, + .shift =3D 12, + .table =3D gen_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gen_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D gen_parent_data, + .num_parents =3D ARRAY_SIZE(gen_parent_data), + /* + * The GEN clock can be connected to an external pad, so it + * may be set up directly from the device tree. Additionally, + * the GEN clock can be inherited from a more accurate RTC + * clock, so in certain situations, it may be necessary + * to freeze its parent. + */ + .flags =3D CLK_SET_RATE_NO_REPARENT, + }, +}; + +static struct clk_regmap gen_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D GEN_CLK_CTRL, + .shift =3D 0, + .width =3D 11, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "gen_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap gen =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D GEN_CLK_CTRL, + .bit_idx =3D 11, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "gen", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &gen_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap saradc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SAR_ADC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "saradc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .hw =3D &sys.hw, }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap saradc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SAR_ADC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "saradc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap saradc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SAR_ADC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "saradc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &saradc_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_abcd_parents[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &sys.hw }, + { .hw =3D &rtc.hw }, +}; + +static struct clk_regmap pwm_a_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_AB_CTRL, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_a_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + }, +}; + +static struct clk_regmap pwm_a_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_AB_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_a_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_a_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_a =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_AB_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_a", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_a_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_b_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_AB_CTRL, + .mask =3D 0x1, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_b_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + }, +}; + +static struct clk_regmap pwm_b_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_AB_CTRL, + .shift =3D 16, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_b_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_b_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_b =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_AB_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_b", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_b_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_c_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_CD_CTRL, + .mask =3D 0x1, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_c_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + }, +}; + +static struct clk_regmap pwm_c_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_CD_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_c_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_c_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_c =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_CD_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_c", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_c_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_d_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_CD_CTRL, + .mask =3D 0x1, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_d_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_abcd_parents, + .num_parents =3D ARRAY_SIZE(pwm_abcd_parents), + }, +}; + +static struct clk_regmap pwm_d_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_CD_CTRL, + .shift =3D 16, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_d_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_d_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_d =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_CD_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_d", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_d_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data pwm_ef_parents[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &sys.hw }, + { .fw_name =3D "fclk_div5", }, + { .hw =3D &rtc.hw }, +}; + +static struct clk_regmap pwm_e_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_EF_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_e_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_ef_parents, + .num_parents =3D ARRAY_SIZE(pwm_ef_parents), + }, +}; + +static struct clk_regmap pwm_e_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_EF_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_e_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_e_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_e =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_EF_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_e", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_e_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_f_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PWM_CLK_EF_CTRL, + .mask =3D 0x3, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_f_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D pwm_ef_parents, + .num_parents =3D ARRAY_SIZE(pwm_ef_parents), + }, +}; + +static struct clk_regmap pwm_f_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PWM_CLK_EF_CTRL, + .shift =3D 16, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "pwm_f_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_f_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap pwm_f =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PWM_CLK_EF_CTRL, + .bit_idx =3D 24, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "pwm_f", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &pwm_f_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* + * spicc clk + * fdiv2 |\ |\ _____ + * ---------| |---DIV--| | | | spicc out + * ---------| | | |-----|GATE |--------- + * ..... |/ | / |_____| + * --------------------|/ + * 24M + */ +static const struct clk_parent_data spicc_spifc_parents[] =3D { + { .fw_name =3D "fclk_div2"}, + { .fw_name =3D "fclk_div3"}, + { .fw_name =3D "fclk_div5"}, + { .fw_name =3D "hifi_pll" }, +}; + +static struct clk_regmap spicc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SPICC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spicc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_spifc_parents, + .num_parents =3D ARRAY_SIZE(spicc_spifc_parents), + }, +}; + +static struct clk_regmap spicc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SPICC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spicc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc_sel2 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SPICC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spicc_sel2", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &spicc_div.hw }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spicc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SPICC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spicc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spicc_sel2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ts_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D TS_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ts_div", + .ops =3D &clk_regmap_divider_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ts =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D TS_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ts", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ts_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spifc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SPIFC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spifc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D spicc_spifc_parents, + .num_parents =3D ARRAY_SIZE(spicc_spifc_parents), + }, +}; + +static struct clk_regmap spifc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SPIFC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spifc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spifc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spifc_sel2 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SPIFC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "spifc_sel2", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &spifc_div.hw }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap spifc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SPIFC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "spifc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &spifc_sel2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data usb_bus_parents[] =3D { + { .fw_name =3D "xtal", }, + { .hw =3D &sys.hw }, + { .fw_name =3D "fclk_div3", }, + { .fw_name =3D "fclk_div5", }, +}; + +static struct clk_regmap usb_bus_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D USB_BUSCLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "usb_bus_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D usb_bus_parents, + .num_parents =3D ARRAY_SIZE(usb_bus_parents), + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap usb_bus_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D USB_BUSCLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "usb_bus_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &usb_bus_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap usb_bus =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D USB_BUSCLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "usb_bus", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &usb_bus_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_parent_data sd_emmc_psram_dmc_parents[] =3D { + { .fw_name =3D "fclk_div2", }, + { .fw_name =3D "fclk_div3", }, + { .fw_name =3D "fclk_div5", }, + { .fw_name =3D "hifi_pll", }, +}; + +static struct clk_regmap sd_emmc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SD_EMMC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sd_emmc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D sd_emmc_psram_dmc_parents, + .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + }, +}; + +static struct clk_regmap sd_emmc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D SD_EMMC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sd_emmc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc_sel2 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D SD_EMMC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "sd_emmc_sel2", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &sd_emmc_div.hw }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap sd_emmc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D SD_EMMC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "sd_emmc", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &sd_emmc_sel2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap psram_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PSRAM_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "psram_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D sd_emmc_psram_dmc_parents, + .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + }, +}; + +static struct clk_regmap psram_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D PSRAM_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "psram_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &psram_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap psram_sel2 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D PSRAM_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "psram_sel2", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &psram_div.hw }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap psram =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D PSRAM_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "psram", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &psram_sel2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dmc_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DMC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dmc_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D sd_emmc_psram_dmc_parents, + .num_parents =3D ARRAY_SIZE(sd_emmc_psram_dmc_parents), + }, +}; + +static struct clk_regmap dmc_div =3D { + .data =3D &(struct clk_regmap_div_data){ + .offset =3D DMC_CLK_CTRL, + .shift =3D 0, + .width =3D 8, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dmc_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dmc_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dmc_sel2 =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D DMC_CLK_CTRL, + .mask =3D 0x1, + .shift =3D 15, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "dmc_sel2", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .hw =3D &dmc_div.hw }, + { .fw_name =3D "xtal", }, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap dmc =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D DMC_CLK_CTRL, + .bit_idx =3D 8, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "dmc", + .ops =3D &clk_regmap_gate_ro_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &dmc_sel2.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ceca_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECA_CLK_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "ceca_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ceca_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CECA_CLK_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CECA_CLK_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CECA_CLK_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CECA_CLK_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CECA_CLK_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ceca_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap ceca_32k_sel_pre =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECA_CLK_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_32k_sel_pre", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ceca_32k_div.hw, + &ceca_32k_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap ceca_32k_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECA_CLK_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_32k_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ceca_32k_sel_pre.hw, + &rtc.hw, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap ceca_32k_out =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECA_CLK_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "ceca_32k_out", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &ceca_32k_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cecb_32k_in =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECB_CLK_CTRL0, + .bit_idx =3D 31, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cecb_32k_in", + .ops =3D &clk_regmap_gate_ops, + .parent_data =3D &(const struct clk_parent_data) { + .fw_name =3D "xtal", + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap cecb_32k_div =3D { + .data =3D &(struct meson_clk_dualdiv_data){ + .n1 =3D { + .reg_off =3D CECB_CLK_CTRL0, + .shift =3D 0, + .width =3D 12, + }, + .n2 =3D { + .reg_off =3D CECB_CLK_CTRL0, + .shift =3D 12, + .width =3D 12, + }, + .m1 =3D { + .reg_off =3D CECB_CLK_CTRL1, + .shift =3D 0, + .width =3D 12, + }, + .m2 =3D { + .reg_off =3D CECB_CLK_CTRL1, + .shift =3D 12, + .width =3D 12, + }, + .dual =3D { + .reg_off =3D CECB_CLK_CTRL0, + .shift =3D 28, + .width =3D 1, + }, + .table =3D clk_32k_div_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_32k_div", + .ops =3D &meson_clk_dualdiv_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &cecb_32k_in.hw + }, + .num_parents =3D 1, + }, +}; + +static struct clk_regmap cecb_32k_sel_pre =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECB_CLK_CTRL1, + .mask =3D 0x1, + .shift =3D 24, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_32k_sel_pre", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &cecb_32k_div.hw, + &cecb_32k_in.hw, + }, + .num_parents =3D 2, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cecb_32k_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CECB_CLK_CTRL1, + .mask =3D 0x1, + .shift =3D 31, + .flags =3D CLK_MUX_ROUND_CLOSEST, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_32k_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &cecb_32k_sel_pre.hw, + &rtc.hw, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap cecb_32k_out =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CECB_CLK_CTRL0, + .bit_idx =3D 30, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cecb_32k_out", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &cecb_32k_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +#define MESON_GATE(_name, _reg, _bit) \ + MESON_PCLK(_name, _reg, _bit, &sys.hw) + +static MESON_GATE(clktree, SYS_CLK_EN0, 0); +static MESON_GATE(reset_ctrl, SYS_CLK_EN0, 1); +static MESON_GATE(analog_ctrl, SYS_CLK_EN0, 2); +static MESON_GATE(pwr_ctrl, SYS_CLK_EN0, 3); +static MESON_GATE(pad_ctrl, SYS_CLK_EN0, 4); +static MESON_GATE(sys_ctrl, SYS_CLK_EN0, 5); +static MESON_GATE(temp_sensor, SYS_CLK_EN0, 6); +static MESON_GATE(am2axi_dev, SYS_CLK_EN0, 7); +static MESON_GATE(spicc_b, SYS_CLK_EN0, 8); +static MESON_GATE(spicc_a, SYS_CLK_EN0, 9); +static MESON_GATE(msr, SYS_CLK_EN0, 10); +static MESON_GATE(audio, SYS_CLK_EN0, 11); +static MESON_GATE(jtag_ctrl, SYS_CLK_EN0, 12); +static MESON_GATE(saradc_en, SYS_CLK_EN0, 13); +static MESON_GATE(pwm_ef, SYS_CLK_EN0, 14); +static MESON_GATE(pwm_cd, SYS_CLK_EN0, 15); +static MESON_GATE(pwm_ab, SYS_CLK_EN0, 16); +static MESON_GATE(cec, SYS_CLK_EN0, 17); +static MESON_GATE(i2c_s, SYS_CLK_EN0, 18); +static MESON_GATE(ir_ctrl, SYS_CLK_EN0, 19); +static MESON_GATE(i2c_m_d, SYS_CLK_EN0, 20); +static MESON_GATE(i2c_m_c, SYS_CLK_EN0, 21); +static MESON_GATE(i2c_m_b, SYS_CLK_EN0, 22); +static MESON_GATE(i2c_m_a, SYS_CLK_EN0, 23); +static MESON_GATE(acodec, SYS_CLK_EN0, 24); +static MESON_GATE(otp, SYS_CLK_EN0, 25); +static MESON_GATE(sd_emmc_a, SYS_CLK_EN0, 26); +static MESON_GATE(usb_phy, SYS_CLK_EN0, 27); +static MESON_GATE(usb_ctrl, SYS_CLK_EN0, 28); +static MESON_GATE(sys_dspb, SYS_CLK_EN0, 29); +static MESON_GATE(sys_dspa, SYS_CLK_EN0, 30); +static MESON_GATE(dma, SYS_CLK_EN0, 31); +static MESON_GATE(irq_ctrl, SYS_CLK_EN1, 0); +static MESON_GATE(nic, SYS_CLK_EN1, 1); +static MESON_GATE(gic, SYS_CLK_EN1, 2); +static MESON_GATE(uart_c, SYS_CLK_EN1, 3); +static MESON_GATE(uart_b, SYS_CLK_EN1, 4); +static MESON_GATE(uart_a, SYS_CLK_EN1, 5); +static MESON_GATE(sys_psram, SYS_CLK_EN1, 6); +static MESON_GATE(rsa, SYS_CLK_EN1, 8); +static MESON_GATE(coresight, SYS_CLK_EN1, 9); +static MESON_GATE(am2axi_vad, AXI_CLK_EN, 0); +static MESON_GATE(audio_vad, AXI_CLK_EN, 1); +static MESON_GATE(axi_dmc, AXI_CLK_EN, 3); +static MESON_GATE(axi_psram, AXI_CLK_EN, 4); +static MESON_GATE(ramb, AXI_CLK_EN, 5); +static MESON_GATE(rama, AXI_CLK_EN, 6); +static MESON_GATE(axi_spifc, AXI_CLK_EN, 7); +static MESON_GATE(axi_nic, AXI_CLK_EN, 8); +static MESON_GATE(axi_dma, AXI_CLK_EN, 9); +static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10); +static MESON_GATE(rom, AXI_CLK_EN, 11); +static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); + +/* Array of all clocks registered by this provider */ +static struct clk_hw_onecell_data a1_periphs_clks =3D { + .hws =3D { + [CLKID_XTAL_IN] =3D &xtal_in.hw, + [CLKID_FIXPLL_IN] =3D &fixpll_in.hw, + [CLKID_USB_PHY_IN] =3D &usb_phy_in.hw, + [CLKID_USB_CTRL_IN] =3D &usb_ctrl_in.hw, + [CLKID_HIFIPLL_IN] =3D &hifipll_in.hw, + [CLKID_SYSPLL_IN] =3D &syspll_in.hw, + [CLKID_DDS_IN] =3D &dds_in.hw, + [CLKID_SYS] =3D &sys.hw, + [CLKID_CLKTREE] =3D &clktree.hw, + [CLKID_RESET_CTRL] =3D &reset_ctrl.hw, + [CLKID_ANALOG_CTRL] =3D &analog_ctrl.hw, + [CLKID_PWR_CTRL] =3D &pwr_ctrl.hw, + [CLKID_PAD_CTRL] =3D &pad_ctrl.hw, + [CLKID_SYS_CTRL] =3D &sys_ctrl.hw, + [CLKID_TEMP_SENSOR] =3D &temp_sensor.hw, + [CLKID_AM2AXI_DIV] =3D &am2axi_dev.hw, + [CLKID_SPICC_B] =3D &spicc_b.hw, + [CLKID_SPICC_A] =3D &spicc_a.hw, + [CLKID_MSR] =3D &msr.hw, + [CLKID_AUDIO] =3D &audio.hw, + [CLKID_JTAG_CTRL] =3D &jtag_ctrl.hw, + [CLKID_SARADC_EN] =3D &saradc_en.hw, + [CLKID_PWM_EF] =3D &pwm_ef.hw, + [CLKID_PWM_CD] =3D &pwm_cd.hw, + [CLKID_PWM_AB] =3D &pwm_ab.hw, + [CLKID_CEC] =3D &cec.hw, + [CLKID_I2C_S] =3D &i2c_s.hw, + [CLKID_IR_CTRL] =3D &ir_ctrl.hw, + [CLKID_I2C_M_D] =3D &i2c_m_d.hw, + [CLKID_I2C_M_C] =3D &i2c_m_c.hw, + [CLKID_I2C_M_B] =3D &i2c_m_b.hw, + [CLKID_I2C_M_A] =3D &i2c_m_a.hw, + [CLKID_ACODEC] =3D &acodec.hw, + [CLKID_OTP] =3D &otp.hw, + [CLKID_SD_EMMC_A] =3D &sd_emmc_a.hw, + [CLKID_USB_PHY] =3D &usb_phy.hw, + [CLKID_USB_CTRL] =3D &usb_ctrl.hw, + [CLKID_SYS_DSPB] =3D &sys_dspb.hw, + [CLKID_SYS_DSPA] =3D &sys_dspa.hw, + [CLKID_DMA] =3D &dma.hw, + [CLKID_IRQ_CTRL] =3D &irq_ctrl.hw, + [CLKID_NIC] =3D &nic.hw, + [CLKID_GIC] =3D &gic.hw, + [CLKID_UART_C] =3D &uart_c.hw, + [CLKID_UART_B] =3D &uart_b.hw, + [CLKID_UART_A] =3D &uart_a.hw, + [CLKID_SYS_PSRAM] =3D &sys_psram.hw, + [CLKID_RSA] =3D &rsa.hw, + [CLKID_CORESIGHT] =3D &coresight.hw, + [CLKID_AM2AXI_VAD] =3D &am2axi_vad.hw, + [CLKID_AUDIO_VAD] =3D &audio_vad.hw, + [CLKID_AXI_DMC] =3D &axi_dmc.hw, + [CLKID_AXI_PSRAM] =3D &axi_psram.hw, + [CLKID_RAMB] =3D &ramb.hw, + [CLKID_RAMA] =3D &rama.hw, + [CLKID_AXI_SPIFC] =3D &axi_spifc.hw, + [CLKID_AXI_NIC] =3D &axi_nic.hw, + [CLKID_AXI_DMA] =3D &axi_dma.hw, + [CLKID_CPU_CTRL] =3D &cpu_ctrl.hw, + [CLKID_ROM] =3D &rom.hw, + [CLKID_PROC_I2C] =3D &prod_i2c.hw, + [CLKID_DSPA_SEL] =3D &dspa_sel.hw, + [CLKID_DSPB_SEL] =3D &dspb_sel.hw, + [CLKID_DSPA_EN] =3D &dspa_en.hw, + [CLKID_DSPA_EN_NIC] =3D &dspa_en_nic.hw, + [CLKID_DSPB_EN] =3D &dspb_en.hw, + [CLKID_DSPB_EN_NIC] =3D &dspb_en_nic.hw, + [CLKID_RTC] =3D &rtc.hw, + [CLKID_CECA_32K] =3D &ceca_32k_out.hw, + [CLKID_CECB_32K] =3D &cecb_32k_out.hw, + [CLKID_24M] =3D &clk_24m.hw, + [CLKID_12M] =3D &clk_12m.hw, + [CLKID_FCLK_DIV2_DIVN] =3D &fclk_div2_divn.hw, + [CLKID_GEN] =3D &gen.hw, + [CLKID_SARADC_SEL] =3D &saradc_sel.hw, + [CLKID_SARADC] =3D &saradc.hw, + [CLKID_PWM_A] =3D &pwm_a.hw, + [CLKID_PWM_B] =3D &pwm_b.hw, + [CLKID_PWM_C] =3D &pwm_c.hw, + [CLKID_PWM_D] =3D &pwm_d.hw, + [CLKID_PWM_E] =3D &pwm_e.hw, + [CLKID_PWM_F] =3D &pwm_f.hw, + [CLKID_SPICC] =3D &spicc.hw, + [CLKID_TS] =3D &ts.hw, + [CLKID_SPIFC] =3D &spifc.hw, + [CLKID_USB_BUS] =3D &usb_bus.hw, + [CLKID_SD_EMMC] =3D &sd_emmc.hw, + [CLKID_PSRAM] =3D &psram.hw, + [CLKID_DMC] =3D &dmc.hw, + [CLKID_SYS_A_SEL] =3D &sys_a_sel.hw, + [CLKID_SYS_A_DIV] =3D &sys_a_div.hw, + [CLKID_SYS_A] =3D &sys_a.hw, + [CLKID_SYS_B_SEL] =3D &sys_b_sel.hw, + [CLKID_SYS_B_DIV] =3D &sys_b_div.hw, + [CLKID_SYS_B] =3D &sys_b.hw, + [CLKID_DSPA_A_SEL] =3D &dspa_a_sel.hw, + [CLKID_DSPA_A_DIV] =3D &dspa_a_div.hw, + [CLKID_DSPA_A] =3D &dspa_a.hw, + [CLKID_DSPA_B_SEL] =3D &dspa_b_sel.hw, + [CLKID_DSPA_B_DIV] =3D &dspa_b_div.hw, + [CLKID_DSPA_B] =3D &dspa_b.hw, + [CLKID_DSPB_A_SEL] =3D &dspb_a_sel.hw, + [CLKID_DSPB_A_DIV] =3D &dspb_a_div.hw, + [CLKID_DSPB_A] =3D &dspb_a.hw, + [CLKID_DSPB_B_SEL] =3D &dspb_b_sel.hw, + [CLKID_DSPB_B_DIV] =3D &dspb_b_div.hw, + [CLKID_DSPB_B] =3D &dspb_b.hw, + [CLKID_RTC_32K_IN] =3D &rtc_32k_in.hw, + [CLKID_RTC_32K_DIV] =3D &rtc_32k_div.hw, + [CLKID_RTC_32K_XTAL] =3D &rtc_32k_xtal.hw, + [CLKID_RTC_32K_SEL] =3D &rtc_32k_sel.hw, + [CLKID_CECB_32K_IN] =3D &cecb_32k_in.hw, + [CLKID_CECB_32K_DIV] =3D &cecb_32k_div.hw, + [CLKID_CECB_32K_SEL_PRE] =3D &cecb_32k_sel_pre.hw, + [CLKID_CECB_32K_SEL] =3D &cecb_32k_sel.hw, + [CLKID_CECA_32K_IN] =3D &ceca_32k_in.hw, + [CLKID_CECA_32K_DIV] =3D &ceca_32k_div.hw, + [CLKID_CECA_32K_SEL_PRE] =3D &ceca_32k_sel_pre.hw, + [CLKID_CECA_32K_SEL] =3D &ceca_32k_sel.hw, + [CLKID_DIV2_PRE] =3D &fclk_div2_divn_pre.hw, + [CLKID_24M_DIV2] =3D &clk_24m_div2.hw, + [CLKID_GEN_SEL] =3D &gen_sel.hw, + [CLKID_GEN_DIV] =3D &gen_div.hw, + [CLKID_SARADC_DIV] =3D &saradc_div.hw, + [CLKID_PWM_A_SEL] =3D &pwm_a_sel.hw, + [CLKID_PWM_A_DIV] =3D &pwm_a_div.hw, + [CLKID_PWM_B_SEL] =3D &pwm_b_sel.hw, + [CLKID_PWM_B_DIV] =3D &pwm_b_div.hw, + [CLKID_PWM_C_SEL] =3D &pwm_c_sel.hw, + [CLKID_PWM_C_DIV] =3D &pwm_c_div.hw, + [CLKID_PWM_D_SEL] =3D &pwm_d_sel.hw, + [CLKID_PWM_D_DIV] =3D &pwm_d_div.hw, + [CLKID_PWM_E_SEL] =3D &pwm_e_sel.hw, + [CLKID_PWM_E_DIV] =3D &pwm_e_div.hw, + [CLKID_PWM_F_SEL] =3D &pwm_f_sel.hw, + [CLKID_PWM_F_DIV] =3D &pwm_f_div.hw, + [CLKID_SPICC_SEL] =3D &spicc_sel.hw, + [CLKID_SPICC_DIV] =3D &spicc_div.hw, + [CLKID_SPICC_SEL2] =3D &spicc_sel2.hw, + [CLKID_TS_DIV] =3D &ts_div.hw, + [CLKID_SPIFC_SEL] =3D &spifc_sel.hw, + [CLKID_SPIFC_DIV] =3D &spifc_div.hw, + [CLKID_SPIFC_SEL2] =3D &spifc_sel2.hw, + [CLKID_USB_BUS_SEL] =3D &usb_bus_sel.hw, + [CLKID_USB_BUS_DIV] =3D &usb_bus_div.hw, + [CLKID_SD_EMMC_SEL] =3D &sd_emmc_sel.hw, + [CLKID_SD_EMMC_DIV] =3D &sd_emmc_div.hw, + [CLKID_SD_EMMC_SEL2] =3D &sd_emmc_sel2.hw, + [CLKID_PSRAM_SEL] =3D &psram_sel.hw, + [CLKID_PSRAM_DIV] =3D &psram_div.hw, + [CLKID_PSRAM_SEL2] =3D &psram_sel2.hw, + [CLKID_DMC_SEL] =3D &dmc_sel.hw, + [CLKID_DMC_DIV] =3D &dmc_div.hw, + [CLKID_DMC_SEL2] =3D &dmc_sel2.hw, + [NR_CLKS] =3D NULL, + }, + .num =3D NR_CLKS, +}; + +/* Convenience table to populate regmap in .probe */ +static struct clk_regmap *const a1_periphs_regmaps[] =3D { + &xtal_in, + &fixpll_in, + &usb_phy_in, + &usb_ctrl_in, + &hifipll_in, + &syspll_in, + &dds_in, + &sys, + &clktree, + &reset_ctrl, + &analog_ctrl, + &pwr_ctrl, + &pad_ctrl, + &sys_ctrl, + &temp_sensor, + &am2axi_dev, + &spicc_b, + &spicc_a, + &msr, + &audio, + &jtag_ctrl, + &saradc_en, + &pwm_ef, + &pwm_cd, + &pwm_ab, + &cec, + &i2c_s, + &ir_ctrl, + &i2c_m_d, + &i2c_m_c, + &i2c_m_b, + &i2c_m_a, + &acodec, + &otp, + &sd_emmc_a, + &usb_phy, + &usb_ctrl, + &sys_dspb, + &sys_dspa, + &dma, + &irq_ctrl, + &nic, + &gic, + &uart_c, + &uart_b, + &uart_a, + &sys_psram, + &rsa, + &coresight, + &am2axi_vad, + &audio_vad, + &axi_dmc, + &axi_psram, + &ramb, + &rama, + &axi_spifc, + &axi_nic, + &axi_dma, + &cpu_ctrl, + &rom, + &prod_i2c, + &dspa_sel, + &dspb_sel, + &dspa_en, + &dspa_en_nic, + &dspb_en, + &dspb_en_nic, + &rtc, + &ceca_32k_out, + &cecb_32k_out, + &clk_24m, + &clk_12m, + &fclk_div2_divn, + &gen, + &saradc_sel, + &saradc, + &pwm_a, + &pwm_b, + &pwm_c, + &pwm_d, + &pwm_e, + &pwm_f, + &spicc, + &ts, + &spifc, + &usb_bus, + &sd_emmc, + &psram, + &dmc, + &sys_a_sel, + &sys_a_div, + &sys_a, + &sys_b_sel, + &sys_b_div, + &sys_b, + &dspa_a_sel, + &dspa_a_div, + &dspa_a, + &dspa_b_sel, + &dspa_b_div, + &dspa_b, + &dspb_a_sel, + &dspb_a_div, + &dspb_a, + &dspb_b_sel, + &dspb_b_div, + &dspb_b, + &rtc_32k_in, + &rtc_32k_div, + &rtc_32k_xtal, + &rtc_32k_sel, + &cecb_32k_in, + &cecb_32k_div, + &cecb_32k_sel_pre, + &cecb_32k_sel, + &ceca_32k_in, + &ceca_32k_div, + &ceca_32k_sel_pre, + &ceca_32k_sel, + &fclk_div2_divn_pre, + &gen_sel, + &gen_div, + &saradc_div, + &pwm_a_sel, + &pwm_a_div, + &pwm_b_sel, + &pwm_b_div, + &pwm_c_sel, + &pwm_c_div, + &pwm_d_sel, + &pwm_d_div, + &pwm_e_sel, + &pwm_e_div, + &pwm_f_sel, + &pwm_f_div, + &spicc_sel, + &spicc_div, + &spicc_sel2, + &ts_div, + &spifc_sel, + &spifc_div, + &spifc_sel2, + &usb_bus_sel, + &usb_bus_div, + &sd_emmc_sel, + &sd_emmc_div, + &sd_emmc_sel2, + &psram_sel, + &psram_div, + &psram_sel2, + &dmc_sel, + &dmc_div, + &dmc_sel2, +}; + +static struct regmap_config a1_periphs_regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int meson_a1_periphs_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + void __iomem *base; + struct regmap *map; + int clkid, i, err; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "can't ioremap resource\n"); + + map =3D devm_regmap_init_mmio(dev, base, &a1_periphs_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "can't init regmap mmio region\n"); + + /* Populate regmap for the regmap backed clocks */ + for (i =3D 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) + a1_periphs_regmaps[i]->map =3D map; + + for (clkid =3D 0; clkid < a1_periphs_clks.num; clkid++) { + err =3D devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); + if (err) + return dev_err_probe(dev, err, + "clock[%d] registration failed\n", + clkid); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &a1_periphs_clks); +} + +static const struct of_device_id a1_periphs_clkc_match_table[] =3D { + { .compatible =3D "amlogic,a1-peripherals-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table); + +static struct platform_driver a1_periphs_clkc_driver =3D { + .probe =3D meson_a1_periphs_probe, + .driver =3D { + .name =3D "a1-peripherals-clkc", + .of_match_table =3D a1_periphs_clkc_match_table, + }, +}; + +module_platform_driver(a1_periphs_clkc_driver); +MODULE_AUTHOR("Jian Hu "); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/meson/a1-peripherals.h b/drivers/clk/meson/a1-peri= pherals.h new file mode 100644 index 000000000000..526fc9ba5c9f --- /dev/null +++ b/drivers/clk/meson/a1-peripherals.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Amlogic A1 Peripherals Clock Controller internals + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_PERIPHERALS_H +#define __A1_PERIPHERALS_H + +/* peripherals clock controller register offset */ +#define SYS_OSCIN_CTRL 0x0 +#define RTC_BY_OSCIN_CTRL0 0x4 +#define RTC_BY_OSCIN_CTRL1 0x8 +#define RTC_CTRL 0xc +#define SYS_CLK_CTRL0 0x10 +#define SYS_CLK_EN0 0x1c +#define SYS_CLK_EN1 0x20 +#define AXI_CLK_EN 0x24 +#define DSPA_CLK_EN 0x28 +#define DSPB_CLK_EN 0x2c +#define DSPA_CLK_CTRL0 0x30 +#define DSPB_CLK_CTRL0 0x34 +#define CLK12_24_CTRL 0x38 +#define GEN_CLK_CTRL 0x3c +#define SAR_ADC_CLK_CTRL 0xc0 +#define PWM_CLK_AB_CTRL 0xc4 +#define PWM_CLK_CD_CTRL 0xc8 +#define PWM_CLK_EF_CTRL 0xcc +#define SPICC_CLK_CTRL 0xd0 +#define TS_CLK_CTRL 0xd4 +#define SPIFC_CLK_CTRL 0xd8 +#define USB_BUSCLK_CTRL 0xdc +#define SD_EMMC_CLK_CTRL 0xe0 +#define CECA_CLK_CTRL0 0xe4 +#define CECA_CLK_CTRL1 0xe8 +#define CECB_CLK_CTRL0 0xec +#define CECB_CLK_CTRL1 0xf0 +#define PSRAM_CLK_CTRL 0xf4 +#define DMC_CLK_CTRL 0xf8 + +/* include the CLKIDs that have been made part of the DT binding */ +#include + +/* + * CLKID index values for internal clocks + * + * These indices are entirely contrived and do not map onto the hardware. + * It has now been decided to expose everything by default in the DT heade= r: + * include/dt-bindings/clock/a1-peripherals-clkc.h. + * Only the clocks ids we don't want to expose, such as the internal muxes= and + * dividers of composite clocks, will remain defined here. + */ +#define CLKID_XTAL_IN 0 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 +#define CLKID_SARADC_SEL 74 +#define CLKID_SYS_A_SEL 89 +#define CLKID_SYS_A_DIV 90 +#define CLKID_SYS_A 91 +#define CLKID_SYS_B_SEL 92 +#define CLKID_SYS_B_DIV 93 +#define CLKID_SYS_B 94 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_IN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define CLKID_CECB_32K_IN 111 +#define CLKID_CECB_32K_DIV 112 +#define CLKID_CECA_32K_IN 115 +#define CLKID_CECA_32K_DIV 116 +#define CLKID_DIV2_PRE 119 +#define CLKID_24M_DIV2 120 +#define CLKID_GEN_DIV 122 +#define CLKID_SARADC_DIV 123 +#define CLKID_PWM_A_DIV 125 +#define CLKID_PWM_B_DIV 127 +#define CLKID_PWM_C_DIV 129 +#define CLKID_PWM_D_DIV 131 +#define CLKID_PWM_E_DIV 133 +#define CLKID_PWM_F_DIV 135 +#define CLKID_SPICC_SEL 136 +#define CLKID_SPICC_DIV 137 +#define CLKID_SPICC_SEL2 138 +#define CLKID_TS_DIV 139 +#define CLKID_SPIFC_SEL 140 +#define CLKID_SPIFC_DIV 141 +#define CLKID_SPIFC_SEL2 142 +#define CLKID_USB_BUS_SEL 143 +#define CLKID_USB_BUS_DIV 144 +#define CLKID_SD_EMMC_SEL 145 +#define CLKID_SD_EMMC_DIV 146 +#define CLKID_PSRAM_SEL 148 +#define CLKID_PSRAM_DIV 149 +#define CLKID_PSRAM_SEL2 150 +#define CLKID_DMC_SEL 151 +#define CLKID_DMC_DIV 152 +#define CLKID_DMC_SEL2 153 +#define NR_CLKS 154 + +#endif /* __A1_PERIPHERALS_H */ --=20 2.36.0