From nobody Tue Feb 10 01:15:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12273C77B73 for ; Mon, 22 May 2023 17:34:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232876AbjEVRey (ORCPT ); Mon, 22 May 2023 13:34:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233127AbjEVReg (ORCPT ); Mon, 22 May 2023 13:34:36 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99D90DB; Mon, 22 May 2023 10:34:35 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-208-162.ewe-ip-backbone.de [91.248.208.162]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 02E986606E6F; Mon, 22 May 2023 18:34:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1684776874; bh=51auYTRk2rmb/OCj/B4amurTw9Zrd8rSx4SmfWqBalc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ITTLftw2mhA1jStffcLz6Tgut4Saukjc8ZlA06O2Nw/5ms77PEx84LKa4TbXcGS2x RkWqnlK9wdOTWbroQVTC9Fp3g460CwDi5WwgOJ/9KPKtgEdnlfTDU1/RcHPgu3CwPh aj3/nABvPnTwM5EA0zMJ1JL+C5WTuI4nSHB6hTbGQnKYmA2nvhcyLUSE+rkbmI8lXZ Ep3RZDlLRY6U6YrJ7kNRd4Zuo4NmxiS79ezjIVi5000pP8PSPTgZTWZyubeQFZsxGL IsJP4kKeOcOpScNivTy30jrus/0NbEM0Lbz+EKSJ8styd74MMG2XBU5XAHe2+2DVFs X89CDHUloyiIA== Received: by jupiter.universe (Postfix, from userid 1000) id 90CB24807EF; Mon, 22 May 2023 19:34:29 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Damien Le Moal , Serge Semin , Vinod Koul , Kishon Vijay Abraham I , linux-ide@vger.kernel.org, linux-phy@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 5/6] arm64: dts: rockchip: rk3588: add combo PHYs Date: Mon, 22 May 2023 19:34:22 +0200 Message-Id: <20230522173423.64691-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522173423.64691-1-sebastian.reichel@collabora.com> References: <20230522173423.64691-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts= /rockchip/rk3588.dtsi index 8be75556af8f..9d8539b5309b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" =20 / { + pipe_phy1_grf: syscon@fd5c0000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible =3D "rockchip,rk3588-i2s-tdm"; reg =3D <0x0 0xfddc8000 0x0 0x1000>; @@ -123,4 +128,20 @@ gmac0_mtl_tx_setup: tx-queues-config { queue1 {}; }; }; + + combphy1_ps: phy@fee10000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee10000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy1_grf>; + status =3D "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dt= s/rockchip/rk3588s.dtsi index 01058fed8f96..45ae457a22a4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -944,6 +944,16 @@ php_grf: syscon@fd5b0000 { reg =3D <0x0 0xfd5b0000 0x0 0x1000>; }; =20 + pipe_phy0_grf: syscon@fd5bc000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible =3D "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg =3D <0x0 0xfd5c4000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible =3D "rockchip,rk3588-ioc", "syscon"; reg =3D <0x0 0xfd5f0000 0x0 0x10000>; @@ -2371,6 +2381,38 @@ dmac2: dma-controller@fed10000 { #dma-cells =3D <1>; }; =20 + combphy0_ps: phy@fee00000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee00000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy0_grf>; + status =3D "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible =3D "rockchip,rk3588-naneng-combphy"; + reg =3D <0x0 0xfee20000 0x0 0x100>; + #phy-cells =3D <1>; + clocks =3D <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names =3D "ref", "apb", "pipe"; + assigned-clocks =3D <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates =3D <100000000>; + resets =3D <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names =3D "phy", "apb"; + rockchip,pipe-grf =3D <&php_grf>; + rockchip,pipe-phy-grf =3D <&pipe_phy2_grf>; + status =3D "disabled"; + }; + system_sram2: sram@ff001000 { compatible =3D "mmio-sram"; reg =3D <0x0 0xff001000 0x0 0xef000>; --=20 2.39.2