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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:57 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 24/30] net: dsa: mt7530: rename MT7530_MFC to MT753X_MFC Date: Mon, 22 May 2023 15:15:26 +0300 Message-Id: <20230522121532.86610-25-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 SoC. Some bits are for MT7530 only. Call the shared ones MT753X, the MT7530-specific ones MT7530. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 30 +++++++++++++++------------ drivers/net/dsa/mt7530.h | 44 ++++++++++++++++++++-------------------- 2 files changed, 39 insertions(+), 35 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9a4d4413287a..58d8738d94d3 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -955,12 +955,13 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int por= t) PORT_SPEC_TAG); =20 /* Enable flooding on the CPU port */ - mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | - UNU_FFP(BIT(port))); + mt7530_set(priv, MT753X_MFC, MT753X_BC_FFP(BIT(port)) | + MT753X_UNM_FFP(BIT(port)) | MT753X_UNU_FFP(BIT(port))); =20 /* Set CPU port number */ if (priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); + mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_MASK, MT7530_CPU_EN | + MT7530_CPU_PORT(port)); =20 /* CPU port gets connected to all user ports of * the switch. @@ -1120,16 +1121,19 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int= port, flags.val & BR_LEARNING ? 0 : SA_DIS); =20 if (flags.mask & BR_FLOOD) - mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), - flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_UNU_FFP(BIT(port)), + flags.val & BR_FLOOD ? + MT753X_UNU_FFP(BIT(port)) : 0); =20 if (flags.mask & BR_MCAST_FLOOD) - mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), - flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_UNM_FFP(BIT(port)), + flags.val & BR_MCAST_FLOOD ? + MT753X_UNM_FFP(BIT(port)) : 0); =20 if (flags.mask & BR_BCAST_FLOOD) - mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), - flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_BC_FFP(BIT(port)), + flags.val & BR_BCAST_FLOOD ? + MT753X_BC_FFP(BIT(port)) : 0); =20 return 0; } @@ -1667,13 +1671,13 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int por= t, static int mt753x_mirror_port_get(unsigned int id, u32 val) { return (id =3D=3D ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : - MIRROR_PORT(val); + MT7530_MIRROR_PORT(val); } =20 static int mt753x_mirror_port_set(unsigned int id, u32 val) { return (id =3D=3D ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : - MIRROR_PORT(val); + MT7530_MIRROR_PORT(val); } =20 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, @@ -2327,8 +2331,8 @@ mt7531_setup_common(struct dsa_switch *ds) mt7530_mib_reset(ds); =20 /* Disable flooding on all ports */ - mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); + mt7530_clear(priv, MT753X_MFC, MT753X_BC_FFP_MASK | MT753X_UNM_FFP_MASK + | MT753X_UNU_FFP_MASK); =20 for (i =3D 0; i < MT7530_NUM_PORTS; i++) { /* Disable forwarding by default on all ports */ diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 216081fb1c12..5ebb942b07ef 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -32,35 +32,35 @@ enum mt753x_id { #define SYSC_REG_RSTCTRL 0x34 #define RESET_MCM BIT(2) =20 -/* Registers to mac forward control for unknown frames */ -#define MT7530_MFC 0x10 -#define BC_FFP(x) (((x) & 0xff) << 24) -#define BC_FFP_MASK BC_FFP(~0) -#define UNM_FFP(x) (((x) & 0xff) << 16) -#define UNM_FFP_MASK UNM_FFP(~0) -#define UNU_FFP(x) (((x) & 0xff) << 8) -#define UNU_FFP_MASK UNU_FFP(~0) -#define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) -#define MIRROR_EN BIT(3) -#define MIRROR_PORT(x) ((x) & 0x7) -#define MIRROR_MASK 0x7 - -/* Registers for CPU forward control */ +/* Register for MAC forward control */ +#define MT753X_MFC 0x10 +#define MT753X_BC_FFP(x) (((x) & 0xff) << 24) +#define MT753X_BC_FFP_MASK MT753X_BC_FFP(~0) +#define MT753X_UNM_FFP(x) (((x) & 0xff) << 16) +#define MT753X_UNM_FFP_MASK MT753X_UNM_FFP(~0) +#define MT753X_UNU_FFP(x) (((x) & 0xff) << 8) +#define MT753X_UNU_FFP_MASK MT753X_UNU_FFP(~0) +#define MT7530_CPU_EN BIT(7) +#define MT7530_CPU_PORT(x) ((x) << 4) +#define MT7530_CPU_MASK (0xf << 4) +#define MT7530_MIRROR_EN BIT(3) +#define MT7530_MIRROR_PORT(x) ((x) & 0x7) +#define MT7530_MIRROR_MASK 0x7 + +/* Register for CPU forward control */ #define MT7531_CFC 0x4 #define MT7531_MIRROR_EN BIT(19) -#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) -#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) -#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) +#define MT7531_MIRROR_MASK (0x7 << 16) +#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & 0x7) +#define MT7531_MIRROR_PORT_SET(x) (((x) & 0x7) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ - MT7531_CFC : MT7530_MFC) + MT7531_CFC : MT753X_MFC) #define MT753X_MIRROR_EN(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D ID= _MT7988)) ? \ - MT7531_MIRROR_EN : MIRROR_EN) + MT7531_MIRROR_EN : MT7530_MIRROR_EN) #define MT753X_MIRROR_MASK(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D = ID_MT7988)) ? \ - MT7531_MIRROR_MASK : MIRROR_MASK) + MT7531_MIRROR_MASK : MT7530_MIRROR_MASK) =20 /* Registers for BPDU and PAE frame control*/ #define MT753X_BPC 0x24 --=20 2.39.2