From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDBCAC77B75 for ; Mon, 22 May 2023 12:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232676AbjEVMRr (ORCPT ); Mon, 22 May 2023 08:17:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230312AbjEVMR2 (ORCPT ); Mon, 22 May 2023 08:17:28 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D34BE42; Mon, 22 May 2023 05:16:09 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-96fa4a6a79bso309122666b.3; Mon, 22 May 2023 05:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757749; x=1687349749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W605wLVAjZcYJ+UbvgGvWkHLkMFaiTir5YrRz0YtXmg=; b=qcQP4Hsv2zkuBD1rc5sn1VmOnLPTnpkC36ZpIoFX5g5+/8j6+xMkWXmdl783YhkydI ouC3vQqGioYtYax5t3LtbhBLe89V6Vvcmvy6iY6tJGf3cATIWqmoIzc8TEzKggVb2nNf GtFBJF02BH88duMq9StIDqPSSWlOF3alAjJwZ+mHLGBnoavDEgukeXWGeSSZ8lWKS7oW R8Xux7ZtyV7n5PbQzbK+ftm9MkcnStykJc9U/2OKQ5iEnYgLYFG3y7QQBOVhTSmk9ktu MN9iT30TXuPt820WSkRz5zuN1Y7nkwixR8RfmWTuHdSKTECqM5eYkVaMiQywohNStgNc qaxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757749; x=1687349749; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W605wLVAjZcYJ+UbvgGvWkHLkMFaiTir5YrRz0YtXmg=; b=Q0hts1ZqmWLQbX0Y+V6rALGaD5ZBvdDD4mtwd0JxwgvT2/YFXA0TN11mFVLBxUtWbo 4RyXw1nyAZZNj7f9K/Q2Rjp6/JS9mQyBUQ35quvLa8KcfLXasC2rTUESwFd/F6arDKMS 3OPSoAU9+Iz5U/H47vpon6a8kq0yuuHHmt2w1eyK8hWndaXIBaCjCTClP4je7ga8NOid Ks4ATEyVPiYrTkgKcJ9jjd+Sfxl7VKSR2DyymiQy0EG0tli+MlckON+GLz6rdHsY00Ef uD1Fwq9eY6xwmYpjF4uJcoKzRq2WvlPkIJNrKXYnK0svEDjl61iyXC0Ju15H8nQTbZm2 TYEQ== X-Gm-Message-State: AC+VfDzM6rCqH5wBVIBUDa0LuuQ3Sybgct+/Ft7Uq1+EwKfsSExMz9FM B08UcNHLC3Pgj87/itq/InU= X-Google-Smtp-Source: ACHHUZ5udgAI9lXoymHWuGkdojdDxgLRZXFK1CAl38y/EIjRGn7RvR87DFYBmjpyu6txHt2HTifOGQ== X-Received: by 2002:a17:907:da8:b0:96f:8666:5fc4 with SMTP id go40-20020a1709070da800b0096f86665fc4mr9492508ejc.50.1684757748618; Mon, 22 May 2023 05:15:48 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:15:48 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 01/30] net: dsa: mt7530: add missing @p5_interface to mt7530_priv description Date: Mon, 22 May 2023 15:15:03 +0300 Message-Id: <20230522121532.86610-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add the missing p5_interface field to the mt7530_priv description. Sort out the description in the process. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Andrew Lunn Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..845f5dd16d83 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -746,7 +746,8 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers - * @p6_interface Holding the current port 6 interface + * @p6_interface: Holding the current port 6 interface + * @p5_interface: Holding the current port 5 interface * @p5_intf_sel: Holding the current port 5 interface select * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E02FC77B73 for ; Mon, 22 May 2023 12:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233815AbjEVMRt (ORCPT ); Mon, 22 May 2023 08:17:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230365AbjEVMR3 (ORCPT ); Mon, 22 May 2023 08:17:29 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8424AE56; Mon, 22 May 2023 05:16:13 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-96fffe11714so109776566b.0; Mon, 22 May 2023 05:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757752; x=1687349752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3GlYa/gtfioHyiBI/gLtS8VjxT1YVLAproZrb+Hou0E=; b=BgHNA/IgLsWdLuIeKOa8zdj4FeAFmGxSiYseC398PviO1oB4odqcU/Fy6xwJz6Z+xe QkjbiKKEogz0fAmjMPXXTbJlYwq9tsk33H/ouTCFbp2kQ2b5WCY+bB+CPyM4UOWf3E/3 VZzR3UYCSFAAugbKGJgcNmUzz8sZLkVz03gOb7NqrvwJE7QhVGS4X3mi3y/cXJXtn3KK tu3fN7K9Nqw/XcA/4dCvTz1gR7yO/o/mr4SYMqROKTdTr9K5HoOCdgmfClfySWYtowsr e4N96toLkYBKv64gc3foWTYSGC5ICtn0EoUIQZNzU+SmjVK9t6rRUBrWtD7LYnH5kA8Q MpXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757752; x=1687349752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3GlYa/gtfioHyiBI/gLtS8VjxT1YVLAproZrb+Hou0E=; b=Wl1n6AMGC8AcKsRe6ErNWuUtLY5wiDgB9b5Htz7NVr3FE4uCHjOdsnnhE146Mvdgmq hudiBCuxSP0klpY8Wi6RI+B+9zX6/GNYcjaCrv1iXGMnppPDVjtS9eu1cmjS4qgMJsYA hlj6qY+gVRXxADgBoyQIS1qMKv9iZGDbIUBBWan02Gc9inWAq/264juG+ZYFr9Xm4Pqr zCF9OGNGHRD+4otOao/Po7MwJXiBWnRPGLANYBH2591rc1FmGRms5S4hFuZSotffvhII HFYCHKR5bDiOWJSoVwLaxfu0oWMw1Snk9+Y6nJuE/TuBCDjzBe0HMIYXphb8Lkcul7bj 01HQ== X-Gm-Message-State: AC+VfDxJofA09jCbLViezCQhqq9hvfKr/cUE0X9DMkKPjeVcjBvy77TQ TN3WHW/upz4WtW6uwpvmB80= X-Google-Smtp-Source: ACHHUZ5ALSJj0jSyx6S9HSdgBAy7lcuTZBOXYIWapLqX0i4YXHmwid/evs1keI+Wl2F7gyxCa8wGXA== X-Received: by 2002:a17:907:d1c:b0:96f:df95:28a0 with SMTP id gn28-20020a1709070d1c00b0096fdf9528a0mr3477558ejc.55.1684757751614; Mon, 22 May 2023 05:15:51 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:15:51 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 02/30] net: dsa: mt7530: use p5_interface_select as data type for p5_intf_sel Date: Mon, 22 May 2023 15:15:04 +0300 Message-Id: <20230522121532.86610-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Use the p5_interface_select enumeration as the data type for the p5_intf_sel field. This ensures p5_intf_sel can only take the values defined in the p5_interface_select enumeration. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 845f5dd16d83..415d8ea07472 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -675,7 +675,7 @@ struct mt7530_port { =20 /* Port 5 interface select definitions */ enum p5_interface_select { - P5_DISABLED =3D 0, + P5_DISABLED, P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, @@ -768,7 +768,7 @@ struct mt7530_priv { bool mcm; phy_interface_t p6_interface; phy_interface_t p5_interface; - unsigned int p5_intf_sel; + enum p5_interface_select p5_intf_sel; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06AE7C77B75 for ; Mon, 22 May 2023 12:17:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231285AbjEVMR5 (ORCPT ); Mon, 22 May 2023 08:17:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbjEVMRc (ORCPT ); Mon, 22 May 2023 08:17:32 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1483B92; Mon, 22 May 2023 05:16:19 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-94a342f7c4cso1138023266b.0; Mon, 22 May 2023 05:16:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757755; x=1687349755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9lsGFTeX0rIQydp877wtSTmMxwYApzY2069TvMjD37Y=; b=VqP2eNCwlVnCy4efBjZkJB3bLGUi3jabdsxen3k5G6KnWVdeOLIjh7dOeYNVcMavJr mJTBZuEOxIDCWPYanLI9TJlNXcK2PixBhy79iMy8vSeNolmorIMKZvF3nkw9TSqkjmTL BbBEEAmF0SYGjTTvcP7C+78argIsDopVNtWRzb9CUN2L7UYbIab6y9d/O1U/9O4sJrb4 GEIMT45lI8e2O31pyiOZyPv250k2TwEaVfTE+cTeroLysM1qA+iVDNL/OHvM/WCmwtDs Huq1EGi91T5Igz7vporOpCiWKt4DVIWk902H0wXeAZksaqPsJsJWJGDRLR5m4ILUDiLR TBLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757755; x=1687349755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9lsGFTeX0rIQydp877wtSTmMxwYApzY2069TvMjD37Y=; b=AdAJuUpNTSTqHtmg1kOVaCAngm0CPniHD8jHYxZCimoHJVCn3jvl5NlxkH8ury5B+0 sUscwTzUndYh9f2dESRPBhxZm3P4ZX9RGotlR8J1q4a+XAsjrEL8cPD/gylL4C06hKJe JUkH3v9Nez88+nWhrNpN6Y5CJLbSdLdYrHNnC7QvaDImz7qUjTx0oAVxePOb0Tyd3Zyz K9V/Dysz4KLx5utoB2SVqx6S6hZmMe/pyDFYgiPR+MSb0Z5rzrSwxv8sPos30+x9W/JQ iesA08ah/KwM1lWpp9Vc1KxuwHCuK4mwLgQ9z8zbUELvN+0N29OLHGwfaNET/saYyN+i xoxw== X-Gm-Message-State: AC+VfDzx6EV42+BFSQu5tUen4UxmUrf3gNFyErKpNQpZRAA+ceaJuQsN ssOyDICUxjGPjc4KpKp2TtE= X-Google-Smtp-Source: ACHHUZ6kk+sEOP2Ik6B6lpCuAGdfmMdjT6rquSwgx2h4JRiQ4Rc0Fo/TfkEJOX2GinqX51LnuYOniw== X-Received: by 2002:a17:907:86a5:b0:966:3c82:4a97 with SMTP id qa37-20020a17090786a500b009663c824a97mr11042680ejc.35.1684757754614; Mon, 22 May 2023 05:15:54 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:15:54 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 03/30] net: dsa: mt7530: properly support MT7531AE and MT7531BE Date: Mon, 22 May 2023 15:15:05 +0300 Message-Id: <20230522121532.86610-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Introduce the p5_sgmii field to store the information for whether port 5 has got SGMII or not. Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the switch is identified. Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the information. Address the code where mt7531_dual_sgmii_supported() is used. Get rid of mt7531_is_rgmii_port() which just prints the opposite of priv->p5_sgmii. Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to represent the mode that port 5 is being used in, not the hardware information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if port 5 is not dsa_is_unused_port(). Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530-mdio.c | 7 ++--- drivers/net/dsa/mt7530.c | 48 ++++++++++++----------------------- drivers/net/dsa/mt7530.h | 6 +++-- 3 files changed, 22 insertions(+), 39 deletions(-) diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c index 088533663b83..fa3ee85a99c1 100644 --- a/drivers/net/dsa/mt7530-mdio.c +++ b/drivers/net/dsa/mt7530-mdio.c @@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus =3D { }; =20 static int -mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii) +mt7531_create_sgmii(struct mt7530_priv *priv) { struct regmap_config *mt7531_pcs_config[2] =3D {}; struct phylink_pcs *pcs; struct regmap *regmap; int i, ret =3D 0; =20 - /* MT7531AE has two SGMII units for port 5 and port 6 - * MT7531BE has only one SGMII unit for port 6 - */ - for (i =3D dual_sgmii ? 0 : 1; i < 2; i++) { + for (i =3D priv->p5_sgmii ? 0 : 1; i < 2; i++) { mt7531_pcs_config[i] =3D devm_kzalloc(priv->dev, sizeof(struct regmap_config), GFP_KERNEL); diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9bc54e1348cb..024b853f9558 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -473,15 +473,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interf= ace_t interface) return 0; } =20 -static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) -{ - u32 val; - - val =3D mt7530_read(priv, MT7531_TOP_SIG_SR); - - return (val & PAD_DUAL_SGMII_EN) !=3D 0; -} - static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -496,9 +487,6 @@ mt7531_pll_setup(struct mt7530_priv *priv) u32 xtal; u32 val; =20 - if (mt7531_dual_sgmii_supported(priv)) - return; - val =3D mt7530_read(priv, MT7531_CREV); top_sig =3D mt7530_read(priv, MT7531_TOP_SIG_SR); hwstrap =3D mt7530_read(priv, MT7531_HWTRAP); @@ -907,8 +895,6 @@ static const char *p5_intf_modes(unsigned int p5_interf= ace) return "PHY P4"; case P5_INTF_SEL_GMAC5: return "GMAC5"; - case P5_INTF_SEL_GMAC5_SGMII: - return "GMAC5_SGMII"; default: return "unknown"; } @@ -2444,6 +2430,12 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } =20 + /* MT7531AE has got two SGMII units. One for port 5, one for port 6. + * MT7531BE has got only one SGMII unit which is for port 6. + */ + val =3D mt7530_read(priv, MT7531_TOP_SIG_SR); + priv->p5_sgmii =3D !!(val & PAD_DUAL_SGMII_EN); + /* all MACs must be forced link-down before sw reset */ for (i =3D 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); @@ -2453,21 +2445,18 @@ mt7531_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); =20 - mt7531_pll_setup(priv); - - if (mt7531_dual_sgmii_supported(priv)) { - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5_SGMII; - + if (!priv->p5_sgmii) { + mt7531_pll_setup(priv); + } else { /* Let ds->slave_mii_bus be able to access external phy. */ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, MT7531_EXT_P_MDC_11); mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, MT7531_EXT_P_MDIO_12); - } else { - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; } - dev_dbg(ds->dev, "P5 support %s interface\n", - p5_intf_modes(priv->p5_intf_sel)); + + if (!dsa_is_unused_port(ds, 5)) + priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; =20 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); @@ -2527,11 +2516,6 @@ static void mt7530_mac_port_get_caps(struct dsa_swit= ch *ds, int port, } } =20 -static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) -{ - return (port =3D=3D 5) && (priv->p5_intf_sel !=3D P5_INTF_SEL_GMAC5_SGMII= ); -} - static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -2544,7 +2528,7 @@ static void mt7531_mac_port_get_caps(struct dsa_switc= h *ds, int port, break; =20 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ - if (mt7531_is_rgmii_port(priv, port)) { + if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } @@ -2611,7 +2595,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *pri= v, u32 port, { u32 val; =20 - if (!mt7531_is_rgmii_port(priv, port)) { + if (priv->p5_sgmii) { dev_err(priv->dev, "RGMII mode is not available for port %d\n", port); return -EINVAL; @@ -2864,7 +2848,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int por= t) =20 switch (port) { case 5: - if (mt7531_is_rgmii_port(priv, port)) + if (!priv->p5_sgmii) interface =3D PHY_INTERFACE_MODE_RGMII; else interface =3D PHY_INTERFACE_MODE_2500BASEX; @@ -3023,7 +3007,7 @@ mt753x_setup(struct dsa_switch *ds) mt7530_free_irq_common(priv); =20 if (priv->create_sgmii) { - ret =3D priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); + ret =3D priv->create_sgmii(priv); if (ret && priv->irq) mt7530_free_irq(priv); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 415d8ea07472..2602c95fd3a5 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -679,7 +679,6 @@ enum p5_interface_select { P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, - P5_INTF_SEL_GMAC5_SGMII, }; =20 struct mt7530_priv; @@ -749,6 +748,8 @@ struct mt753x_info { * @p6_interface: Holding the current port 6 interface * @p5_interface: Holding the current port 5 interface * @p5_intf_sel: Holding the current port 5 interface select + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN @@ -769,6 +770,7 @@ struct mt7530_priv { phy_interface_t p6_interface; phy_interface_t p5_interface; enum p5_interface_select p5_intf_sel; + bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; @@ -778,7 +780,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; - int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + int (*create_sgmii)(struct mt7530_priv *priv); }; =20 struct mt7530_hw_vlan_entry { --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A4F3C77B75 for ; Mon, 22 May 2023 12:18:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233877AbjEVMSD (ORCPT ); Mon, 22 May 2023 08:18:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233428AbjEVMRf (ORCPT ); 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:15:57 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 04/30] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Mon, 22 May 2023 15:15:06 +0300 Message-Id: <20230522121532.86610-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no PHY muxing on MT7531. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Andrew Lunn Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 024b853f9558..b28d66a7c0b2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2499,7 +2499,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays, mii, and gmii. + */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2507,7 +2509,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switc= h *ds, int port, config->supported_interfaces); break; =20 - case 6: /* 1st cpu port */ + case 6: /* Port 6 which can be used as a CPU port supports rgmii and + * trgmii. + */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2527,14 +2531,17 @@ static void mt7531_mac_port_get_caps(struct dsa_swi= tch *ds, int port, config->supported_interfaces); break; =20 - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays on MT7531BE, sgmii/802.3z on MT7531AE. + */ if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; =20 - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6 which can be used as a CPU port supports sgmii/802.3z. + */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2726,7 +2733,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, state->interface !=3D PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, can be used as a CPU port. */ if (priv->p5_interface =3D=3D state->interface) break; =20 @@ -2736,7 +2743,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p5_intf_sel !=3D P5_DISABLED) priv->p5_interface =3D state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, can be used as a CPU port. */ if (priv->p6_interface =3D=3D state->interface) break; =20 --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE6E7C77B73 for ; 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:00 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 05/30] net: dsa: mt7530: read XTAL value from correct register Date: Mon, 22 May 2023 15:15:07 +0300 Message-Id: <20230522121532.86610-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL On commit 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") macros for reading the crystal frequency were added under the MT7530_HWTRAP register. However, the value given to the xtal variable on mt7530_pad_clk_setup() is read from the MT7530_MHWTRAP register instead. Although the document MT7621 Giga Switch Programming Guide v0.3 states that the value can be read from both registers, use the register where the macros were defined under. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Andrew Lunn --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b28d66a7c0b2..1a842d6fbc27 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -406,7 +406,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interfa= ce_t interface) struct mt7530_priv *priv =3D ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; =20 - xtal =3D mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; + xtal =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; =20 if (xtal =3D=3D HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CD73C77B75 for ; Mon, 22 May 2023 12:18:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233882AbjEVMSI (ORCPT ); Mon, 22 May 2023 08:18:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233711AbjEVMRg (ORCPT ); Mon, 22 May 2023 08:17:36 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E673E77; Mon, 22 May 2023 05:16:26 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-96f6a9131fdso487288166b.1; Mon, 22 May 2023 05:16:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757764; x=1687349764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sVScU3zTASH0j+hzCtGsuJpxvVIRAa/zOAQpgtqJqxM=; b=m/51O7eeNxXRxZobtDWnfuSbXiWtJSC0wvV80vnFvNFADKAIc79e3DbvcYWkIX0Es+ lnG2avO/BMV0hllT+W42afHz3Bfan3SuBZjmKwuHvMgw9DE6OpI616Dbct9VIbmpguXz SGWfkJXGT1JURJ/lAVs/9MQLC60uK7NeuICC0FWMcbqxceDzDm05F3x/a2JbDZ9cnoWg 42E4NzsRza43iy8ttDxLLC9XImCHDBq2LjbXeeh8i97UidmlBVnDMNYFho7FWe1F0ASd kE+JSZ5hkRl5iAM2m1hCfCw4Io260THp2c2D/KMV6Mm7ebSiTTyFRlxmJUr2jHvokQsJ xgrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757764; x=1687349764; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sVScU3zTASH0j+hzCtGsuJpxvVIRAa/zOAQpgtqJqxM=; b=NZHTLtexMJdqrtmPpe3gwPy4ZiMAdKGlZjPyvF5XIShkqHTyP+KHrkvHyG+OaFZD7r dKqQbAgC27twZFG9K/OlTgF4GEAZrla61ghpfolx+c9VsPyVgPdwv5kMllRhz12Rzrgi hkHjN4APmji5hZ09k6BOHawbAch3b8AlWuYn8GBWl3DH0kvXQ3i/FRyEcZ/PwKOw0XUl S0caUgrgtDni3G2Sc25XnB4d1Jp3iCBPda/i6WPNZPog6Uc/DYle6gpUx1jsJgn+1h05 Aq//7t3Ic9gH6Sjwv4YrznMHC6yK0cxjwOsWyoLcvTT5je0bbItXgrVgYLt12bBFFeMS 2zvA== X-Gm-Message-State: AC+VfDzXpsIrB5XtIqMWshtpDNqWrVbkJzOmp+CQW51T3zdaAHyfsVKq RNGA9OR60XFgGepDa139Amk= X-Google-Smtp-Source: ACHHUZ6nI3Y3aSr0F4aJBr62iBc2SfSRXIfMW/88mqvOgFDT7L584mwB8aklUVOYhZxsTd11d+L5jg== X-Received: by 2002:a17:907:7e81:b0:966:3114:c790 with SMTP id qb1-20020a1709077e8100b009663114c790mr9442040ejc.37.1684757763663; Mon, 22 May 2023 05:16:03 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:03 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 06/30] net: dsa: mt7530: improve code path for setting up port 5 Date: Mon, 22 May 2023 15:15:08 +0300 Message-Id: <20230522121532.86610-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5 is used as a CPU, DSA, or user port, mt7530_setup_port5() from mt753x_phylink_mac_config() won't run. That is because priv->p5_interface set on mt7530_setup_port5() will match state->interface on mt753x_phylink_mac_config() which will stop running mt7530_setup_port5() again. mt7530_setup_port5() from mt753x_phylink_mac_config() won't run when port 5 is disabled or used for PHY muxing as port 5 won't be defined on the devicetree. Therefore, mt7530_setup_port5() will never run from mt753x_phylink_mac_config(). Address this by not running mt7530_setup_port5() from mt7530_setup() if port 5 is used as a CPU, DSA, or user port. For the cases of PHY muxing or the port being disabled, call mt7530_setup_port5() from mt7530_setup(). Do not set priv->p5_interface on mt7530_setup_port5(). There won't be a case where mt753x_phylink_mac_config() runs after mt7530_setup_port5() anymore. Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when "priv" is allocated. Move setting the interface to a more specific location. It's supposed to be overwritten if PHY muxing is detected. Improve the comment which explains the process. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 1a842d6fbc27..b8f159afcd45 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -965,8 +965,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, intf_sel=3D%s, phy-mode=3D%s\n= ", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); =20 - priv->p5_interface =3D interface; - unlock_exit: mutex_unlock(&priv->reg_mutex); } @@ -2274,16 +2272,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; =20 /* Setup port 5 */ - priv->p5_intf_sel =3D P5_DISABLED; - interface =3D PHY_INTERFACE_MODE_NA; - if (!dsa_is_unused_port(ds, 5)) { priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; - ret =3D of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); - if (ret && ret !=3D -ENODEV) - return ret; } else { - /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. + * Set priv->p5_intf_sel to the appropriate value if PHY muxing + * is detected. + */ + interface =3D PHY_INTERFACE_MODE_NA; + for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2314,6 +2311,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } + + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB @@ -2324,8 +2323,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ =20 - mt7530_setup_port5(ds, interface); - /* Flush the FDB table */ ret =3D mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A88BC77B73 for ; Mon, 22 May 2023 12:18:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233896AbjEVMSU (ORCPT ); Mon, 22 May 2023 08:18:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233758AbjEVMRj (ORCPT ); Mon, 22 May 2023 08:17:39 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9BBFE7B; Mon, 22 May 2023 05:16:29 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-969f90d71d4so899898366b.3; Mon, 22 May 2023 05:16:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757767; x=1687349767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wn2mhEGH9uSsWYt0IDE04ECLf6CmZ7rlTUGMQ0klVZI=; b=grVTVpbbAcn9i9tzer/Hhyb4oNJujAtO5z3JCzf25YBi1o17XTLsveA2xSkhm86GmL PfzVa/wiVvVYo70qik+FWTWUp58R1ANSICt/zHTdBA5bRiTZxk6/tn27aWfM/BJ+PKRF cfsdfLmuhcwxr+CaZgUju7xlg1HavSi9agaUVatCzMBMqyXXpbIuWCXLZjLh1/zs5xCy 9bqTLmKEjXE2bB18DrdvYsCAB4VVkU8KlCFbzXOqXDQKt7Sbf6xfDmOuLNDLvfbJHco/ FYhCluYVWAbRdHMXjetgEY5dqqaeQfxR6yjJG6UMMraor/qiFWozHyr8YU/lJZ2x4G3F 5loA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757767; x=1687349767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wn2mhEGH9uSsWYt0IDE04ECLf6CmZ7rlTUGMQ0klVZI=; b=aMbc1uLpMq38dZoY6ZlfafjbGbmciraetGX28LNtqnNODXYfnN1AISAEWJ2pZqyQLG b42eUoDZYb9izKEgx7LQC1ptJAKa4nC+CkwTHi9bw4RrnXyFYZ4zNkZ3TS//R4pOVSod DnZ83q486J++zMmcR40ZnCCU93f+4RtRNT6z1e22Pfmh4X6rUFQXUYWsgsyuFSpCvPeJ bV4/YQwcGu+6nrFDHzBmng4J342ecYk+j7viRoaHu2ry/fBqIwE2QT9bOvQ829hiQEy7 2Aoi/jrUFURdeqypE9to9ZxXRYM6k6DkNsiJgHgJgmr/E8ys7bVBtznBAlYYLybSgzr+ nRoQ== X-Gm-Message-State: AC+VfDxTkGCnm9q3r8FBOWaGHHvKJirNWCb0Xa8mvtOLL3zy6OOQVqOJ KUT80ie7H0yyrjeWCfMdd+k= X-Google-Smtp-Source: ACHHUZ6fvbfhJF4Z2fVXL4PBY3Bkq5p8IxPW8S31fGnhpc3IX2FCvH9KpW5KVg5srUK4wri4CsIx/A== X-Received: by 2002:a17:906:6a0d:b0:96a:9c44:86d9 with SMTP id qw13-20020a1709066a0d00b0096a9c4486d9mr10488875ejc.12.1684757766853; Mon, 22 May 2023 05:16:06 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:06 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 07/30] net: dsa: mt7530: do not run mt7530_setup_port5() if port 5 is disabled Date: Mon, 22 May 2023 15:15:09 +0300 Message-Id: <20230522121532.86610-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There's no need to run all the code on mt7530_setup_port5() if port 5 is disabled. The only case for calling mt7530_setup_port5() from mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from mt7530_setup_port5(). Stop initialising the interface variable as the remaining cases will always call mt7530_setup_port5() with it initialised. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b8f159afcd45..710c6622d648 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -929,9 +929,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &=3D ~MHWTRAP_P5_DIS; break; - case P5_DISABLED: - interface =3D PHY_INTERFACE_MODE_NA; - break; default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); @@ -2279,8 +2276,6 @@ mt7530_setup(struct dsa_switch *ds) * Set priv->p5_intf_sel to the appropriate value if PHY muxing * is detected. */ - interface =3D PHY_INTERFACE_MODE_NA; - for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2312,7 +2307,9 @@ mt7530_setup(struct dsa_switch *ds) break; } =20 - mt7530_setup_port5(ds, interface); + if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) + mt7530_setup_port5(ds, interface); } =20 #ifdef CONFIG_GPIOLIB --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63DECC77B73 for ; Mon, 22 May 2023 12:18:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233899AbjEVMSW (ORCPT ); Mon, 22 May 2023 08:18:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233783AbjEVMRk (ORCPT ); Mon, 22 May 2023 08:17:40 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C08AE7F; Mon, 22 May 2023 05:16:30 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-96f683e8855so500888466b.2; Mon, 22 May 2023 05:16:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757770; x=1687349770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=09nd6fTFveBIw7H/yL3o+Sjulkglg9M/F+8IUrvwpII=; b=EnpEKFtOllWOIegh28dhFbPOFH/HrmzaHge/LOuCS9HUToi39rBRx2FNGrAZcvXM+T AZlW3o1QfFyb6Clgw1RJYXfBrM/2yqMfVl9DG6qebBEI4sSdIEhb1rcYxRvMiakpB4q4 z07RkUSOb45BSrnYSg9fCLSyXOMFCykMXAvVb07Evbl7MkutAW3kWDtvUvo2mfC+yzht HyMDIGKR8mlinmJYbV9bxGWQki9RmN9IvFKg3V3i3dRhOEoNoetIJJddkAxA2svnfG5O FPWs7km3YkEBZqSg/eNKj4NChquNnmOsaiQ/3+dZfAZkM9crRMBhqymCeYX4APL7opEK HBBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757770; x=1687349770; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=09nd6fTFveBIw7H/yL3o+Sjulkglg9M/F+8IUrvwpII=; b=FIIfxHkTwY56vmYcOxiHqaEyOQH7aWcwkpUTIqNtRtmxqR7AizAqOQU4hCUbCfmUSQ hgq2b6bb65FN9KurYW7xUvkoZhvRlb2LTqoFIdp9P5UNwcDaHEfDnl5m7Lmfb0sE/8rY h0tnxXY6gQrSLzOc+bcp1VYCp+ZLV+iwcjgrwi8US+tEAWZvJwLuKyqLrzfELE675k1Y mR7cu2z4pjK0RLyIf3VerqUplrtvQkHzx4fHTQ0VOsSaBL0Ol/1vuTabXCrOm8NzJIE+ AwxzEhgAsIi69mSVCSAJjNjm1prjYoXHOHtsgb+IKa/ZuQw5dr7U08EVGziGI3bSFUBC ygUA== X-Gm-Message-State: AC+VfDzO7oFJnGW5qeXwTRB3bXmvtNS99/9KRxJUPUMPnQBPo0M0JKuZ Yi4QiwzfmNaB7e+pDIs71Es= X-Google-Smtp-Source: ACHHUZ5hU+NOmEAdAFMlajNG3Yg1qbkVUC8BFFF3ClhNmgfBkSGyllIYy5W5FEVql6P6xiR8IV0xfA== X-Received: by 2002:a17:907:7252:b0:970:c9f:2db3 with SMTP id ds18-20020a170907725200b009700c9f2db3mr1169157ejc.5.1684757769819; Mon, 22 May 2023 05:16:09 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:09 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 08/30] net: dsa: mt7530: change p{5,6}_interface to p{5,6}_configured Date: Mon, 22 May 2023 15:15:10 +0300 Message-Id: <20230522121532.86610-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The idea of p5_interface and p6_interface pointers is to prevent mt753x_mac_config() from running twice for MT7531, as it's already run with mt753x_cpu_port_enable() from mt7531_setup_common(), if the port is used as a CPU port. Change p5_interface and p6_interface to p5_configured and p6_configured. Make them boolean. Do not set them for any other reason. The priv->p5_intf_sel check is useless as in this code path, it will always be P5_INTF_SEL_GMAC5. There was also no need to set priv->p5_interface and priv->p6_interface to PHY_INTERFACE_MODE_NA on mt7530_setup() and mt7531_setup() as they would already be set to that when "priv" is allocated. The pointers were of the phy_interface_t enumeration type, and the first element of the enum is PHY_INTERFACE_MODE_NA. There was nothing in between that would change this beforehand. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 19 ++++--------------- drivers/net/dsa/mt7530.h | 10 ++++++---- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 710c6622d648..d837aa20968c 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2234,8 +2234,6 @@ mt7530_setup(struct dsa_switch *ds) val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 @@ -2455,10 +2453,6 @@ mt7531_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); =20 - /* Let phylink decide the interface later. */ - priv->p5_interface =3D PHY_INTERFACE_MODE_NA; - priv->p6_interface =3D PHY_INTERFACE_MODE_NA; - /* Enable PHY core PLL, since phy_device has not yet been created * provided for phy_[read,write]_mmd_indirect is called, we provide * our own mt7531_ind_mmd_phy_[read,write] to complete this @@ -2728,25 +2722,20 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, in= t port, unsigned int mode, goto unsupported; break; case 5: /* Port 5, can be used as a CPU port. */ - if (priv->p5_interface =3D=3D state->interface) + if (priv->p5_configured) break; =20 if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - if (priv->p5_intf_sel !=3D P5_DISABLED) - priv->p5_interface =3D state->interface; break; case 6: /* Port 6, can be used as a CPU port. */ - if (priv->p6_interface =3D=3D state->interface) + if (priv->p6_configured) break; =20 mt753x_pad_setup(ds, state); =20 if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - priv->p6_interface =3D state->interface; break; default: unsupported: @@ -2854,12 +2843,12 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int p= ort) else interface =3D PHY_INTERFACE_MODE_2500BASEX; =20 - priv->p5_interface =3D interface; + priv->p5_configured =3D true; break; case 6: interface =3D PHY_INTERFACE_MODE_2500BASEX; =20 - priv->p6_interface =3D interface; + priv->p6_configured =3D true; break; default: return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 2602c95fd3a5..06037be5882c 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -745,8 +745,10 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers - * @p6_interface: Holding the current port 6 interface - * @p5_interface: Holding the current port 5 interface + * @p6_configured: Flag for distinguishing if port 6 of the MT7531 switch + * is already configured + * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch + * is already configured * @p5_intf_sel: Holding the current port 5 interface select * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII @@ -767,8 +769,8 @@ struct mt7530_priv { const struct mt753x_info *info; unsigned int id; bool mcm; - phy_interface_t p6_interface; - phy_interface_t p5_interface; + bool p6_configured; + bool p5_configured; enum p5_interface_select p5_intf_sel; bool p5_sgmii; u8 mirror_rx; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64EFEC77B75 for ; Mon, 22 May 2023 12:18:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233905AbjEVMS1 (ORCPT ); Mon, 22 May 2023 08:18:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233854AbjEVMRm (ORCPT ); Mon, 22 May 2023 08:17:42 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69FB51BC7; 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:12 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 09/30] net: dsa: mt7530: empty default case on mt7530_setup_port5() Date: Mon, 22 May 2023 15:15:11 +0300 Message-Id: <20230522121532.86610-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() On the first code path, priv->p5_intf_sel is either set to P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run. On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when mt7530_setup_port5() is run. Empty the default case which will never run but is needed nonetheless to handle all the remaining enumeration values. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d837aa20968c..50f150ff481a 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -930,9 +930,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) val &=3D ~MHWTRAP_P5_DIS; break; default: - dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", - priv->p5_intf_sel); - goto unlock_exit; + break; } =20 /* Setup RGMII settings */ @@ -962,7 +960,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, intf_sel=3D%s, phy-mode=3D%s\n= ", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); =20 -unlock_exit: mutex_unlock(&priv->reg_mutex); } =20 --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89B2BC77B73 for ; Mon, 22 May 2023 12:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233865AbjEVMSf (ORCPT ); Mon, 22 May 2023 08:18:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231358AbjEVMRn (ORCPT ); Mon, 22 May 2023 08:17:43 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9B121BCC; Mon, 22 May 2023 05:16:34 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-96ff9c0a103so103011466b.0; Mon, 22 May 2023 05:16:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757776; x=1687349776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W9sUzeE3WCfQ+rJ/EsdfBikYVvHj1ppa8r6Hpeq3Xns=; b=Lru3OuyMurIkYbxbLVEVMZ/Jo0Q1/ypDQXQjCZNIgIj7jLHaw7aIU41akE0EsFPrQX hHiBxYJUpAOmZIhjHqyOrm53kaBoH3P1/jqSqtR3Qi5aSc3BoE07iNMeBCx/E+2vd+3X akaBXJlboxM574/wtu7wBakkO/e8vpCpgcqXpQ71RQwCCrvrjXcN/TAobYVRUn6Qr7P/ Y1c2EZNM+SVM2PPv03/+iiS8byBqa89rvt1nOpKrSUWT44Haf2eldP+S5hXB0y5DD9wL YcKVr0JMeVaJuQT0Ih1IHjlEDV4yhOxPyO1NR0PAOsAW2v/BsE4sp1oaoYqPo8Eu5OLT Ox9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757776; x=1687349776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W9sUzeE3WCfQ+rJ/EsdfBikYVvHj1ppa8r6Hpeq3Xns=; b=HLor66t5vYpuDdCGyiBH9O60fYHudoDIZ0VX0vFMtIHiAZG638EcftUXuHxkhEv4lM UibJSFsd9V3+n6bTTSQddklfAToTF5D9TyWn8FhfbvbFnyHW1WTBCn15hvyOoT5Gwphb 7gxERD69XeFEnPh6q9dFdzBrwaJ4hb7G8+TbxldjP6xTLFhuvG5V+LbMnnJ59YPBR1Ri VqC9UMSdg3Kss5ZQb8iNToiiXzOhm018+PcSEQYm33wglj6v7TvQz2PWLV5OcpjNUSQr jD1zUnysRmIIOBfS0b8WLab1scpy/tTL/v8JXDogyaTbXhGsyL5+spYn1Qp7qNXYs5e4 aYNQ== X-Gm-Message-State: AC+VfDwh7VYgZAWU50DB9Oz4mHiJZwJ8IBq+WBejpkkx00bgzx7Ltq8I nsV8ou1BJk9bgF92VsvSxHU= X-Google-Smtp-Source: ACHHUZ5MU8p3F+UDBjC8RPaKb565fSlJlhmk4dmBGe9CiVj0i7SklbrLxSMJnto+s68zga+9h8C47A== X-Received: by 2002:a17:907:162a:b0:96f:dd14:f749 with SMTP id hb42-20020a170907162a00b0096fdd14f749mr2811980ejc.23.1684757776077; Mon, 22 May 2023 05:16:16 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:15 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 10/30] net: dsa: mt7530: call port 6 setup from mt7530_mac_config() Date: Mon, 22 May 2023 15:15:12 +0300 Message-Id: <20230522121532.86610-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more things than setting up port 6. That part was moved to more appropriate locations, mt7530_setup() and mt7530_pll_setup(). Now that all it does is set up port 6, rename it to mt7530_setup_port6(), and move it to a more appropriate location, under mt7530_mac_config(). Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function pointer. This is the code path for setting up the ports before: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt753x_pad_setup() -> mt7530_pad_clk_setup() This is after: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt7530_setup_port6() Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 50f150ff481a..0b0ed1bd2afa 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -401,7 +401,7 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) =20 /* Setup port 6 interface mode and TRGMII TX circuit */ static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; @@ -473,6 +473,12 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interf= ace_t interface) return 0; } =20 +static int +mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +{ + return 0; +} + static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -2571,12 +2577,15 @@ mt7530_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; + int ret; =20 - /* Only need to setup port5. */ - if (port !=3D 5) - return 0; - - mt7530_setup_port5(priv->ds, interface); + if (port =3D=3D 5) { + mt7530_setup_port5(priv->ds, interface); + } else if (port =3D=3D 6) { + ret =3D mt7530_setup_port6(priv->ds, interface); + if (ret) + return ret; + } =20 return 0; } --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21E1C77B75 for ; Mon, 22 May 2023 12:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232538AbjEVMSm (ORCPT ); Mon, 22 May 2023 08:18:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233823AbjEVMRo (ORCPT ); Mon, 22 May 2023 08:17:44 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D66721BD1; Mon, 22 May 2023 05:16:35 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-96f8d485ef3so368752066b.0; Mon, 22 May 2023 05:16:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757779; x=1687349779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NC6YZzrcByzpZ4gpaBCW+or5QHPTH2iNbvDVQvL05bo=; b=BW308YhYirBYDaC16QvJwMVBaZVb/Eh3rg9CYru+1WEZNs4BIiJSzw8PCSJWjfkg2A RzY5h0RMsWNZpHnhyw7yoapWpoMm4yjeeF6csc2geWmOvm5pb3Wym6FE920iKPgna8vk RYgN64SDBgEgAjvvwDeFBkSB/SEh9WV6tQjmZ8UVufeYwtXBny6icdn1v/oxHfMx1by0 l8t+Ldq8MPTu6X6uXC6kGJElv6FKXQxKdIXrdd88IeIsaLko/gaLQOpuY5DJGkhKf3K0 DPt98XD5Dg7rmwlhy/2wvR4ZK2prgN5g2gRu9A/m/jW2muibrOmLrO3fGa61BHPdS1Py Q9rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757779; x=1687349779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NC6YZzrcByzpZ4gpaBCW+or5QHPTH2iNbvDVQvL05bo=; b=TulKm1drgQGbcXxRoXG7Y9n+ayBQGYWt0rhBUGz6fG5aQ/H5qTGkPMafQdXLfszvcW zIb/Q8Ct9eMeFky673lQqUfvAzHw+WPAtbawYXXyUBgUgAE5n4XnLNZ55QhVXfjdFh42 gC7jVODpNcJbMt7yFVZOMhCGlI145Dywb8E6WXeSp5bkfebLiSm+CfpsC9kJiYtv/R+a IPUF+xqeLtFtCnRyfTJ6Bly0JCn5DrJW1rWrl0BR2p4Sd7FE614bo9xPrhd68RGEhjhs lHq/XYm00AZzW0GxrVKN5nVfWk621xSJjocT/F1yoKyQZoZrbrN0CUnKYGKYwp9tYwtR c+fA== X-Gm-Message-State: AC+VfDwXqElkSEw4ED8Ph6z2nZtemmbRkF5GdvvAPHu5xKwcDtfOVYvY mAXMBJfalTNqb0bx0Kgu8Ss= X-Google-Smtp-Source: ACHHUZ5k3AfrQJAGbfRfJccF74zmMk6YsAOSCi93F4q7/JnywGs055W/an73T9NM4PVrrElWAPfrbg== X-Received: by 2002:a17:907:9490:b0:94f:61f5:9ef7 with SMTP id dm16-20020a170907949000b0094f61f59ef7mr9594223ejc.44.1684757779023; Mon, 22 May 2023 05:16:19 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:18 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 11/30] net: dsa: mt7530: remove pad_setup function pointer Date: Mon, 22 May 2023 15:15:13 +0300 Message-Id: <20230522121532.86610-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware"). It was being used to set up the core clock and port 6 of the MT7530 switch, and pll of the MT7531 switch. All of these were moved to more appropriate locations, and it was never used for the switch on the MT7988 SoC. Therefore, this function pointer hasn't got a use anymore. Remove it. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 36 ++---------------------------------- drivers/net/dsa/mt7530.h | 3 --- 2 files changed, 2 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0b0ed1bd2afa..049f7be0d790 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -473,18 +473,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) return 0; } =20 -static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - -static int -mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static void mt7531_pll_setup(struct mt7530_priv *priv) { @@ -2564,14 +2552,6 @@ static void mt7988_mac_port_get_caps(struct dsa_swit= ch *ds, int port, } } =20 -static int -mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *s= tate) -{ - struct mt7530_priv *priv =3D ds->priv; - - return priv->info->pad_setup(ds, state->interface); -} - static int mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2738,8 +2718,6 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int = port, unsigned int mode, if (priv->p6_configured) break; =20 - mt753x_pad_setup(ds, state); - if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; break; @@ -3041,11 +3019,6 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 -static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) -{ - return 0; -} - static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; @@ -3107,7 +3080,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7530_phy_write_c22, .phy_read_c45 =3D mt7530_phy_read_c45, .phy_write_c45 =3D mt7530_phy_write_c45, - .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, }, @@ -3119,7 +3091,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7530_phy_write_c22, .phy_read_c45 =3D mt7530_phy_read_c45, .phy_write_c45 =3D mt7530_phy_write_c45, - .pad_setup =3D mt7530_pad_clk_setup, .mac_port_get_caps =3D mt7530_mac_port_get_caps, .mac_port_config =3D mt7530_mac_config, }, @@ -3131,7 +3102,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7531_ind_c22_phy_write, .phy_read_c45 =3D mt7531_ind_c45_phy_read, .phy_write_c45 =3D mt7531_ind_c45_phy_write, - .pad_setup =3D mt7531_pad_setup, .cpu_port_config =3D mt7531_cpu_port_config, .mac_port_get_caps =3D mt7531_mac_port_get_caps, .mac_port_config =3D mt7531_mac_config, @@ -3144,7 +3114,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c22 =3D mt7531_ind_c22_phy_write, .phy_read_c45 =3D mt7531_ind_c45_phy_read, .phy_write_c45 =3D mt7531_ind_c45_phy_write, - .pad_setup =3D mt7988_pad_setup, .cpu_port_config =3D mt7988_cpu_port_config, .mac_port_get_caps =3D mt7988_mac_port_get_caps, .mac_port_config =3D mt7988_mac_config, @@ -3174,9 +3143,8 @@ mt7530_probe_common(struct mt7530_priv *priv) /* Sanity check if these required device operations are filled * properly. */ - if (!priv->info->sw_setup || !priv->info->pad_setup || - !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || - !priv->info->mac_port_get_caps || + if (!priv->info->sw_setup || !priv->info->phy_read_c22 || + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || !priv->info->mac_port_config) return -EINVAL; =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 06037be5882c..f7a504e4c17b 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -696,8 +696,6 @@ struct mt753x_pcs { * @phy_write_c22: Holding the way writing PHY port using C22 * @phy_read_c45: Holding the way reading PHY port using C45 * @phy_write_c45: Holding the way writing PHY port using C45 - * @pad_setup: Holding the way setting up the bus pad for a certain - * MAC port * @phy_mode_supported: Check if the PHY type is being supported on a cert= ain * port * @mac_port_validate: Holding the way to set addition validate type for a @@ -718,7 +716,6 @@ struct mt753x_info { int regnum); int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, int regnum, u16 val); - int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04BF7C77B73 for ; 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:21 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 12/30] net: dsa: mt7530: move XTAL check to mt7530_setup() Date: Mon, 22 May 2023 15:15:14 +0300 Message-Id: <20230522121532.86610-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The crystal frequency concerns the switch core. The frequency should be checked when the switch is being set up so the driver can reject the unsupported hardware earlier and without requiring port 6 to be used. Move it to mt7530_setup(). Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Andrew Lunn --- drivers/net/dsa/mt7530.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 049f7be0d790..fa48273269c4 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -408,13 +408,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) =20 xtal =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; =20 - if (xtal =3D=3D HWTRAP_XTAL_20MHZ) { - dev_err(priv->dev, - "%s: MT7530 with a 20MHz XTAL is not supported!\n", - __func__); - return -EINVAL; - } - switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint =3D 0; @@ -2133,7 +2126,7 @@ mt7530_setup(struct dsa_switch *ds) struct mt7530_dummy_poll p; phy_interface_t interface; struct dsa_port *cpu_dp; - u32 id, val; + u32 id, val, xtal; int ret, i; =20 /* The parent node of master netdev which holds the common system @@ -2203,6 +2196,15 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } =20 + xtal =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; + + if (xtal =3D=3D HWTRAP_XTAL_20MHZ) { + dev_err(priv->dev, + "%s: MT7530 with a 20MHz XTAL is not supported!\n", + __func__); + return -EINVAL; + } + /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0ACFC77B73 for ; Mon, 22 May 2023 12:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233926AbjEVMSw (ORCPT ); Mon, 22 May 2023 08:18:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233866AbjEVMRs (ORCPT ); Mon, 22 May 2023 08:17:48 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 619101BD5; Mon, 22 May 2023 05:16:37 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-96f5685f902so569189366b.2; Mon, 22 May 2023 05:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757785; x=1687349785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=of7dhH8J3ho1PfuXe76W3u3tJHukqwcuraQIJQcYN60=; b=qWTaVgWkUzAJ06YY3hTPNp7zErtB8/KIq1sA0UBFKANHLaNi9kTWG+Iexjhx7sRc7T CUf0F+oRPCaTCziA8nv9p8qnq6S4K24BbLoTxpLz7Y1Z0XoRJmOkAUwHZy+2qDaIqbMd mIse49HGrVml3HYhG4vcUKquF4PmGXv7Fi7QEpUx/SvXtNIaYpNQiatHJYY+o7N4A8Ss zx2vZKFl88Z7svGALWMdOnDStY+Rl6aupg/ESSpiYsi9SUg2Q6mXgNIYnm0CG186vd/9 CmhaR795SFKc8ntDNgXSJRdiQ6JJJW8BhviqYiMFe7E8IK13/+pRazkfFYUeqV+BlgRz m2Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757785; x=1687349785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=of7dhH8J3ho1PfuXe76W3u3tJHukqwcuraQIJQcYN60=; b=j5exVz/wQSqFfkgqgR4BcHXZS9eaSI2G13ZlUbXEkJozN67yd5dA3vdPdO5YHFX71m DlABZoBzGGEfgwVvAN1oOHY40kyuAtVQ6Se72W76rRQTaV5RQjQNBKqoM4ICi6ZCS+1d FfSyUQYEzLaivPfcr0yo0JNW9y7cglgd5IG/UMwbZq9wk6RyUFLi7JozOirDUA2oS2l8 0in6vL6R0HeZRU1vajRnN5By1//P4F6VfGuuw/p5aZ+nGhlhcpvWDEpQCb3SB1tvI+7U 1OZ8/FnAlalOesY9ZJjM8xV6H5R/9YUZR8hUTumjeKng62PmACHE99SlekiDLGYrVRVN 1doQ== X-Gm-Message-State: AC+VfDzTzAOsBCFS1ZYF+qqAuJ0RZjNrCvjLb3nLg5s6IBGB4SZeVUeZ 5KnogGHdjwyTH2zkEcX9dOc= X-Google-Smtp-Source: ACHHUZ5iPQRvAzfYeHS21dOJr4kXanM4mzWwkMni0MAf/pp0FexpqhAICo6YCIZpRsHeEJUcw9e59Q== X-Received: by 2002:a17:906:5d08:b0:961:8570:4589 with SMTP id g8-20020a1709065d0800b0096185704589mr11089592ejt.30.1684757784983; Mon, 22 May 2023 05:16:24 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:24 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 13/30] net: dsa: mt7530: move enabling port 6 to mt7530_setup_port6() Date: Mon, 22 May 2023 15:15:15 +0300 Message-Id: <20230522121532.86610-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Enable port 6 only when port 6 is being used. Update the comment on mt7530_setup() with a better explanation. Do not set MHWTRAP_MANUAL on mt7530_setup_port5() as it's already done on mt7530_setup() beforehand. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index fa48273269c4..47b89193d4cc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -406,6 +406,8 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface= _t interface) struct mt7530_priv *priv =3D ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; =20 + mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); + xtal =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; =20 switch (interface) { @@ -897,7 +899,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) =20 val =3D mt7530_read(priv, MT7530_MHWTRAP); =20 - val |=3D MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val |=3D MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &=3D ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; =20 switch (priv->p5_intf_sel) { @@ -2221,9 +2223,11 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); =20 - /* Enable port 6 */ + /* Directly access the PHY registers via C_MDC/C_MDIO. The bit that + * enables modifying the hardware trap must be set for this. + */ val =3D mt7530_read(priv, MT7530_MHWTRAP); - val &=3D ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; + val &=3D ~MHWTRAP_PHY_ACCESS; val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73D9DC77B73 for ; Mon, 22 May 2023 12:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233931AbjEVMTB (ORCPT ); Mon, 22 May 2023 08:19:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232717AbjEVMRx (ORCPT ); Mon, 22 May 2023 08:17:53 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECF851BDD; Mon, 22 May 2023 05:16:39 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-96f7bf29550so456816966b.3; Mon, 22 May 2023 05:16:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757788; x=1687349788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MXJvm4BanXy98faJtbpsaIfSwxdUE0yan5VZ72bTyhw=; b=JFML/u+TZX374inSW9dEos+1RCN6m2sGTv63O/EfGGpmOJhQQ8zqpNh8cRppdWf6lq ymtwX6Y+BdlMhtGfP3cEfoIq6tCmI20/SW0P7pS4lumP3KLTKIBmVIFxResi0X2aX+vx tke2x165gkXom6+/GJc1qS8fTaXlif3ynvr1PR7AYCS+1NGwKINg9ZvJndQj++BiPJXt BSJzvT+aIOM1QbGeJE6tvr2JonPJ22OOI2QaCQFGEFZRdA+un4O9XAugd3E0qrC+DhXZ 8LjrEhGpP4PY0IPPRcOkPXfhXq/fR/cZUY8VA5RY2NwPmB8zghJLyL3Lza4loz0O7b3F wyZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757788; x=1687349788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MXJvm4BanXy98faJtbpsaIfSwxdUE0yan5VZ72bTyhw=; b=KrkKU4s2Ssa/ByOWeUK+rMzeBJibee/gqyeE5PE44wTNNotVy5z5zKUjzBYi0Wy5Z0 oYVAhT39UCqLUFpptiT7a03X6g6AjHBeuRNKhoHeUySbwpwV2oXkmUizlRvxrD+wZs7j 5mc87kaZTejf9xWYAFvq+nZOZlRgSUQPdyqAJIdWTL6T4IG1j65EnnoDRKkkwgl+tnnk Ac3UGG8lnRdCtNXvWQCCJbxF+bJwi8NshPWfw2ZEAoHfv9KwW4ah/mCff5MCTFadtHj1 ZBRgR5QKNGwE/vqj8Eiv0dJ9NEQKiLgTzTcRF72JvNh5F3wDXe0ytaC/kRkgF7hPkJNh SvTg== X-Gm-Message-State: AC+VfDw26UPpU+V0icPt/QHvfK0AUszeMDE7mKK54W/Bq9Fft0sdkA3U 9e7URG3dhjfl1tawmlgdTlQ= X-Google-Smtp-Source: ACHHUZ6vJ8AzE8PNAfVN1zoa1xmkJap1GYfYdM/+VUy2HoekWvjptqJ31qOUOdDQPBDRBrJsLfLySw== X-Received: by 2002:a17:907:3206:b0:94f:6058:4983 with SMTP id xg6-20020a170907320600b0094f60584983mr8336972ejb.76.1684757787991; Mon, 22 May 2023 05:16:27 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:27 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 14/30] net: dsa: mt7530: switch to if/else statements on mt7530_setup_port6() Date: Mon, 22 May 2023 15:15:16 +0300 Message-Id: <20230522121532.86610-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL This code is from before this driver was converted to phylink API. Phylink deals with the unsupported interface cases before mt7530_setup_port6() is run. Therefore, the default case would never run. However, it must be defined nonetheless to handle all the remaining enumeration values, the phy-modes. Switch to if/else statements which simplifies the code. Change mt7530_setup_port6() to void now that there're no error cases left. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 47b89193d4cc..744787e38ecc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -400,26 +400,28 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) } =20 /* Setup port 6 interface mode and TRGMII TX circuit */ -static int +static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal; + u32 ncpo1, ssc_delta, xtal; =20 mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); =20 xtal =3D mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; =20 - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - trgint =3D 0; - break; - case PHY_INTERFACE_MODE_TRGMII: - trgint =3D 1; + if (interface =3D=3D PHY_INTERFACE_MODE_RGMII) { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(0)); + } else { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(1)); + if (xtal =3D=3D HWTRAP_XTAL_25MHZ) ssc_delta =3D 0x57; else ssc_delta =3D 0x87; + if (priv->id =3D=3D ID_MT7621) { /* PLL frequency: 125MHz: 1.0GBit */ if (xtal =3D=3D HWTRAP_XTAL_40MHZ) @@ -432,17 +434,7 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) if (xtal =3D=3D HWTRAP_XTAL_25MHZ) ncpo1 =3D 0x1400; } - break; - default: - dev_err(priv->dev, "xMII interface %d not supported\n", - interface); - return -EINVAL; - } =20 - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, - P6_INTF_MODE(trgint)); - - if (trgint) { /* Disable the MT7530 TRGMII clocks */ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); =20 @@ -464,8 +456,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface= _t interface) /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); } - - return 0; } =20 static void @@ -2563,14 +2553,11 @@ mt7530_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - int ret; =20 if (port =3D=3D 5) { mt7530_setup_port5(priv->ds, interface); } else if (port =3D=3D 6) { - ret =3D mt7530_setup_port6(priv->ds, interface); - if (ret) - return ret; + mt7530_setup_port6(priv->ds, interface); } =20 return 0; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBFD1C7EE2D for ; Mon, 22 May 2023 12:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233940AbjEVMTM (ORCPT ); Mon, 22 May 2023 08:19:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233042AbjEVMR5 (ORCPT ); Mon, 22 May 2023 08:17:57 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3298A1BE5; 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:30 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 15/30] net: dsa: mt7530: set TRGMII RD TAP if trgmii is being used Date: Mon, 22 May 2023 15:15:17 +0300 Message-Id: <20230522121532.86610-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL This code sets the Read Data (RD) TAP value to 16 for all TRGMII control registers. The for loop iterates over all the TRGMII control registers, and mt7530_rmw() function is used to perform a read-modify-write operation on each register's RD_TAP field to set its value to 16. This operation is used to tune the timing of the read data signal in TRGMII to match the TX signal of the link partner. Run this if trgmii is being used. Since this code doesn't lower the driving, there's no apparent benefit to run this if trgmii is not being used. Add a comment to explain the code. Thanks to =E8=B6=99=E7=9A=8E=E5=AE=8F (Landen Chao) for pointing out what t= he code does. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean --- drivers/net/dsa/mt7530.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 744787e38ecc..f2c1aa9cf7f7 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, xtal; + u32 ncpo1, ssc_delta, i, xtal; =20 mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); =20 @@ -455,6 +455,11 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interfac= e_t interface) =20 /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); + + /* Set the Read Data TAP value of the MT7530 TRGMII */ + for (i =3D 0; i < NUM_TRGMII_CTRL; i++) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); } } =20 @@ -2209,10 +2214,6 @@ mt7530_setup(struct dsa_switch *ds) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), TD_DM_DRVP(8) | TD_DM_DRVN(8)); =20 - for (i =3D 0; i < NUM_TRGMII_CTRL; i++) - mt7530_rmw(priv, MT7530_TRGMII_RD(i), - RD_TAP_MASK, RD_TAP(16)); - /* Directly access the PHY registers via C_MDC/C_MDIO. The bit that * enables modifying the hardware trap must be set for this. */ --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A252C77B75 for ; Mon, 22 May 2023 12:19:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231393AbjEVMTP (ORCPT ); Mon, 22 May 2023 08:19:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbjEVMR5 (ORCPT ); Mon, 22 May 2023 08:17:57 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B7191BEF; Mon, 22 May 2023 05:16:43 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-96f99222e80so449236066b.1; Mon, 22 May 2023 05:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757794; x=1687349794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LXWcb5B2+vJzEM1ajF8yrjUWQCkaIrKdZXzgLh1rBzw=; b=khhO8hLijzVbaNMGFVCDvnqJ4dImG84zrCI76PV6OxcquPDu4U5AhUaiUPnQN0WOsc EngublP0KhkERGpYyon51lVE+fhOh+8of5CCwMxQhUPiMGCUq4VPQxEOSB0rXpk2SzM2 YnEX5WDiCQEQWLmkTNW0uLJokzkGu2rnCPKWJbRHtGPFf0lJvzlmc4q/AdrtIE74vtgD HHTrqENF4j5Gg+OuH/PA/YvVSaxCmU1rMvLBkcOl+qeY+jpYbcfOLTnLwgaBvkaHmWmA T95oNv4yY5OaB9kQ4FGFCIvBgZskr9F79dhpUv2RW3iy5DGWrKJlQAB7+9CTSIs2QNak Erog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757794; x=1687349794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LXWcb5B2+vJzEM1ajF8yrjUWQCkaIrKdZXzgLh1rBzw=; b=MSfDrmgJTPTwrxy2yoIPfPhUdu/NaxScVSYKR4qN7Ses3jv4Ei+eKyFSzM3d9XEFen VpX4XI/RISfYMVeU++tNLcItE/qRlKaoOkwjmQr3auif+GlRnhsovtvIbBGXl70l92H9 LIZj2Dd4hyTqHHTpKsaXr1nK5CL/L2sR76Npz6J0AoBL7MDpyiU7JKAbRQrtZ/O3rOGX 90SQf5Ci8LeebZILbYircUOtZu/XJHtdDya2nbcPHvq7DsE/5SttD/Jdx1lxTUO2snXd 9viyKuXRUSz61Zz6+0hkuO1sVZMXqqDemH5HtgoKYdmQlB/DsJmLGN4hlUyXUffmekg/ z7mw== X-Gm-Message-State: AC+VfDygBcY0Nc7P34U+j9FgBjA8tQZnJAw+kx2ZWmnYkCtfD9ikrA39 7HgWHpUH9XROsn5N+9MXwTI= X-Google-Smtp-Source: ACHHUZ6QHJYC5GUYqWHlBjRvQ9wBEB0YxRBTmvWBroelqSxpoGapH/6RRzqmpJJv+ptd0XgHV+e2ww== X-Received: by 2002:a17:907:7ea3:b0:966:399e:a5a5 with SMTP id qb35-20020a1709077ea300b00966399ea5a5mr8891079ejc.35.1684757793930; Mon, 22 May 2023 05:16:33 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:33 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 16/30] net: dsa: mt7530: move lowering port 5 RGMII driving to mt7530_setup() Date: Mon, 22 May 2023 15:15:18 +0300 Message-Id: <20230522121532.86610-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Move lowering Tx driving of rgmii on port 5 to right before lowering of Tx driving of trgmii on port 6 on mt7530_setup(). This way, the switch should consume less power regardless of port 5 being used. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f2c1aa9cf7f7..514e82299537 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -933,10 +933,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, = phy_interface_t interface) /* P5 RGMII TX Clock Control: delay x */ mt7530_write(priv, MT7530_P5RGMIITXCR, CSR_RGMII_TXC_CFG(0x10 + tx_delay)); - - /* reduce P5 RGMII Tx driving, 8mA */ - mt7530_write(priv, MT7530_IO_DRV_CR, - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); } =20 mt7530_write(priv, MT7530_MHWTRAP, val); @@ -2209,6 +2205,10 @@ mt7530_setup(struct dsa_switch *ds) =20 mt7530_pll_setup(priv); =20 + /* Lower P5 RGMII Tx driving, 8mA */ + mt7530_write(priv, MT7530_IO_DRV_CR, + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + /* Lower Tx driving for TRGMII path */ for (i =3D 0; i < NUM_TRGMII_CTRL; i++) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30F81C77B75 for ; Mon, 22 May 2023 12:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233946AbjEVMTT (ORCPT ); Mon, 22 May 2023 08:19:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233848AbjEVMR6 (ORCPT ); Mon, 22 May 2023 08:17:58 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D47391BF0; Mon, 22 May 2023 05:16:43 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-97000a039b2so112625466b.2; Mon, 22 May 2023 05:16:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757797; x=1687349797; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BlebeOxwlkH4BlrTKG+sqIzxXmw3yFvwUw1o/jS7CVE=; b=CCUVOMg5NOmJkyahPTiVIE7b2Qz5Vgq/LKhxpQjav2u0Up8mDWWHYHm+0NgSpreCKY oioifpMAJWedSMwhbyN8jDY9pwgCJGnH7bd4Ygk8b7B9sVPqQtgkc2FCCPFUCBU57ary +4BzYdNeuugT1YdEpqBzFbrDvneFS0r+8lPnrweiTEtRITKC7oaLW6cyJ/kwD4d0HzgC bNmunD2PsgSccaF0Cl/J7t2B/8ePdkcZBMlRny2V4h2pjYpcAcI8C1aS3NKrJyG5TC9q oHAY46EJDa1qCxinrv+tmOSQv/ZrDGNbbRiVZERTjnAeTwNIDVNjrh2Adwcn4nkeV6Lw DZyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757797; x=1687349797; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BlebeOxwlkH4BlrTKG+sqIzxXmw3yFvwUw1o/jS7CVE=; b=Lj6ELRdFI7pLiNIS+og3aCb6Z7xwuLNai2VwIGgxMXKfaJ1hshVzMr1L300rpZSt0H 3h1UyeU0MltKRFk84JPDkVY29ravElPFjPB5S6KMD7mJUwB9vlPNNdLkqIRvmn7FPxd5 eDk6J1pQALHg5ZEVJDM5cQ5FGehZGrz4HPoxLpQec6acOU+YlBOxEbPtRF9inxP4wREP UYUdNw+NLbCKD4EJpKKNbb7eqE2ClnxdpsBAOc/4dG28AdJhhQrnsROywxyRaKp5o2T4 ClEcvfMjt24IkDuMb+nvshWUJBrn6cAVit65m6vEw/tK1IkLWNi0waFa97QynEIAB9nR QXVA== X-Gm-Message-State: AC+VfDxSK9rrpZPrSpI+gWaWDy7v6gkUqEy+JPVmMUOle73qciGRwQzh 9UJ4p/U3xogELosCXyfwE8k= X-Google-Smtp-Source: ACHHUZ5tp5FjFfcmtJpb7cAxVY5NVD2PSNFXgo6ZrgwEF5wMZEr1HL6G4oZxYD/wtw9KZaLVPfXp5g== X-Received: by 2002:a17:907:7da7:b0:94e:fa56:a74f with SMTP id oz39-20020a1709077da700b0094efa56a74fmr10398638ejc.14.1684757796855; Mon, 22 May 2023 05:16:36 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:36 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 17/30] net: dsa: mt7530: fix port capabilities for MT7988 Date: Mon, 22 May 2023 15:15:19 +0300 Message-Id: <20230522121532.86610-18-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3. Set the internal phy cases to '0 ... 3'. There's no need to clear the config->supported_interfaces bitmap before reporting the supported interfaces as all bits in the bitmap will already be initialized to zero when the phylink_config structure is allocated. There's no code that would change the bitmap beforehand. Remove it. Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-i= n switch") Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 514e82299537..f017cc028183 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2533,10 +2533,8 @@ static void mt7531_mac_port_get_caps(struct dsa_swit= ch *ds, int port, static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { - phy_interface_zero(config->supported_interfaces); - switch (port) { - case 0 ... 4: /* Internal phy */ + case 0 ... 3: /* Internal phy */ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E497AC77B75 for ; Mon, 22 May 2023 12:19:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233957AbjEVMT1 (ORCPT ); Mon, 22 May 2023 08:19:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233888AbjEVMSK (ORCPT ); Mon, 22 May 2023 08:18:10 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 39A8A1BFB; Mon, 22 May 2023 05:16:49 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-96652cb7673so945803366b.0; Mon, 22 May 2023 05:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757800; x=1687349800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7tJgSrsfJjBPduQ55oOsMul7hMtXzANzGQOA9D+BS4Q=; b=ZIVjXqZm2HxwrcjR1rFQj37pSDw/EAe2pmr8IgX7/oRVAdO9D5Mbtu3SPqksLMkREh T9xTkPJ2DH2L0Bm2ImuoBgnY8/k0+e8W9VyG5EHAm1KPXNqJyHAHBcCbCjcRC279kXWE Hwv1G68hkvXY2wx0dvWAg9806gcUAxWQFqrn0WKD4bJ14M8AwDRSaNdVCfY7B+psbCDh T775ROUERYrZTumv4F3HNyvUOp58lEMr0ZMUb2d7H9XQlGDCKoszmThhYdkotT184POj UV8UG5Y/cD/bzTDgSRiUpaY3kc8tSagfqHUSERWDR9NYGfNkbJPw4aDw7Pxr1ncazO4A 95vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757800; x=1687349800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7tJgSrsfJjBPduQ55oOsMul7hMtXzANzGQOA9D+BS4Q=; b=XnrvT0+R7C+WnHdD7yuH2mudO81I4jXJiPvuPIEHMbGBfR2KrpthNteJhpHKXHal0v GDlig7/yFmil9d8Z7JQAgXZUbeeAVxj6GuhxjybZWZ6o4jJCAuN8IOn4fWEr88vtXbKS xHZfb56H31snT2Qoc0zD04kIhAngw3K7vWCG8q3eJ5rPNcmAS6dAbLHY7wO/5W/3aK/P 6b0Lzm1VluhBz857/tP7BGGDlF4mWQlJiiu2wJMNbUI/KguSRIUp1yVbS4ZF+vFkxBwD oNXdtuSi2tVJPz19eXdiahNS6n2nUuWBMKLQDJQ2gp3DxN/FRHKyZcLV2sG/uuTAnQ/D UJLA== X-Gm-Message-State: AC+VfDwzPCkY4usZdh1pqj7Z5AaD/ncJHzuU3fVGrzy9DnVC8guC/uuE GRnXCHv9wl0eMMhE2J8i4SI= X-Google-Smtp-Source: ACHHUZ72VmGhmmYTe0AopjokPSVMzaGVY/fJu0fyOgd/aAvX2GqtNUrGr+ViNueHkprxGWrI+408+w== X-Received: by 2002:a17:907:7f8c:b0:96a:5e38:ba49 with SMTP id qk12-20020a1709077f8c00b0096a5e38ba49mr10976896ejc.2.1684757799838; Mon, 22 May 2023 05:16:39 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:39 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 18/30] net: dsa: mt7530: remove .mac_port_config for MT7988 and make it optional Date: Mon, 22 May 2023 15:15:20 +0300 Message-Id: <20230522121532.86610-19-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL For the switch on the MT7988 SoC, the code in mac_port_config for MT7988 is not needed as the interface of the CPU port is already handled on mt7988_mac_port_get_caps(). Make .mac_port_config optional. Before calling priv->info->mac_port_config(), if there's no mac_port_config member in the priv->info table, exit mt753x_mac_config() successfully. Remove mac_port_config from the sanity check as the sanity check requires a pointer to a mac_port_config function to be non-NULL. This will fail for MT7988 as mac_port_config won't be a member of its info table. Co-developed-by: Daniel Golle Signed-off-by: Daniel Golle Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f017cc028183..99f5da8b27be 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2614,17 +2614,6 @@ static bool mt753x_is_mac_port(u32 port) return (port =3D=3D 5 || port =3D=3D 6); } =20 -static int -mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, - phy_interface_t interface) -{ - if (dsa_is_cpu_port(ds, port) && - interface =3D=3D PHY_INTERFACE_MODE_INTERNAL) - return 0; - - return -EINVAL; -} - static int mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2665,6 +2654,9 @@ mt753x_mac_config(struct dsa_switch *ds, int port, un= signed int mode, { struct mt7530_priv *priv =3D ds->priv; =20 + if (!priv->info->mac_port_config) + return 0; + return priv->info->mac_port_config(ds, port, mode, state->interface); } =20 @@ -3108,7 +3100,6 @@ const struct mt753x_info mt753x_table[] =3D { .phy_write_c45 =3D mt7531_ind_c45_phy_write, .cpu_port_config =3D mt7988_cpu_port_config, .mac_port_get_caps =3D mt7988_mac_port_get_caps, - .mac_port_config =3D mt7988_mac_config, }, }; EXPORT_SYMBOL_GPL(mt753x_table); @@ -3136,8 +3127,7 @@ mt7530_probe_common(struct mt7530_priv *priv) * properly. */ if (!priv->info->sw_setup || !priv->info->phy_read_c22 || - !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || - !priv->info->mac_port_config) + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps) return -EINVAL; =20 priv->id =3D priv->info->id; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD30FC77B73 for ; Mon, 22 May 2023 12:19:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233892AbjEVMTY (ORCPT ); Mon, 22 May 2023 08:19:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233714AbjEVMSN (ORCPT ); Mon, 22 May 2023 08:18:13 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4139E1BFC; Mon, 22 May 2023 05:16:49 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-96f50e26b8bso750867466b.2; Mon, 22 May 2023 05:16:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757803; x=1687349803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oOz3FMLGe/kTMEltMrvKqCCw9Yz4vcJ+Yr7EPAljZ3I=; b=fuq5xMh5QeKKUpQOPlVevL5RMj4Mdz0Tk5r/V+Yu3p+xhEmUXAbcglm14LFiiF9VlS S8kjR8VPmtEjfEZuv2ABY/Cn1QBNbs0pmScOZRUoUkY5bL3jc9EIW97xNRwrdv2e3IZh C+1GKM1j59M8cTCOLX5xnIm3V01MVJ86dxgj+t0daNrMcr0MfFD6hLcdqxp0wv8waVwx xqGzWNFwug5vjs4zIdeqAPPIYL+Z+vj37Q+Tqtaw9kd2t314MoyTxwtbtDH1r2AHyt4s Gl8gpcg+p+JD1dbJgx5Oc9vpulqPvih5H/D2gy8Ld/Gxz6OnUKycO7JBzzgD8aHvIoq8 hrsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757803; x=1687349803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oOz3FMLGe/kTMEltMrvKqCCw9Yz4vcJ+Yr7EPAljZ3I=; b=G7IDO29YMOmB8N4y0pNEp2f6luPslhjZAN7jDYM9Aeb8Xs3TA9204dEepPRtIJUihq w0lLHNjKxTrnF8E29iAsHEa9VJAIyksznNcMzHhqLai9SC2t683EpX9RTwcI502Gf/Og 1TQj+hwut47XL75zNFMzkv6sNg9jVMN2LVL9+qUrhzzNXMjCtdAE06HeaR8a/R+U9xDx Jbq+lx57BNBFCpjAcJWur8Xe5KIWtL5riIwZSibDgbhkST88Z+6HCfJ6ZMCAxe4oVTnU j+TRNrQMGSt+PuRB2MC1/YemU6S6uJwoZWCYinuA5s065dIviOn8nnu2ACKJbjgF1ULx F+Yw== X-Gm-Message-State: AC+VfDyrxEtZQlR+eSnUTNqhrxXpR0xTrC2V++dSptO3AVk/esuJLNEs R+PfNGtIP+QQRKB7JiPEBWlIfR2f1XzAq1Bv X-Google-Smtp-Source: ACHHUZ7axMa1F5LzzMgJRwk3Tc7YfoPBpyFJ6l9vcFkJW1FELcAvedTGajpVnr2j57Ka8knzp60tYw== X-Received: by 2002:a17:907:3604:b0:94f:6d10:ad9f with SMTP id bk4-20020a170907360400b0094f6d10ad9fmr9384418ejc.42.1684757802926; Mon, 22 May 2023 05:16:42 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:42 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 19/30] net: dsa: mt7530: set interrupt register only for MT7530 Date: Mon, 22 May 2023 15:15:21 +0300 Message-Id: <20230522121532.86610-20-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Setting this register related to interrupts is only needed for the MT7530 switch. Make an exclusive check to ensure this. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Tested-by: Daniel Golle Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 99f5da8b27be..0c261ef87bee 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2029,7 +2029,7 @@ mt7530_setup_irq(struct mt7530_priv *priv) } =20 /* This register must be set for MT7530 to properly fire interrupts */ - if (priv->id !=3D ID_MT7531) + if (priv->id =3D=3D ID_MT7530 || priv->id =3D=3D ID_MT7621) mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); =20 ret =3D request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31849C77B73 for ; Mon, 22 May 2023 12:19:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233964AbjEVMTb (ORCPT ); Mon, 22 May 2023 08:19:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233893AbjEVMST (ORCPT ); Mon, 22 May 2023 08:18:19 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D22951FCC; Mon, 22 May 2023 05:16:51 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-96fd3a658eeso186902566b.1; Mon, 22 May 2023 05:16:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757806; x=1687349806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=50+e+zsfVv5J1BqpAiWf9C7KcKligVVxQwX0YPFvKBI=; b=sjnpuNcMC4vPuNPM5W8qAKHq8laEr0IiAs8Yv8iF7D6XCl2l39DG4sCvemNN4DXMs3 ygsXI11bEbL4/sQHwESDh5EijbGBg0RFP7Bgk80DGY4cAwRo2iK+FiCX/ApZ+Pp5xjIH PoXGQ/fNfKgDR0sfgxwy/1E++kxv7CmxHSTppQ/sSAD/si0gUa4LHUf/78iNajzyzreo aRCWFhGX1GF6TLN/e+8vq6PeNM81ysMzgguyezsQRJ1g6kPblL8ZxH8mzUeRSvOUlbWP et0xQ/W7NAx3eCpXY2a52dWtedYRdKGxpOrP4dt1+TzYuTNxIoDpLv5/aKY8yyldcukJ ZHsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757806; x=1687349806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=50+e+zsfVv5J1BqpAiWf9C7KcKligVVxQwX0YPFvKBI=; b=RSwFH6BSD0flXgrcsVlVJ7eL7t1s/xe0M8Yaw7NqzKnOR+NENHL+8izlqPrnIj2XJp FsXWRepKoVsAt7NEY3BdCm0Mlr9TL/gS/g8C/7xPccTaGI1uOfZUzxbM9UFrNSGQZ3hD XTlhlj87XIwjd0DJhPM6q30jJTGDUBtqxlRBCDaQffEXcq1XBJLh6QmqitzYf4bHRLod 9l6Qh2FRH9naoSx5UefTwxlM0wcfkedfUa0sN2f3MYzC1mjZPMs+X8MlJDOEYpQacmuK LliEn/s59wXOXtMGYIsY9YKrxfo8o9a0x7/JpmgNbrQJVd+wEsipsars0YGy7warPMwL /bdA== X-Gm-Message-State: AC+VfDyu+8cQvc3bHeBk+HyTp0v32Nq7KVrWQ7HRJEcITfHTcjQXzxKm HXBm2cYQrXeAHBIJDO7BzVM= X-Google-Smtp-Source: ACHHUZ4M8Me0lXeuQHSHRWp3YouOQ/LLClhxE/remDAZsXN4DblDXCqROAKiLf/beTuFQ7E/eEU2Qw== X-Received: by 2002:a17:907:60ce:b0:96a:f21f:ab64 with SMTP id hv14-20020a17090760ce00b0096af21fab64mr8346390ejc.49.1684757806185; Mon, 22 May 2023 05:16:46 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:45 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 20/30] net: dsa: mt7530: properly reset MT7531 switch Date: Mon, 22 May 2023 15:15:22 +0300 Message-Id: <20230522121532.86610-21-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL According to the document MT7531 Reference Manual for Development Board v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for MT7531. This is likely why forcing link-down on the MACs is necessary for MT7531. Therefore, do not set SW_PHY_RST on mt7531_setup(). Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0c261ef87bee..aafb7415e2ce 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2416,14 +2416,12 @@ mt7531_setup(struct dsa_switch *ds) val =3D mt7530_read(priv, MT7531_TOP_SIG_SR); priv->p5_sgmii =3D !!(val & PAD_DUAL_SGMII_EN); =20 - /* all MACs must be forced link-down before sw reset */ + /* Force link-down on all MACs before internal reset */ for (i =3D 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); =20 /* Reset the switch through internal reset */ - mt7530_write(priv, MT7530_SYS_CTRL, - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | - SYS_CTRL_REG_RST); + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); =20 if (!priv->p5_sgmii) { mt7531_pll_setup(priv); --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25E89C77B75 for ; Mon, 22 May 2023 12:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233372AbjEVMTg (ORCPT ); Mon, 22 May 2023 08:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233798AbjEVMSV (ORCPT ); Mon, 22 May 2023 08:18:21 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA9F71FD8; Mon, 22 May 2023 05:16:55 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-96f683e8855so501064866b.2; Mon, 22 May 2023 05:16:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757809; x=1687349809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L7JBtEPSTsLOs/JWqoRR+gHqVNN2Pp1AK8gJa80nPkU=; b=VQzCHkaoUfd1TJA66iSSLvg+i2UzryWZ2LZ10vl37d3qhgdkC9STal6sT65wfEKHmM DVjbklaBuGxtD56ZSe6zMYkQMom6MnLrELVZJkA7UR/pvB1/wzdE7CwXt7g4R+c+Evpu LOkvUYAvYwycI0kma7g4cWkPUWRbP3N5+vxE0Fsgd/AxwvOlS7Z3FdvrTmvUDB39sHsw ivR8kfbOZdtXg59akv5vNisMMm2pwYHz2oZ1U20/74NgbfIzX7x3Ld1V6J1PHcbUHmBm UPoZEeemgso2mWxm8C6JoV7hM6ygaVNzaiydiRLxzCwEyvE7dpYoL4jUvuh1UK2cedFJ 38jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757809; x=1687349809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L7JBtEPSTsLOs/JWqoRR+gHqVNN2Pp1AK8gJa80nPkU=; b=czZJKodLdvEjpoMwKx+6umqBjZbec5neLwY56apcyETtlG3Id+dZiIxYzE6+Td+UXA d8AiRIypNVf8JzTVdGk3qbDkrZat/OC6gHGm85dHtZquZrT6f6WU3Otl2MmXDVSu1wOj fMnhIsUDzifIHvZehOmSAMMNNIZJnt4N9Gm2Gq06snyftmtYVI3KEPyxdfGwANCYgYNt Nqd/kTKhbnR9rU9lcXXCi09Y4EVZxDdC1RW9tKHq3EgRcSGOT4GttZ3r0udYVymKuzqR 4ikj7vFm4imRPbaTDNpAHijRE6umiNvPB7eUdja7Fl15F1ZvnVl+khXjOVuQt4TkakR6 K5UQ== X-Gm-Message-State: AC+VfDzBq2AkEBtNOVVusNMLmCVDgcbqYKIPFjM1yJVfp1NOSWz3nc3x QWJXKhC8i79gCk2KeC5hXuI= X-Google-Smtp-Source: ACHHUZ4ernIKsoBOw6M1XLrlLoJ0AnuWIqRtrMaNnZj1SxdtLoMWsiR3HBHRQqp1eZPA/qrftxlNng== X-Received: by 2002:a17:906:db04:b0:957:1df0:9cbf with SMTP id xj4-20020a170906db0400b009571df09cbfmr9202182ejb.19.1684757809148; Mon, 22 May 2023 05:16:49 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:48 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 21/30] net: dsa: mt7530: get rid of useless error returns on phylink code path Date: Mon, 22 May 2023 15:15:23 +0300 Message-Id: <20230522121532.86610-22-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Remove error returns on the cases where they are already handled with the function the mac_port_get_caps member points to. mt7531_mac_config() is also called from mt7531_cpu_port_config() outside of phylink but the port and interface modes are already handled there. Change the functions and the mac_port_config function pointer to void now that there're no error returns anymore. Remove mt753x_is_mac_port() that used to help the said error returns. On mt7531_mac_config(), switch to if statements to simplify the code. Remove internal phy cases from mt753x_phylink_mac_config() as there is no configuration to be done for them. There's also no need to check the interface mode as that's already handled with the function the mac_port_get_caps member points to. Remove the comments for port 5 and 6 as they're not really useful. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Acked-by: Daniel Golle Tested-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 85 +++++++++------------------------------- drivers/net/dsa/mt7530.h | 2 +- 2 files changed, 19 insertions(+), 68 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index aafb7415e2ce..996b8c02cb05 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2545,7 +2545,7 @@ static void mt7988_mac_port_get_caps(struct dsa_switc= h *ds, int port, } } =20 -static int +static void mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { @@ -2556,22 +2556,14 @@ mt7530_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, } else if (port =3D=3D 6) { mt7530_setup_port6(priv->ds, interface); } - - return 0; } =20 -static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, - phy_interface_t interface, - struct phy_device *phydev) +static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, + phy_interface_t interface, + struct phy_device *phydev) { u32 val; =20 - if (priv->p5_sgmii) { - dev_err(priv->dev, "RGMII mode is not available for port %d\n", - port); - return -EINVAL; - } - val =3D mt7530_read(priv, MT7531_CLKGEN_CTRL); val |=3D GP_CLK_EN; val &=3D ~GP_MODE_MASK; @@ -2599,20 +2591,14 @@ static int mt7531_rgmii_setup(struct mt7530_priv *p= riv, u32 port, case PHY_INTERFACE_MODE_RGMII_ID: break; default: - return -EINVAL; + break; } } - mt7530_write(priv, MT7531_CLKGEN_CTRL, val); =20 - return 0; -} - -static bool mt753x_is_mac_port(u32 port) -{ - return (port =3D=3D 5 || port =3D=3D 6); + mt7530_write(priv, MT7531_CLKGEN_CTRL, val); } =20 -static int +static void mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { @@ -2620,42 +2606,21 @@ mt7531_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, struct phy_device *phydev; struct dsa_port *dp; =20 - if (!mt753x_is_mac_port(port)) { - dev_err(priv->dev, "port %d is not a MAC port\n", port); - return -EINVAL; - } - - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: + if (phy_interface_mode_is_rgmii(interface)) { dp =3D dsa_to_port(ds, port); phydev =3D dp->slave->phydev; - return mt7531_rgmii_setup(priv, port, interface, phydev); - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_NA: - case PHY_INTERFACE_MODE_1000BASEX: - case PHY_INTERFACE_MODE_2500BASEX: - /* handled in SGMII PCS driver */ - return 0; - default: - return -EINVAL; + mt7531_rgmii_setup(priv, port, interface, phydev); } - - return -EINVAL; } =20 -static int +static void mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct mt7530_priv *priv =3D ds->priv; =20 - if (!priv->info->mac_port_config) - return 0; - - return priv->info->mac_port_config(ds, port, mode, state->interface); + if (priv->info->mac_port_config) + priv->info->mac_port_config(ds, port, mode, state->interface); } =20 static struct phylink_pcs * @@ -2684,30 +2649,18 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, in= t port, unsigned int mode, u32 mcr_cur, mcr_new; =20 switch (port) { - case 0 ... 4: /* Internal phy */ - if (state->interface !=3D PHY_INTERFACE_MODE_GMII && - state->interface !=3D PHY_INTERFACE_MODE_INTERNAL) - goto unsupported; - break; - case 5: /* Port 5, can be used as a CPU port. */ + case 5: if (priv->p5_configured) break; =20 - if (mt753x_mac_config(ds, port, mode, state) < 0) - goto unsupported; + mt753x_mac_config(ds, port, mode, state); break; - case 6: /* Port 6, can be used as a CPU port. */ + case 6: if (priv->p6_configured) break; =20 - if (mt753x_mac_config(ds, port, mode, state) < 0) - goto unsupported; + mt753x_mac_config(ds, port, mode, state); break; - default: -unsupported: - dev_err(ds->dev, "%s: unsupported %s port: %i\n", - __func__, phy_modes(state->interface), port); - return; } =20 mcr_cur =3D mt7530_read(priv, MT7530_PMCR_P(port)); @@ -2800,7 +2753,6 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int por= t) struct mt7530_priv *priv =3D ds->priv; phy_interface_t interface; int speed; - int ret; =20 switch (port) { case 5: @@ -2825,9 +2777,8 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int por= t) else speed =3D SPEED_1000; =20 - ret =3D mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); - if (ret) - return ret; + mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); + mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPU_PORT_SETTING(priv->id)); mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index f7a504e4c17b..b7f80a487073 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -722,7 +722,7 @@ struct mt753x_info { void (*mac_port_validate)(struct dsa_switch *ds, int port, phy_interface_t interface, unsigned long *supported); - int (*mac_port_config)(struct dsa_switch *ds, int port, + void (*mac_port_config)(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface); }; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84C76C77B75 for ; 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([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:51 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 22/30] net: dsa: mt7530: rename p5_intf_sel and use only for MT7530 switch Date: Mon, 22 May 2023 15:15:24 +0300 Message-Id: <20230522121532.86610-23-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The p5_intf_sel pointer is used to store the information of whether PHY muxing is used or not. PHY muxing is a feature specific to port 5 of the MT7530 switch. Do not use it for other switch models. Rename the pointer to p5_mode to store the mode the port is being used in. Rename the p5_interface_select enum to mt7530_p5_mode, the string representation to mt7530_p5_mode_str, and the enum elements. If PHY muxing is not detected, the default mode, GMAC5, will be used. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 61 ++++++++++++++++------------------------ drivers/net/dsa/mt7530.h | 15 +++++----- 2 files changed, 32 insertions(+), 44 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 996b8c02cb05..19afcd914109 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -868,19 +868,15 @@ mt7530_set_ageing_time(struct dsa_switch *ds, unsigne= d int msecs) return 0; } =20 -static const char *p5_intf_modes(unsigned int p5_interface) -{ - switch (p5_interface) { - case P5_DISABLED: - return "DISABLED"; - case P5_INTF_SEL_PHY_P0: - return "PHY P0"; - case P5_INTF_SEL_PHY_P4: - return "PHY P4"; - case P5_INTF_SEL_GMAC5: - return "GMAC5"; +static const char *mt7530_p5_mode_str(unsigned int mode) +{ + switch (mode) { + case MUX_PHY_P0: + return "MUX PHY P0"; + case MUX_PHY_P4: + return "MUX PHY P4"; default: - return "unknown"; + return "GMAC5"; } } =20 @@ -897,23 +893,21 @@ static void mt7530_setup_port5(struct dsa_switch *ds,= phy_interface_t interface) val |=3D MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &=3D ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; =20 - switch (priv->p5_intf_sel) { - case P5_INTF_SEL_PHY_P0: - /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ + switch (priv->p5_mode) { + case MUX_PHY_P0: + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ val |=3D MHWTRAP_PHY0_SEL; fallthrough; - case P5_INTF_SEL_PHY_P4: - /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ + case MUX_PHY_P4: + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ val &=3D ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; =20 /* Setup the MAC by default for the cpu port */ mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); break; - case P5_INTF_SEL_GMAC5: - /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ - val &=3D ~MHWTRAP_P5_DIS; - break; default: + /* GMAC5: P5 -> SoC MAC or external PHY */ + val &=3D ~MHWTRAP_P5_DIS; break; } =20 @@ -937,8 +931,8 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) =20 mt7530_write(priv, MT7530_MHWTRAP, val); =20 - dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, intf_sel=3D%s, phy-mode=3D%s\n= ", - val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); + dev_dbg(ds->dev, "Setup P5, HWTRAP=3D0x%x, mode=3D%s, phy-mode=3D%s\n", v= al, + mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); =20 mutex_unlock(&priv->reg_mutex); } @@ -2254,13 +2248,11 @@ mt7530_setup(struct dsa_switch *ds) if (ret) return ret; =20 - /* Setup port 5 */ - if (!dsa_is_unused_port(ds, 5)) { - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; - } else { + /* Check for PHY muxing on port 5 */ + if (dsa_is_unused_port(ds, 5)) { /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. - * Set priv->p5_intf_sel to the appropriate value if PHY muxing - * is detected. + * Set priv->p5_mode to the appropriate value if PHY muxing is + * detected. */ for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, @@ -2284,17 +2276,17 @@ mt7530_setup(struct dsa_switch *ds) } id =3D of_mdio_parse_addr(ds->dev, phy_node); if (id =3D=3D 0) - priv->p5_intf_sel =3D P5_INTF_SEL_PHY_P0; + priv->p5_mode =3D MUX_PHY_P0; if (id =3D=3D 4) - priv->p5_intf_sel =3D P5_INTF_SEL_PHY_P4; + priv->p5_mode =3D MUX_PHY_P4; } of_node_put(mac_np); of_node_put(phy_node); break; } =20 - if (priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P0 || - priv->p5_intf_sel =3D=3D P5_INTF_SEL_PHY_P4) + if (priv->p5_mode =3D=3D MUX_PHY_P0 || + priv->p5_mode =3D=3D MUX_PHY_P4) mt7530_setup_port5(ds, interface); } =20 @@ -2433,9 +2425,6 @@ mt7531_setup(struct dsa_switch *ds) MT7531_EXT_P_MDIO_12); } =20 - if (!dsa_is_unused_port(ds, 5)) - priv->p5_intf_sel =3D P5_INTF_SEL_GMAC5; - mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index b7f80a487073..216081fb1c12 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -673,12 +673,11 @@ struct mt7530_port { struct phylink_pcs *sgmii_pcs; }; =20 -/* Port 5 interface select definitions */ -enum p5_interface_select { - P5_DISABLED, - P5_INTF_SEL_PHY_P0, - P5_INTF_SEL_PHY_P4, - P5_INTF_SEL_GMAC5, +/* Port 5 mode definitions of the MT7530 switch */ +enum mt7530_p5_mode { + GMAC5, + MUX_PHY_P0, + MUX_PHY_P4, }; =20 struct mt7530_priv; @@ -746,7 +745,7 @@ struct mt753x_info { * is already configured * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch * is already configured - * @p5_intf_sel: Holding the current port 5 interface select + * @p5_mode: Holding the current mode of port 5 of the MT7530 switch * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII * @irq: IRQ number of the switch @@ -768,7 +767,7 @@ struct mt7530_priv { bool mcm; bool p6_configured; bool p5_configured; - enum p5_interface_select p5_intf_sel; + enum mt7530_p5_mode p5_mode; bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF7D7C77B75 for ; Mon, 22 May 2023 12:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233419AbjEVMUh (ORCPT ); Mon, 22 May 2023 08:20:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233906AbjEVMSc (ORCPT ); Mon, 22 May 2023 08:18:32 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 477401FE2; Mon, 22 May 2023 05:16:58 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-96f850b32caso556726766b.3; Mon, 22 May 2023 05:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757815; x=1687349815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4hNEGPM/k2Wei/lMuV138s3+HJRM8F0X5AH8IxuRIA=; b=fgTbTLbrzx4eo36no/L8MljlJBC1raKbuJH3jDHYd9gnY9AhIubXn/hHbnFm1TkYov rplpfCyGp1bgCgmoFg8GxDhr88mrhioacmZ2cH9/K59E6zaHJNIw6HVOXGkCnaMDmVHL IuKBK+g0SLZLZXW0tLFZ/Cjhbvq3/uGzlwd+drhLVd0mBTwzMLRFmyXPSkYNkoRANEo7 Zr2zuRM1nrPhO1FZ10STqdJUhxFbt2TyLEDUf8uJJdeUqZCs1XEcm1oz1Q/ulHiUgIpN 7jIDvc0F2RS7UanOrmUoIlX6kbkgozgyVfO9mCQ0+tf2XOEpf5jvQS4NZ2XWYIU1oWX+ RNaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757815; x=1687349815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4hNEGPM/k2Wei/lMuV138s3+HJRM8F0X5AH8IxuRIA=; b=ejsF6PdzbMKC0BI2yA/giOsmn8gMd1kK0h2J61B0OzDyaDoC5S5BE45rfnqlRm8uYE 6izaJ9tMLRpT1nddKcOBj5Xt+qD6HHuWdyZ8oqmZXIaJHoM5ahYFgS81ZOiVDnWov3ui +Q4lPlCBVHJHc8azbfLrF0RESvtEn4Q5Mwxm7UPp0pOLBaQsvsauKX0ZUe7WD/N1JYzn fISOPNKTVv4OTgI/mOwaNOdT4RqlGGur0o2F2IlolvqIux/iX3Muy+Ts63Vb+LaTlAo8 6YA+Nz4HZtFr3pp0bbxROhtP6HGNQD2FSDNLYmBRcc3G5iVYK6QHM7bzcFpcrg5D1vGX VMVA== X-Gm-Message-State: AC+VfDy89cw/IhL/IBMgpNB9YjBqK3TSNhFYlRwxS3vrm8y+F0SCzbRD 8rHfBz5TJmXZM3swr6sSSiI= X-Google-Smtp-Source: ACHHUZ5m37/bUe5mAu+tGniN6yeCVXzYQceZL78+LqffaXJuXJdXrKLQp107cXJA8y5v2VuUCLVyAQ== X-Received: by 2002:a17:907:60d4:b0:94e:c8c:42ec with SMTP id hv20-20020a17090760d400b0094e0c8c42ecmr10735915ejc.20.1684757815127; Mon, 22 May 2023 05:16:55 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:54 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 23/30] net: dsa: mt7530: run mt7530_pll_setup() only with 40 MHz XTAL Date: Mon, 22 May 2023 15:15:25 +0300 Message-Id: <20230522121532.86610-24-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The code on mt7530_pll_setup() needs to be run only on the MT7530 switch with a 40 MHz oscillator. Introduce a check to do this. Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a287= 2fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L10= 39 Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 19afcd914109..9a4d4413287a 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2197,7 +2197,8 @@ mt7530_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); =20 - mt7530_pll_setup(priv); + if (xtal =3D=3D HWTRAP_XTAL_40MHZ) + mt7530_pll_setup(priv); =20 /* Lower P5 RGMII Tx driving, 8mA */ mt7530_write(priv, MT7530_IO_DRV_CR, --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E634DC7EE2A for ; Mon, 22 May 2023 12:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233867AbjEVMUk (ORCPT ); Mon, 22 May 2023 08:20:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233857AbjEVMSc (ORCPT ); Mon, 22 May 2023 08:18:32 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3B511FE3; Mon, 22 May 2023 05:16:58 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-96f683e8855so501095966b.2; Mon, 22 May 2023 05:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757818; x=1687349818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oPhQTZxBab4ufG3A5RcvU+2T8JQbUsDstYw6d3ZLLiw=; b=Vh2gMaMcDU8jGTAJ64+I6w7OsRyuFmSt4rWAK1dxNrOoY9tIiRuU75044JIdRePTtO NuRK1ZHTVhCCWtrymhT+r6VRukrylRNlGD+PQH/caFXbgixM+lB0fDK2DQ6EZiXRhHPb UzdUqwE+r5aTFsVajGP/AgxFxVZ9BWteFm9DrJo2B1465B8RZL71FjHyxbeQ292Eyhow JGJb6P/0XbaNmrQ+1mniEKkOxIxeAxZy82IpErLbGpDJRqEytQjhiXEL3T2+ECEeDx8x mLxzeIBcMuZn3CxBkCMXqt+emUL24ACR+Gzcv8yabzwR+2HXUwFweAVdFSwE8Mwzj8jm /02Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757818; x=1687349818; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oPhQTZxBab4ufG3A5RcvU+2T8JQbUsDstYw6d3ZLLiw=; b=My6AKMX6vqqbrGxXhoHQBMc/g9CvtQkyCr/SrmQ7s1WV3RaE65xBdCmgs6X43HEodJ tHy+xgRGVfqRAtXD8E1ecQonPnB2RlbDBaho/fUJNJVjK3woPM2IySVHU/YSul37ATSK qinrCkhI3wrKoLZKtmasgqQihVsJMNsCveUYCWbTWk9Z/LVC8t3lsjnKZDg6rNl6W8OE Gy55JAj/gD32r9ezhSNiuWNBUCCtSSkQC5Lkij1RDnun8EMnROnAk2Y3HM4yuO63cMPf dklnkUDXCeQUhMkNgHKkBURmp/+3AfVkWu9920CpqZEOVuf/+YyESqsQ2S05z2lnJ3XE j0vw== X-Gm-Message-State: AC+VfDx3f4DZpDRgh2lizuY6Kg9iTK10ho/EbK/GAv1DydUo4jK7Yq6K XzbKwQl7JltYVTslDrn1f504PnJpTNNtkR56 X-Google-Smtp-Source: ACHHUZ61QvAvaJ6JXwAl5ZK+Z+iWCx3i0ErjlAje5iGoTtpti1TXdrNI1eenVMW0q+/1TTrQZTvoBQ== X-Received: by 2002:a17:907:ea3:b0:96f:f451:187f with SMTP id ho35-20020a1709070ea300b0096ff451187fmr2155579ejc.7.1684757818084; Mon, 22 May 2023 05:16:58 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:16:57 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 24/30] net: dsa: mt7530: rename MT7530_MFC to MT753X_MFC Date: Mon, 22 May 2023 15:15:26 +0300 Message-Id: <20230522121532.86610-25-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988 SoC. Some bits are for MT7530 only. Call the shared ones MT753X, the MT7530-specific ones MT7530. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 30 +++++++++++++++------------ drivers/net/dsa/mt7530.h | 44 ++++++++++++++++++++-------------------- 2 files changed, 39 insertions(+), 35 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 9a4d4413287a..58d8738d94d3 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -955,12 +955,13 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int por= t) PORT_SPEC_TAG); =20 /* Enable flooding on the CPU port */ - mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | - UNU_FFP(BIT(port))); + mt7530_set(priv, MT753X_MFC, MT753X_BC_FFP(BIT(port)) | + MT753X_UNM_FFP(BIT(port)) | MT753X_UNU_FFP(BIT(port))); =20 /* Set CPU port number */ if (priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); + mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_MASK, MT7530_CPU_EN | + MT7530_CPU_PORT(port)); =20 /* CPU port gets connected to all user ports of * the switch. @@ -1120,16 +1121,19 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int= port, flags.val & BR_LEARNING ? 0 : SA_DIS); =20 if (flags.mask & BR_FLOOD) - mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), - flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_UNU_FFP(BIT(port)), + flags.val & BR_FLOOD ? + MT753X_UNU_FFP(BIT(port)) : 0); =20 if (flags.mask & BR_MCAST_FLOOD) - mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), - flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_UNM_FFP(BIT(port)), + flags.val & BR_MCAST_FLOOD ? + MT753X_UNM_FFP(BIT(port)) : 0); =20 if (flags.mask & BR_BCAST_FLOOD) - mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), - flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); + mt7530_rmw(priv, MT753X_MFC, MT753X_BC_FFP(BIT(port)), + flags.val & BR_BCAST_FLOOD ? + MT753X_BC_FFP(BIT(port)) : 0); =20 return 0; } @@ -1667,13 +1671,13 @@ mt7530_port_vlan_del(struct dsa_switch *ds, int por= t, static int mt753x_mirror_port_get(unsigned int id, u32 val) { return (id =3D=3D ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : - MIRROR_PORT(val); + MT7530_MIRROR_PORT(val); } =20 static int mt753x_mirror_port_set(unsigned int id, u32 val) { return (id =3D=3D ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : - MIRROR_PORT(val); + MT7530_MIRROR_PORT(val); } =20 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, @@ -2327,8 +2331,8 @@ mt7531_setup_common(struct dsa_switch *ds) mt7530_mib_reset(ds); =20 /* Disable flooding on all ports */ - mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | - UNU_FFP_MASK); + mt7530_clear(priv, MT753X_MFC, MT753X_BC_FFP_MASK | MT753X_UNM_FFP_MASK + | MT753X_UNU_FFP_MASK); =20 for (i =3D 0; i < MT7530_NUM_PORTS; i++) { /* Disable forwarding by default on all ports */ diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 216081fb1c12..5ebb942b07ef 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -32,35 +32,35 @@ enum mt753x_id { #define SYSC_REG_RSTCTRL 0x34 #define RESET_MCM BIT(2) =20 -/* Registers to mac forward control for unknown frames */ -#define MT7530_MFC 0x10 -#define BC_FFP(x) (((x) & 0xff) << 24) -#define BC_FFP_MASK BC_FFP(~0) -#define UNM_FFP(x) (((x) & 0xff) << 16) -#define UNM_FFP_MASK UNM_FFP(~0) -#define UNU_FFP(x) (((x) & 0xff) << 8) -#define UNU_FFP_MASK UNU_FFP(~0) -#define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) -#define MIRROR_EN BIT(3) -#define MIRROR_PORT(x) ((x) & 0x7) -#define MIRROR_MASK 0x7 - -/* Registers for CPU forward control */ +/* Register for MAC forward control */ +#define MT753X_MFC 0x10 +#define MT753X_BC_FFP(x) (((x) & 0xff) << 24) +#define MT753X_BC_FFP_MASK MT753X_BC_FFP(~0) +#define MT753X_UNM_FFP(x) (((x) & 0xff) << 16) +#define MT753X_UNM_FFP_MASK MT753X_UNM_FFP(~0) +#define MT753X_UNU_FFP(x) (((x) & 0xff) << 8) +#define MT753X_UNU_FFP_MASK MT753X_UNU_FFP(~0) +#define MT7530_CPU_EN BIT(7) +#define MT7530_CPU_PORT(x) ((x) << 4) +#define MT7530_CPU_MASK (0xf << 4) +#define MT7530_MIRROR_EN BIT(3) +#define MT7530_MIRROR_PORT(x) ((x) & 0x7) +#define MT7530_MIRROR_MASK 0x7 + +/* Register for CPU forward control */ #define MT7531_CFC 0x4 #define MT7531_MIRROR_EN BIT(19) -#define MT7531_MIRROR_MASK (MIRROR_MASK << 16) -#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) -#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) +#define MT7531_MIRROR_MASK (0x7 << 16) +#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & 0x7) +#define MT7531_MIRROR_PORT_SET(x) (((x) & 0x7) << 16) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ - MT7531_CFC : MT7530_MFC) + MT7531_CFC : MT753X_MFC) #define MT753X_MIRROR_EN(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D ID= _MT7988)) ? \ - MT7531_MIRROR_EN : MIRROR_EN) + MT7531_MIRROR_EN : MT7530_MIRROR_EN) #define MT753X_MIRROR_MASK(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D = ID_MT7988)) ? \ - MT7531_MIRROR_MASK : MIRROR_MASK) + MT7531_MIRROR_MASK : MT7530_MIRROR_MASK) =20 /* Registers for BPDU and PAE frame control*/ #define MT753X_BPC 0x24 --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6DDBC77B73 for ; Mon, 22 May 2023 12:20:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233468AbjEVMUm (ORCPT ); Mon, 22 May 2023 08:20:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232821AbjEVMSg (ORCPT ); Mon, 22 May 2023 08:18:36 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB1E9CD; Mon, 22 May 2023 05:17:01 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-96f588bc322so587709766b.1; Mon, 22 May 2023 05:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757821; x=1687349821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V9tpdUvQNrY+vXu1QgfXUo403K9j/yDPqK1JzzKX9TY=; b=q/+t+61YH1yRLDRJJOPmPwfYDM0nR2iAwN298kG0G6zmP9vpFPXhIHdNDzkdUd48l/ cwN6osMyujFwj9quQ6Mtsi8e0J6fK2EcekhZ5NI2Fy4o6LfpS7sxMvHuKPS/CA6TUtxl 873vrc68tsP58h5nIdlh1ZB2RXtaTmOT/4BmyCexQmjYNvwKx/pPFFHp4fkwE0R6HtaR gv+qXYYj6ax+RsWDq2Qjx8GFM9k/kVueB83PuKVI1LuAkEMwSR6Wr3WbXVoTl/Nh6E7J BYO8AW4KFY0NNwhPTu97qaEn0/4VLOCxrfhqk953FaUHq74O91UbEYPHlE/lOPeoQTRu tugA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757821; x=1687349821; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V9tpdUvQNrY+vXu1QgfXUo403K9j/yDPqK1JzzKX9TY=; b=XcjNgUnJul6siSgd8dbv0gsKndzRp3lhDUXfQPF2lu8fjf6wjpHEtdjkp4PsadaEk1 hQHfLM1Orv1omGvyb+NSD4d98dXJc8RmW+UkwWttUqvGPk9GS1cB1cXX3eiFWg7Lv0X1 UZxaenViQvIz4iYAPu46MNAgPwLst7yDErotwP9S1aOZnKg9xlo03glDltsqoVweh37D RgsB7F8SoIUvn5yE+JbdOayJz3EA/fMId2+7WISpzzuZxhwE7t9RaYZoO/h7Ky8iAALc TB8IohO7Doyx+84RQa5HnJ5BfG+7Wn6D2JZY9JoFrse0osv8sOT6jKNSyxUb5SrZVbP6 I1zw== X-Gm-Message-State: AC+VfDxQfhkorqVSQog2h04ezekDGFgbVN29vZxW7QeWy5/MSyzKnoLB 7fEIis9VUznzMfMYyG4Fmcs= X-Google-Smtp-Source: ACHHUZ7AzgOwwMT64Nky0TTC6ZmE3dmOJIVkxkaYdVOAOo9F1zIfL1k1AU/yDAPVy4izH3/6gBiQ8A== X-Received: by 2002:a17:907:7246:b0:96a:ee54:9f20 with SMTP id ds6-20020a170907724600b0096aee549f20mr10610920ejc.37.1684757821114; Mon, 22 May 2023 05:17:01 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.16.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:00 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 25/30] net: dsa: mt7530: properly set MT7531_CPU_PMAP Date: Mon, 22 May 2023 15:15:27 +0300 Message-Id: <20230522121532.86610-26-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Every bit of the CPU port bitmap for MT7531 and the switch on the MT7988 SoC represents a CPU port to trap frames to. Currently only the bit that corresponds to the first found CPU port is set on the bitmap. Introduce the MT7531_CPU_PMAP macro to individually set the bits of the CPU port bitmap. Set the CPU port bitmap for MT7531 and the switch on the MT7988 SoC on mt753x_cpu_port_enable() which runs on a loop for each CPU port. Add comments to explain this. According to the document MT7531 Reference Manual for Development Board v1.0, the MT7531_CPU_PMAP bits are unset after reset so no need to clear it beforehand. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 15 ++++++++------- drivers/net/dsa/mt7530.h | 3 ++- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 58d8738d94d3..0b513e3628fe 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -963,6 +963,13 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_MASK, MT7530_CPU_EN | MT7530_CPU_PORT(port)); =20 + /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on + * the MT7988 SoC. Any frames set for trapping to CPU port will be + * trapped to the CPU port the user port is affine to. + */ + if (priv->id =3D=3D ID_MT7531 || priv->id =3D=3D ID_MT7988) + mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); + /* CPU port gets connected to all user ports of * the switch. */ @@ -2315,15 +2322,9 @@ static int mt7531_setup_common(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; - struct dsa_port *cpu_dp; int ret, i; =20 - /* BPDU to CPU port */ - dsa_switch_for_each_cpu_port(cpu_dp, ds) { - mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, - BIT(cpu_dp->index)); - break; - } + /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, MT753X_BPDU_CPU_ONLY); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5ebb942b07ef..fd2a2f726b8a 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -53,7 +53,8 @@ enum mt753x_id { #define MT7531_MIRROR_MASK (0x7 << 16) #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & 0x7) #define MT7531_MIRROR_PORT_SET(x) (((x) & 0x7) << 16) -#define MT7531_CPU_PMAP_MASK GENMASK(7, 0) +#define MT7531_CPU_PMAP(x) ((x) & 0xff) +#define MT7531_CPU_PMAP_MASK MT7531_CPU_PMAP(~0) =20 #define MT753X_MIRROR_REG(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D I= D_MT7988)) ? \ MT7531_CFC : MT753X_MFC) --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21156C77B75 for ; Mon, 22 May 2023 12:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233874AbjEVMUp (ORCPT ); Mon, 22 May 2023 08:20:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232730AbjEVMTN (ORCPT ); Mon, 22 May 2023 08:19:13 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 252CDE0; Mon, 22 May 2023 05:17:06 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-96fb45a5258so345352666b.2; Mon, 22 May 2023 05:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757824; x=1687349824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WPQmGsbOPIy9wPstzIBKggjPnfoTVHg5cTQKcX+NZkA=; b=fx8uQ3GYpgRsHyL6dZtp9/EUw/x7/v2NuHFv1Fck7p8yRfR2+KxdHdS5+fR38zWink u+GlxOuK0KczPi5WbnTYbRL/djIGyQCkePQ89NngPwMQrudlDBnolgm5G1oHaaakwPxm LR18qpdlQquOZsYlAP13riLQOeBZ5xFNOeqsVdkV5FqPP5uW3kNAmGbgf65HJMSzIA3+ tctwHZWLyvC375W34wStBbYMSPLAYfXt6os0VVaa/u4faCPf4UXTTxxExUGJacy1d33h /q/zSFPZ9UGNYK3EqCIi4jfsxexgNbYc4gvHZWE/t1kROWGvinFlre0rvJv31MtoOhLW zDGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757824; x=1687349824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WPQmGsbOPIy9wPstzIBKggjPnfoTVHg5cTQKcX+NZkA=; b=HuE/TdzaRQYATkJtteabmzMQJJyXQGOtwpU5LkLwmtYa2eWl/5VwaV16tXx97FWdon ziFInOKXDuPkP0Zq1m/tnj7X8vfhIoacx4DOOeW0QVitMkX83x/4V/r1Ld0bzwbomo1D +kxWLq9hHoFYda+gCRciqPTacW11H/WnHM0G6vibxtQtRiujMFJRep2KkBihmnitttbE OVmGKXcFkGuS4eDJZdCp/BDwUjeHgCgoGJU9Cw8TRJ1BvV4z3MUqtndZgWXd3RL3x0JW +VQv+fZTzaQbbqDo0qckLs98Z+idjYn9UTnvQLRrLy3c7lIIQQuCs3YM8hGTI7d+K1tW BGVQ== X-Gm-Message-State: AC+VfDxPRFt9VmjbSw+D84zeYBG3s7gYsFAbiTT1F7s/yju93+TEnZ0q t/E41JqjYkp27+dEUL0DPXw= X-Google-Smtp-Source: ACHHUZ6I1A9bM1EEvi1AGJ9bLFYnfQ5/p5HefY45mD7dPiufH15Hn+5UFV+U6lPAjEgw7X1qcuVXkg== X-Received: by 2002:a17:907:8390:b0:953:37eb:7727 with SMTP id mv16-20020a170907839000b0095337eb7727mr7799238ejc.43.1684757824116; Mon, 22 May 2023 05:17:04 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:03 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 26/30] net: dsa: mt7530: properly set MT7530_CPU_PORT Date: Mon, 22 May 2023 15:15:28 +0300 Message-Id: <20230522121532.86610-27-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT7530_CPU_PORT bits represent the CPU port to trap frames to for the MT7530 switch. There are two issues with the current way of setting these bits. ID_MT7530 which is for the standalone MT7530 switch is not included. When multiple CPU ports are being used, the trapped frames won't be received when the DSA conduit interface, which the frames are supposed to be trapped to, is down because it's not affine to any user port. This requires the DSA conduit interface to be manually set up for the trapped frames to be received. Address these issues by implementing ds->ops->master_state_change() on this subdriver and setting the MT7530_CPU_PORT bits there. Introduce the active_cpu_ports field to store the information of active CPU ports. Correct the macros, MT7530_CPU_PORT is bits 4 through 6 of the register. Any frames set for trapping to CPU port will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is set up. To make the understatement obvious, the frames won't necessarily be trapped to the CPU port the user port, which these frames are received from, is affine to. This operation is only there to make sure the trapped frames always reach the CPU. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Co-developed-by: Vladimir Oltean Signed-off-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 33 ++++++++++++++++++++++++++++----- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0b513e3628fe..cd16911fcb01 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -958,11 +958,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int port) mt7530_set(priv, MT753X_MFC, MT753X_BC_FFP(BIT(port)) | MT753X_UNM_FFP(BIT(port)) | MT753X_UNU_FFP(BIT(port))); =20 - /* Set CPU port number */ - if (priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_MASK, MT7530_CPU_EN | - MT7530_CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Any frames set for trapping to CPU port will be * trapped to the CPU port the user port is affine to. @@ -2947,6 +2942,33 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 +static void +mt753x_master_state_change(struct dsa_switch *ds, + const struct net_device *master, + bool operational) +{ + struct mt7530_priv *priv =3D ds->priv; + struct dsa_port *cpu_dp =3D master->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. There can be only one + * CPU port due to MT7530_CPU_PORT having only 3 bits. Any frames set + * for trapping to CPU port will be trapped to the numerically smallest + * CPU port which is affine to the DSA conduit interface that is set up. + */ + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |=3D BIT(cpu_dp->index); + else + priv->active_cpu_ports &=3D ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | + MT7530_CPU_PORT_MASK, MT7530_CPU_EN | + MT7530_CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv =3D ds->priv; @@ -2996,6 +3018,7 @@ const struct dsa_switch_ops mt7530_switch_ops =3D { .phylink_mac_link_up =3D mt753x_phylink_mac_link_up, .get_mac_eee =3D mt753x_get_mac_eee, .set_mac_eee =3D mt753x_set_mac_eee, + .master_state_change =3D mt753x_master_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index fd2a2f726b8a..52e5d71a04d3 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define MT753X_UNU_FFP(x) (((x) & 0xff) << 8) #define MT753X_UNU_FFP_MASK MT753X_UNU_FFP(~0) #define MT7530_CPU_EN BIT(7) -#define MT7530_CPU_PORT(x) ((x) << 4) -#define MT7530_CPU_MASK (0xf << 4) +#define MT7530_CPU_PORT(x) (((x) & 0x7) << 4) +#define MT7530_CPU_PORT_MASK MT7530_CPU_PORT(~0) #define MT7530_MIRROR_EN BIT(3) #define MT7530_MIRROR_PORT(x) ((x) & 0x7) #define MT7530_MIRROR_MASK 0x7 @@ -753,6 +753,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -780,6 +781,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv); + unsigned long active_cpu_ports; }; =20 struct mt7530_hw_vlan_entry { --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0B1BC77B75 for ; Mon, 22 May 2023 12:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233919AbjEVMUv (ORCPT ); Mon, 22 May 2023 08:20:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233890AbjEVMTV (ORCPT ); Mon, 22 May 2023 08:19:21 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4CF3C1703; Mon, 22 May 2023 05:17:09 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-96f5d651170so717215666b.1; Mon, 22 May 2023 05:17:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757827; x=1687349827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BR4WaMfs6beJCKcHWOQHHYOIrYTJQ7SOSyqfSGCZK48=; b=nwiwhL23+3X1oPllcBS1eFqvx6YOW0qrnjo6coLOpG+/Db0N6PmxOO20Bgw4/Ko7jC NNQFp+/ri7bHwwBz1/mJDxdeV7ipq02QonFCuub9e8XWjjowcJenASuiwMeUCw7AmKBq ZTd7O2Nbd9X1aRA1nGMwka7Cu/XaR7hXZxF4WzI+1gTuK3kFppDxa5C+QUxNnmp8L49h ZRJepRgXz5UXIkIh9T2ToZJIfwb5dZYtSxMf994Xd1X2OO6S6XpTcyUS7S7P1o5LreyU Nv87UeNeTA4S9RSGc5qa8+EULyB46WbQOvE5VuO5jQuqp7gNlsRVEegDRBiChqB+ds3h IhlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757827; x=1687349827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BR4WaMfs6beJCKcHWOQHHYOIrYTJQ7SOSyqfSGCZK48=; b=Wk88Isiivb+N5CnrhVjc5D3RWdK0vQn3ZYyVUtCLQ7xbmZpBTkdACZSkJSC7Dzxf0h //oNQnEyHs6jNb7M9u/9QxOP+maL4z0qXWy9OzHM/5lVrNAGOdqKxxnXcW0jsvUBrVuW guElToUQBQ9yCSLcJ3r2FFkIESxYS3sQeRrLTHGxPjGlH0VX8KB5wBuG3u5/ZsvgBL3w psKlEnejZh8stISxq80gxfFCnl7pK4Bc9bYKA68njkm0JbGSy9zEPSRFFQnEK3hc9dJF GC9NAqab1Lq625/KHlCV8ELnEpzA3gg7rgmkLueZF3EahyUwj0VRczx3CAz9fVgwdEtC YpTA== X-Gm-Message-State: AC+VfDzK/aLNkopz1biCb1NipLknuhZfbguHOA6wZBJGSmBi+2yvmJ8/ 4gQqM9kk4Z+RfIDULLO0bpg= X-Google-Smtp-Source: ACHHUZ56qzah9yxHVqSw1YLNAtp+w9qL77H/bmaw8t3TgdQHUL42y3kfN0W7hPVk5MauUttl9OVMrA== X-Received: by 2002:a17:907:7211:b0:96f:8afc:b310 with SMTP id dr17-20020a170907721100b0096f8afcb310mr6981274ejc.3.1684757827140; Mon, 22 May 2023 05:17:07 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:06 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 27/30] net: dsa: mt7530: introduce BPDU trapping for MT7530 switch Date: Mon, 22 May 2023 15:15:29 +0300 Message-Id: <20230522121532.86610-28-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT753X switches are capable of trapping certain frames. Introduce trapping BPDUs to the CPU port for the MT7530 switch. BPDUs will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is set up. The BPDUs won't necessarily be trapped to the CPU port the user port, which these BPDUs are received from, is affine to. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index cd16911fcb01..2fb4b0bc6335 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2223,6 +2223,10 @@ mt7530_setup(struct dsa_switch *ds) val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 + /* Trap BPDUs to the CPU port */ + mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, + MT753X_BPDU_CPU_ONLY); + /* Enable and reset MIB counters */ mt7530_mib_reset(ds); =20 --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C7C4C77B73 for ; Mon, 22 May 2023 12:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233939AbjEVMUy (ORCPT ); Mon, 22 May 2023 08:20:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233475AbjEVMTb (ORCPT ); Mon, 22 May 2023 08:19:31 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDFE9170E; Mon, 22 May 2023 05:17:10 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-96f6e83e12fso489794466b.1; Mon, 22 May 2023 05:17:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757830; x=1687349830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HqRoVOW5ATPKkmSDchjmJB2cTgfNIDW4SGp9tBnvP0Q=; b=pUw4uKIUNJh5QEQn8is2R/h6lUbhpzqig1b4ddexVTPPD9XVIqJ9g/wMetQyRjn/s7 iyIKR2mc40MhSUcoC26nUXn9ZJgchgDimE5YicIDCx2k72qNqSvIfXw8XSbIm0nZjI/2 ZNKZvbWbdT7tUqstSqQQuknQZ+KQVxgJljPqP8DsyHGp00yDl/FmeJ2tOO0QVn8LfqJ8 cqNZjEBvuMLPRx7VkW9vxZESHTDhL0JR4mrys+CwGHuaM5WfD4PDegQPyLj2RuAJ7gEi DDtuYHcfsS9wxf8QoW7c3BS6C0EvcavSrBErQHu0xHwiqKp/M7qqwKR5whWOaTBjpIav mMWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757830; x=1687349830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HqRoVOW5ATPKkmSDchjmJB2cTgfNIDW4SGp9tBnvP0Q=; b=JYvSQoeJaF5xismkStu+24We8S7Z4j8kAWCLCE/rt39gtgqYAllnXg/Ll9NGPA+WQM euqgUMtAL72AcGA60jSeylaSJk6k4WFE1Q5X5LsyNgBPFmOkJHHHfrYpXjr1WVNHs/TR WEUBGnPkvRazRFy4wXARb+lTi/HAjEsOy0VjAq/1W1nNo1gEfDKBn+2G4ChS98lcRX40 dWa8gHdStfLiE+JII9LRoVAfkyDrlLZOayfI+ysiaekLPrZT7PrQxPGJbX5iNPaDV5r6 7UfNWgvJ3N5f5PgoDNWD1z5gMeX+rN2eTvTA8xgdj4nfXocCgvRARa99UTs6CmEJrUWQ 5gvg== X-Gm-Message-State: AC+VfDzspjaMGd4wpfXww6p25Ma8KvUrtOuKW9qVT3pqxNpSRlO+2I0S x37zDW81wpfbsEcANLUCQnE= X-Google-Smtp-Source: ACHHUZ7S5doXEQbzc7jj+Nwm/KeUfeIBOBxtvMLCkdUE7EEsyV+Swmuat4wLSM2bpWQovi+wxudbjQ== X-Received: by 2002:a17:907:25c2:b0:96f:8439:6143 with SMTP id ae2-20020a17090725c200b0096f84396143mr7741710ejc.40.1684757830174; Mon, 22 May 2023 05:17:10 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.17.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:09 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 28/30] net: dsa: mt7530: introduce LLDP frame trapping Date: Mon, 22 May 2023 15:15:30 +0300 Message-Id: <20230522121532.86610-29-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL The MT753X switches are capable of trapping certain frames. Introduce trapping LLDP frames to the CPU port(s) for the MT753X switches. For MT7530, LLDP frames will be trapped to the numerically smallest CPU port which is affine to the DSA conduit interface that is set up. The LLDP frames won't necessarily be trapped to the CPU port the user port, which these LLDP frames are received from, is affine to. For MT7531 and the switch on the MT7988 SoC, LLDP frames will be trapped to the CPU port the user port is affine to. The bit for R0E_MANG_FR is 27. When set, the switch regards the frames with :0E MAC DA as management (LLDP) frames. This bit is set to 1 after reset on MT7530 and MT7531 according to the documents MT7620 Programming Guide v1.0 and MT7531 Reference Manual for Development Board v1.0, so there's no need to deal with this bit. Since there's currently no public document for the switch on the MT7988 SoC, I assume this is also the case for this switch. Remove the ETHSYS_CLKCFG0 register which doesn't exist on the said documents, and conflicts with the MT753X_RGAC2 register. The mt753x_bpdu_port_fw enum is universally used for trapping frames, therefore rename it and the values in it to mt753x_port_fw. Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 12 ++++++++++-- drivers/net/dsa/mt7530.h | 23 ++++++++++++----------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2fb4b0bc6335..8f5a8803cb33 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2225,7 +2225,11 @@ mt7530_setup(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -2325,7 +2329,11 @@ mt7531_setup_common(struct dsa_switch *ds) =20 /* Trap BPDUs to the CPU port(s) */ mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, - MT753X_BPDU_CPU_ONLY); + MT753X_PORT_FW_CPU_ONLY); + + /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ + mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, + MT753X_R0E_PORT_FW(MT753X_PORT_FW_CPU_ONLY)); =20 /* Enable and reset MIB counters */ mt7530_mib_reset(ds); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 52e5d71a04d3..2664057b3cd2 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -25,10 +25,6 @@ enum mt753x_id { =20 #define TRGMII_BASE(x) (0x10000 + (x)) =20 -/* Registers to ethsys access */ -#define ETHSYS_CLKCFG0 0x2c -#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) - #define SYSC_REG_RSTCTRL 0x34 #define RESET_MCM BIT(2) =20 @@ -63,16 +59,21 @@ enum mt753x_id { #define MT753X_MIRROR_MASK(id) ((((id) =3D=3D ID_MT7531) || ((id) =3D=3D = ID_MT7988)) ? \ MT7531_MIRROR_MASK : MT7530_MIRROR_MASK) =20 -/* Registers for BPDU and PAE frame control*/ +/* Register for BPDU and PAE frame control */ #define MT753X_BPC 0x24 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) =20 -enum mt753x_bpdu_port_fw { - MT753X_BPDU_FOLLOW_MFC, - MT753X_BPDU_CPU_EXCLUDE =3D 4, - MT753X_BPDU_CPU_INCLUDE =3D 5, - MT753X_BPDU_CPU_ONLY =3D 6, - MT753X_BPDU_DROP =3D 7, +/* Register for :03 and :0E MAC DA frame control */ +#define MT753X_RGAC2 0x2c +#define MT753X_R0E_PORT_FW(x) (((x) & 0x7) << 16) +#define MT753X_R0E_PORT_FW_MASK MT753X_R0E_PORT_FW(~0) + +enum mt753x_port_fw { + MT753X_PORT_FW_FOLLOW_MFC, + MT753X_PORT_FW_CPU_EXCLUDE =3D 4, + MT753X_PORT_FW_CPU_INCLUDE =3D 5, + MT753X_PORT_FW_CPU_ONLY =3D 6, + MT753X_PORT_FW_DROP =3D 7, }; =20 /* Registers for address table access */ --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E656DC77B75 for ; Mon, 22 May 2023 12:20:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233947AbjEVMU6 (ORCPT ); Mon, 22 May 2023 08:20:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233976AbjEVMTp (ORCPT ); Mon, 22 May 2023 08:19:45 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78332B9; Mon, 22 May 2023 05:17:15 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-970028cfb6cso110344366b.1; Mon, 22 May 2023 05:17:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757833; x=1687349833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mxWWB7HmyaQxi9NwzKK1iFLClbKEyjguXBwGckYC6x8=; b=Cwu9QH2AZmQcRhHwA+ZcwadKeOGCxhKOkTs82jLCRDxvAHVHr3jl1RrFR1XERbcQeT JX1qZJqtNrTpOVPZlDMwahBWvSeb7N7k53+2mzNX424sSgCU8moWUJXJ62SanLQZlw24 wCwZRKtLkyqfP+OFfdBKIjAa+6Fb6zYxsoTz/hLgxpPjiTEHvdnudVhYhttdIZiZyNiK wiCUpoc0I1z+aYuJ85TamKkpGomqTWQXHP9StMBtA4vqf5ufXO946BTT99mxLHyWpP0s 1dzhKNT7MyypZvWVUFsXrc+ntPxSUO1PHQtEtgo2UC0tYYp/hyXr1C6bb9PsJpsTNFor UKxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757833; x=1687349833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxWWB7HmyaQxi9NwzKK1iFLClbKEyjguXBwGckYC6x8=; b=MS996cHcYBseoW96/sTZZUdvZ8C2gwJTM+nTJw+ZOdCCiVRsRAQecl9m4u/CXmtIwx b7TT4q44qJ/TXO04QJENC1++uq2HD8uDI/+UjZ1ofB06rXxYAG0A4zLiYZBB9J4yuCCK PF7YEbo7n65ZuMuN136xqWhnWGqtZy8UKx4a55pLCDTzUjsWZjSbsxFhZluyJrJuI3oy DGaskpaUDOTvtSjGpErRPvfH0gIfj4HnLupJqmNXDoTY0BqrP1w3NQv304fLIymsHv2I Fc/CMhM8nzxzpSrJHCL0h5xTgcvX4ZYNkF+5S+WANUSVQyQQ4LMLsWmSZ/vTTZbrXwXJ XhDg== X-Gm-Message-State: AC+VfDwq47WsbkeeTdb+KjiDuJA3yZtzz3fcJ+6/dQ9M73yvCc/nN54j VJTsIPyS1+nXPnXCVT3OltY= X-Google-Smtp-Source: ACHHUZ7lHciZxL/m+3gJDMRRhfEEhmZCJvEN4N5PFHo9LfjsW5bEY/4Ew6UVZ9xDQF0lolEeJ4TpcQ== X-Received: by 2002:a17:906:4785:b0:970:9a7:65e1 with SMTP id cw5-20020a170906478500b0097009a765e1mr1377480ejc.56.1684757833163; Mon, 22 May 2023 05:17:13 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:12 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 29/30] net: dsa: introduce preferred_default_local_cpu_port and use on MT7530 Date: Mon, 22 May 2023 15:15:31 +0300 Message-Id: <20230522121532.86610-30-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Vladimir Oltean When multiple CPU ports are being used, the numerically smallest CPU port becomes the port all user ports become affine to. This may not be the best choice for all switches as there may be a numerically greater CPU port with more bandwidth than the numerically smallest one. Such switches are MT7530 and MT7531BE, which the MT7530 DSA subdriver controls. Port 5 of these switches has got RGMII whilst port 6 has got either TRGMII or SGMII. Therefore, introduce the preferred_default_local_cpu_port operation to the DSA subsystem and use it on the MT7530 DSA subdriver to prefer port 6 as the default CPU port. To prove the benefit of this operation, I (Ar=C4=B1n=C3=A7) have done a bid= irectional speed test between two DSA user ports on the MT7531BE switch using iperf3. The user ports are 1 Gbps full duplex and on different networks so the SoC MAC would have to do 2 Gbps TX and 2 Gbps RX to deliver full speed. Without preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 374 MBytes 157 Mbits/sec 734 sender [ 5][TX-C] 0.00-20.00 sec 373 MBytes 156 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 778 Mbits/sec 0 sender [ 7][RX-C] 0.00-20.00 sec 1.81 GBytes 777 Mbits/sec receiver With preferring port 6: [ ID][Role] Interval Transfer Bitrate Retr [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 856 Mbits/sec 273 sender [ 5][TX-C] 0.00-20.00 sec 1.99 GBytes 855 Mbits/sec receiver [ 7][RX-C] 0.00-20.00 sec 1.72 GBytes 737 Mbits/sec 15 sender [ 7][RX-C] 0.00-20.00 sec 1.71 GBytes 736 Mbits/sec receiver Using one port for WAN and the other ports for LAN is a very popular use case which is what this test emulates. This doesn't affect the remaining switches, MT7531AE and the switch on the MT7988 SoC. Both CPU ports of the MT7531AE switch have got SGMII and there is only one CPU port on the switch on the MT7988 SoC. Signed-off-by: Vladimir Oltean Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ include/net/dsa.h | 8 ++++++++ net/dsa/dsa.c | 24 +++++++++++++++++++++++- 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 8f5a8803cb33..8fd23da76169 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -399,6 +399,20 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); } =20 +/* If port 6 is available as a CPU port, always prefer that as the default, + * otherwise don't care. + */ +static struct dsa_port * +mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp =3D dsa_to_port(ds, 6); + + if (dsa_port_is_cpu(cpu_dp)) + return cpu_dp; + + return NULL; +} + /* Setup port 6 interface mode and TRGMII TX circuit */ static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) @@ -3000,6 +3014,7 @@ static int mt7988_setup(struct dsa_switch *ds) const struct dsa_switch_ops mt7530_switch_ops =3D { .get_tag_protocol =3D mtk_get_tag_protocol, .setup =3D mt753x_setup, + .preferred_default_local_cpu_port =3D mt753x_preferred_default_local_cpu_= port, .get_strings =3D mt7530_get_strings, .get_ethtool_stats =3D mt7530_get_ethtool_stats, .get_sset_count =3D mt7530_get_sset_count, diff --git a/include/net/dsa.h b/include/net/dsa.h index 8903053fa5aa..ab0f0a5b0860 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -958,6 +958,14 @@ struct dsa_switch_ops { struct phy_device *phy); void (*port_disable)(struct dsa_switch *ds, int port); =20 + /* + * Compatibility between device trees defining multiple CPU ports and + * drivers which are not OK to use by default the numerically smallest + * CPU port of a switch for its local ports. This can return NULL, + * meaning "don't know/don't care". + */ + struct dsa_port *(*preferred_default_local_cpu_port)(struct dsa_switch *d= s); + /* * Port's MAC EEE settings */ diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c index ab1afe67fd18..1afed89e03c0 100644 --- a/net/dsa/dsa.c +++ b/net/dsa/dsa.c @@ -403,6 +403,24 @@ static int dsa_tree_setup_default_cpu(struct dsa_switc= h_tree *dst) return 0; } =20 +static struct dsa_port * +dsa_switch_preferred_default_local_cpu_port(struct dsa_switch *ds) +{ + struct dsa_port *cpu_dp; + + if (!ds->ops->preferred_default_local_cpu_port) + return NULL; + + cpu_dp =3D ds->ops->preferred_default_local_cpu_port(ds); + if (!cpu_dp) + return NULL; + + if (WARN_ON(!dsa_port_is_cpu(cpu_dp) || cpu_dp->ds !=3D ds)) + return NULL; + + return cpu_dp; +} + /* Perform initial assignment of CPU ports to user ports and DSA links in = the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a= CPU @@ -410,12 +428,16 @@ static int dsa_tree_setup_default_cpu(struct dsa_swit= ch_tree *dst) */ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp, *dp; + struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; =20 list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; =20 + preferred_cpu_dp =3D dsa_switch_preferred_default_local_cpu_port(cpu_dp-= >ds); + if (preferred_cpu_dp && preferred_cpu_dp !=3D cpu_dp) + continue; + /* Prefer a local CPU port */ dsa_switch_for_each_port(dp, cpu_dp->ds) { /* Prefer the first local CPU port found */ --=20 2.39.2 From nobody Fri Sep 20 18:48:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CCEAC77B73 for ; Mon, 22 May 2023 12:21:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233963AbjEVMVB (ORCPT ); Mon, 22 May 2023 08:21:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234005AbjEVMTu (ORCPT ); Mon, 22 May 2023 08:19:50 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E38D1FEC; Mon, 22 May 2023 05:17:18 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-96f588bc322so587774666b.1; Mon, 22 May 2023 05:17:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684757836; x=1687349836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SG7TaztQuB5xH4PvogAkuq91yKarYjtMle5JWo2W3pY=; b=EO7b3IAzP1SXc9MmJGIcSSe7861+cIi3CHEghbiJcKaGzWX+L98AMOPbdutsRySWL5 EJrXsEovtZWyh9eA1nnQk0qsqqPN1J3Xuw8I6LdGVAXKfjyBlTmJEgH6zVShFDGmpRZn XkOx+uWN50aPNXztlw8xmKqXj0XhEju7M2jefqZiSvvu0iLYoZD26BzrDluKb95vmhLp amdPqR5k6kucItLpP2MP+QGqJGz2lNC5A5f2rUs3pnyPLRVqsXU7wOZJaaUNBSUK9MPw PQXBHyWWhrTJ7AMsZx/eAJT4OWw4BPQ9X8ZSt38Dr66aw+A/LIAmG4Jv72WN0UNf7d0G Mk1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684757836; x=1687349836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SG7TaztQuB5xH4PvogAkuq91yKarYjtMle5JWo2W3pY=; b=T29EEf7LmCyre83Ld/47Bj7guxdHYWMIIx4RxnZZGBHl8MgTHXnUW27WO6mgCZ6Xek m5YZ8Ggk7f5QwpEJ552W7swzhMQu/uU46Fwzvy/ItgL5WMv1xrHyhoiKYPpdv6be7USv rfWy3D2uhi0pVF1W5q3DlI0OiASVZutBiz1b54myZ17uQMjkTqJdZCm+7rmgSLthMJeA wJULiO36jXybULGNASqaVkT8HGf2W6pxdHWW4RpM78RCvztPE19faJ2pP11h4hmwmRuj ZgRYTcD9tiy/bcPro3+x+UuBjr5cDKoumHVo8WIRru8tnUSZ1CezL5qYPC5Mwfh2rIFH PR9w== X-Gm-Message-State: AC+VfDw+GiASgJBvCefjBtc+dg0cjgX/q8LTZrYrcKxNeEO1K8gopdmI YPKO7J3VDyF/GVtLeq1QTuU= X-Google-Smtp-Source: ACHHUZ6ILsyx6GlzQ/rNkEbarGHyNFwGSGGr3EMybRgtPQv7aSowIU1Ar1v0dmHaogkEZpVZCkAldw== X-Received: by 2002:a17:907:3f1c:b0:96f:c46f:d8fa with SMTP id hq28-20020a1709073f1c00b0096fc46fd8famr4292186ejc.1.1684757836353; Mon, 22 May 2023 05:17:16 -0700 (PDT) Received: from arinc9-PC.. ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id y26-20020a17090614da00b009659fed3612sm2999950ejc.24.2023.05.22.05.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 May 2023 05:17:15 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, mithat.guner@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 30/30] MAINTAINERS: add me as maintainer of MEDIATEK SWITCH DRIVER Date: Mon, 22 May 2023 15:15:32 +0300 Message-Id: <20230522121532.86610-31-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230522121532.86610-1-arinc.unal@arinc9.com> References: <20230522121532.86610-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ar=C4=B1n=C3=A7 =C3=9CNAL Add me as a maintainer of the MediaTek MT7530 DSA subdriver. List maintainers in alphabetical order by first name. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL Reviewed-by: Vladimir Oltean Tested-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index e2fd64c2ebdc..51e8d30651a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13254,10 +13254,11 @@ F: drivers/memory/mtk-smi.c F: include/soc/mediatek/smi.h =20 MEDIATEK SWITCH DRIVER -M: Sean Wang +M: Ar=C4=B1n=C3=A7 =C3=9CNAL +M: Daniel Golle M: Landen Chao M: DENG Qingfang -M: Daniel Golle +M: Sean Wang L: netdev@vger.kernel.org S: Maintained F: drivers/net/dsa/mt7530-mdio.c --=20 2.39.2