From nobody Thu Feb 12 10:39:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E21D1C7EE2A for ; Mon, 22 May 2023 09:22:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232866AbjEVJWs (ORCPT ); Mon, 22 May 2023 05:22:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232833AbjEVJWe (ORCPT ); Mon, 22 May 2023 05:22:34 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2369E9; Mon, 22 May 2023 02:22:25 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34M9MHsN049107; Mon, 22 May 2023 04:22:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1684747337; bh=Ppdp6mq1esy3x8XkblPahsO1RcBX9wHN1CQbS7/jecc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HttH6RxucYa/Gjva5Ayttu9gYuoNNq+EJONr2iXXrhO1/DD/N0hF5dqZRQDZbl9W6 iPDy8vtlHFdoSiVXtX0uOzjrzaT67Ye+h1ux4NmXboQfFCY5u0mZ30G7tc+zvZndCa ieXPQCAQ/VjIxcbhEAQhS/lLL8HXVet4Nu/x5Re8= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34M9MHrR038619 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 May 2023 04:22:17 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 22 May 2023 04:22:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 22 May 2023 04:22:17 -0500 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34M9M2e7127198; Mon, 22 May 2023 04:22:14 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH 3/3] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Mon, 22 May 2023 14:52:01 +0530 Message-ID: <20230522092201.127598-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230522092201.127598-1-s-vadapalli@ti.com> References: <20230522092201.127598-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/Makefile | 1 + .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 72 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.= dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 88c43f1f211b..8ac7507f60ba 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-j784s4-evm-usxgmii-exp1-exp2.dtbo =20 # Enable support for device-tree overlays DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/= arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..1482a61d5487 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&main_cpsw0 { + status =3D "okay"; + pinctrl-names =3D "default"; +}; + +&main_cpsw0_port1 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status =3D "okay"; + phy-mode =3D "usxgmii"; + mac-address =3D [00 00 00 00 00 00]; + phys =3D <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names =3D "mac", "serdes"; + fixed-link { + speed =3D <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status =3D "okay"; + assigned-clock-parents =3D <&k3_clks 406 9>; +}; + +&serdes2 { + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + serdes2_usxgmii_link: phy@2 { + reg =3D <2>; + cdns,num-lanes =3D <2>; + #phy-cells =3D <0>; + cdns,phy-type =3D ; + resets =3D <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states =3D , , + , , + , , + , , + , , + , ; +}; --=20 2.25.1