From nobody Mon Feb 9 10:52:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C8FC7EE2A for ; Sat, 20 May 2023 02:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229870AbjETCa4 (ORCPT ); Fri, 19 May 2023 22:30:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229543AbjETCaz (ORCPT ); Fri, 19 May 2023 22:30:55 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA3461B0; Fri, 19 May 2023 19:30:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 672D365B1A; Sat, 20 May 2023 02:30:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF210C433EF; Sat, 20 May 2023 02:30:49 +0000 (UTC) From: Huacai Chen To: Huacai Chen Cc: loongarch@lists.linux.dev, linux-arch@vger.kernel.org, Xuefeng Li , Guo Ren , Xuerui Wang , Jiaxun Yang , linux-kernel@vger.kernel.org, loongson-kernel@lists.loongnix.cn, Huacai Chen , stable@vger.kernel.org, Jun Yi Subject: [PATCH] LoongArch: Fix perf event id calculation Date: Sat, 20 May 2023 10:30:00 +0800 Message-Id: <20230520023001.3491257-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" LoongArch PMCFG has 10bit event id rather than 8 bit, so fix it. Cc: stable@vger.kernel.org Signed-off-by: Jun Yi Signed-off-by: Huacai Chen --- arch/loongarch/kernel/perf_event.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/per= f_event.c index ff28f99b47d7..0491bf453cd4 100644 --- a/arch/loongarch/kernel/perf_event.c +++ b/arch/loongarch/kernel/perf_event.c @@ -271,7 +271,7 @@ static void loongarch_pmu_enable_event(struct hw_perf_e= vent *evt, int idx) WARN_ON(idx < 0 || idx >=3D loongarch_pmu.num_counters); =20 /* Make sure interrupt enabled. */ - cpuc->saved_ctrl[idx] =3D M_PERFCTL_EVENT(evt->event_base & 0xff) | + cpuc->saved_ctrl[idx] =3D M_PERFCTL_EVENT(evt->event_base) | (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE; =20 cpu =3D (event->cpu >=3D 0) ? event->cpu : smp_processor_id(); @@ -594,7 +594,7 @@ static struct pmu pmu =3D { =20 static unsigned int loongarch_pmu_perf_event_encode(const struct loongarch= _perf_event *pev) { - return (pev->event_id & 0xff); + return M_PERFCTL_EVENT(pev->event_id); } =20 static const struct loongarch_perf_event *loongarch_pmu_map_general_event(= int idx) @@ -849,7 +849,7 @@ static void resume_local_counters(void) =20 static const struct loongarch_perf_event *loongarch_pmu_map_raw_event(u64 = config) { - raw_event.event_id =3D config & 0xff; + raw_event.event_id =3D M_PERFCTL_EVENT(config); =20 return &raw_event; } --=20 2.39.1