From nobody Sun Feb 8 23:06:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F095C77B75 for ; Fri, 19 May 2023 15:33:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232190AbjESPdt (ORCPT ); Fri, 19 May 2023 11:33:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232160AbjESPdr (ORCPT ); Fri, 19 May 2023 11:33:47 -0400 Received: from exchange.fintech.ru (exchange.fintech.ru [195.54.195.159]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FA4A1AC for ; Fri, 19 May 2023 08:33:44 -0700 (PDT) Received: from Ex16-01.fintech.ru (10.0.10.18) by exchange.fintech.ru (195.54.195.169) with Microsoft SMTP Server (TLS) id 14.3.498.0; Fri, 19 May 2023 18:33:34 +0300 Received: from localhost (10.0.253.138) by Ex16-01.fintech.ru (10.0.10.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Fri, 19 May 2023 18:33:34 +0300 From: Nikita Zhandarovich To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= CC: Nikita Zhandarovich , "Pan, Xinhui" , David Airlie , Daniel Vetter , , , , Subject: [PATCH] drm/radeon: fix possible division-by-zero errors Date: Fri, 19 May 2023 08:33:27 -0700 Message-ID: <20230519153327.231806-1-n.zhandarovich@fintech.ru> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.253.138] X-ClientProxiedBy: Ex16-02.fintech.ru (10.0.10.19) To Ex16-01.fintech.ru (10.0.10.18) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Function rv740_get_decoded_reference_divider() may return 0 due to unpredictable reference divider value calculated in radeon_atom_get_clock_dividers(). This will lead to division-by-zero error once that value is used as a divider in calculating 'clk_s'. While unlikely, this issue should nonetheless be prevented so add a sanity check for such cases by testing 'decoded_ref' value against 0. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 66229b200598 ("drm/radeon/kms: add dpm support for rv7xx (v4)") Signed-off-by: Nikita Zhandarovich --- drivers/gpu/drm/radeon/cypress_dpm.c | 7 +++++-- drivers/gpu/drm/radeon/ni_dpm.c | 7 +++++-- drivers/gpu/drm/radeon/rv740_dpm.c | 7 +++++-- 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/= cypress_dpm.c index fdddbbaecbb7..3678b7e384e1 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -555,10 +555,13 @@ static int cypress_populate_mclk_value(struct radeon_= device *rdev, =20 if (radeon_atombios_get_asic_ss_info(rdev, &ss, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { + u32 clk_s, clk_v; u32 reference_clock =3D rdev->clock.mpll.reference_freq; u32 decoded_ref =3D rv740_get_decoded_reference_divider(dividers.ref_di= v); - u32 clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v =3D ss.percentage * + if (!decoded_ref) + return -EINVAL; + clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); + clk_v =3D ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk= _s * 625); =20 mpll_ss1 &=3D ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dp= m.c index 672d2239293e..9ce3e5635efc 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -2239,10 +2239,13 @@ static int ni_populate_mclk_value(struct radeon_dev= ice *rdev, =20 if (radeon_atombios_get_asic_ss_info(rdev, &ss, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { + u32 clk_s, clk_v; u32 reference_clock =3D rdev->clock.mpll.reference_freq; u32 decoded_ref =3D rv740_get_decoded_reference_divider(dividers.ref_di= v); - u32 clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v =3D ss.percentage * + if (!decoded_ref) + return -EINVAL; + clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); + clk_v =3D ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk= _s * 625); =20 mpll_ss1 &=3D ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c b/drivers/gpu/drm/radeon/rv= 740_dpm.c index d57a3e1df8d6..ca76efa0f59d 100644 --- a/drivers/gpu/drm/radeon/rv740_dpm.c +++ b/drivers/gpu/drm/radeon/rv740_dpm.c @@ -247,10 +247,13 @@ int rv740_populate_mclk_value(struct radeon_device *r= dev, =20 if (radeon_atombios_get_asic_ss_info(rdev, &ss, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { + u32 clk_s, clk_v; u32 reference_clock =3D rdev->clock.mpll.reference_freq; u32 decoded_ref =3D rv740_get_decoded_reference_divider(dividers.ref_di= v); - u32 clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v =3D 0x40000 * ss.percentage * + if (!decoded_ref) + return -EINVAL; + clk_s =3D reference_clock * 5 / (decoded_ref * ss.rate); + clk_v =3D 0x40000 * ss.percentage * (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); =20 mpll_ss1 &=3D ~CLKV_MASK; --=20 2.25.1