From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71420C7EE2C for ; Thu, 18 May 2023 23:06:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231215AbjERXGx (ORCPT ); Thu, 18 May 2023 19:06:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229869AbjERXGs (ORCPT ); Thu, 18 May 2023 19:06:48 -0400 Received: from mail-il1-x134.google.com (mail-il1-x134.google.com [IPv6:2607:f8b0:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5C2210E9 for ; Thu, 18 May 2023 16:06:40 -0700 (PDT) Received: by mail-il1-x134.google.com with SMTP id e9e14a558f8ab-334f64c91aeso6782945ab.2 for ; Thu, 18 May 2023 16:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684451200; x=1687043200; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eat7ZZkvIgNO0d+Nb1ho7Qs2hgM0XyaATLA4vhm7AEo=; b=DE944Ib1ld+120uL+TpRFUQEUj6080i0PgE0CJljKz9AT6i5kL6jbS5vo+Ah3G3Y6Q 5A1JNFqdHCind3nF0DuR3oKRPNTu1RxUEuYUDTkX1+xBVMZPnXBQ1G+7GPrdhsX+GoqS T3zCHFtXehuLBWscviMN4qwDbIgVkASo9Gke+noVwt/+OjXpd+qf1KVxAKH48lWwLbMQ lJHm2t3SHeoxm92FdGafsqeapPFYMsR5GAirsGd5fUHZysjBnjw17yGhij2oa/63kybo SqJPRjIP31NhhlmQLOTEsiycV0yBuMZZmW17Eayv17N0vhYIuxXAb6DHYG6WQ1O4p8lE 6T+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684451200; x=1687043200; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eat7ZZkvIgNO0d+Nb1ho7Qs2hgM0XyaATLA4vhm7AEo=; b=k/kIPERhgGf3eSpmJ6JZixsbd1maW1UaXVDWWAbSX5ZxzMHLIHxNjxNIVOzKr9NnZq s3OAjFCV8+h3N5s2F6Qn3y3MtbzNs6CbhttakpniXdcKuX/Nb8pcBQ4Mv2s/srE+djBc ZMfXAoXcOnTB7LTmZ9iVyObhgiqm8HU1teK1evj45ats0dMNdfzwXCVDUaUDKpN4Rb1u GqeN8LtvHizceOIrl8Vrp7E1dBdsTL7eC9Jlp7FdCaBwqTcPRkiY+w3UhHvOJjtAhLOe lEpGgi0LzctU/VF4E7lKXqKXd3sIkNyOc0c6hp6TNyQCd/23eZDRrLMoAczQYycxYag5 tSUg== X-Gm-Message-State: AC+VfDysCjOuL1mGcvNi3ZBXiXaTtWJvxO0+lcIXDAcAwYu037kG5MUL Yy0DbLazT7ozMu5pE94KMVk= X-Google-Smtp-Source: ACHHUZ7k+Omw1YOkZhO0tjeAZNgxijvwDBeh4ZVTvPZ9gntUZInKMpBhWZ0XSLvpAnWgmUezU83HtA== X-Received: by 2002:a92:c6cf:0:b0:332:b18a:7ba7 with SMTP id v15-20020a92c6cf000000b00332b18a7ba7mr5201843ilm.27.1684451199670; Thu, 18 May 2023 16:06:39 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:56b8:635c:4c7a:15b1]) by smtp.gmail.com with ESMTPSA id z12-20020a92cd0c000000b003317ebbc426sm635897iln.47.2023.05.18.16.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 16:06:39 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Lucas Stach , Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V7 1/6] drm: bridge: samsung-dsim: fix blanking packet size calculation Date: Thu, 18 May 2023 18:06:21 -0500 Message-Id: <20230518230626.404068-2-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518230626.404068-1-aford173@gmail.com> References: <20230518230626.404068-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Lucas Stach Scale the blanking packet sizes to match the ratio between HS clock and DPI interface clock. The controller seems to do internal scaling to the number of active lanes, so we don't take those into account. Signed-off-by: Lucas Stach Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index e0a402a85787..2be3b58624c3 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -874,17 +874,29 @@ static void samsung_dsim_set_display_mode(struct sams= ung_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; + int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; + int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + + /* remove packet overhead when possible */ + hfp =3D max(hfp - 6, 0); + hbp =3D max(hbp - 6, 0); + hsa =3D max(hsa - 6, 0); + + dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", + hfp, hbp, hsa); + reg =3D DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); =20 - reg =3D DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg =3D DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); =20 reg =3D DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA(hsa); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg =3D DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | --=20 2.39.2 From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4B18C7EE2C for ; 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Thu, 18 May 2023 16:06:41 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:56b8:635c:4c7a:15b1]) by smtp.gmail.com with ESMTPSA id z12-20020a92cd0c000000b003317ebbc426sm635897iln.47.2023.05.18.16.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 16:06:40 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , linux-kernel@vger.kernel.org Subject: [PATCH V7 2/6] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp] Date: Thu, 18 May 2023 18:06:22 -0500 Message-Id: <20230518230626.404068-3-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518230626.404068-1-aford173@gmail.com> References: <20230518230626.404068-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" According to Table 13-45 of the i.MX8M Mini Reference Manual, the min and max values for M and the frequency range for the VCO_out calculator were incorrect. This information was contradicted in other parts of the mini, nano and plus manuals. After reaching out to my NXP Rep, when confronting him about discrepencies in the Nano manual, he responded with: "Yes it is definitely wrong, the one that is part of the NOTE in MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is not correct. I will report this to Doc team, the one customer should be take into account is the Table 13-40 DPHY PLL Parameters and the Note above." These updated values also match what is used in the NXP downstream kernel. To fix this, make new variables to hold the min and max values of m and the minimum value of VCO_out, and update the PMS calculator to use these new variables instead of using hard-coded values to keep the backwards compatibility with other parts using this driver. Fixes: 4d562c70c4dc ("drm: bridge: samsung-dsim: Add i.MX8M Mini/Nano suppo= rt") Signed-off-by: Adam Ford Reviewed-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 22 ++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 3 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 2be3b58624c3..bf4b33d2de76 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -405,6 +405,9 @@ static const struct samsung_dsim_driver_data exynos3_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data =3D { @@ -418,6 +421,9 @@ static const struct samsung_dsim_driver_data exynos4_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data =3D { @@ -429,6 +435,9 @@ static const struct samsung_dsim_driver_data exynos5_ds= i_driver_data =3D { .num_bits_resol =3D 11, .pll_p_offset =3D 13, .reg_values =3D reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = =3D { @@ -441,6 +450,9 @@ static const struct samsung_dsim_driver_data exynos5433= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5433_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = =3D { @@ -453,6 +465,9 @@ static const struct samsung_dsim_driver_data exynos5422= _dsi_driver_data =3D { .num_bits_resol =3D 12, .pll_p_offset =3D 13, .reg_values =3D exynos5422_reg_values, + .m_min =3D 41, + .m_max =3D 125, + .min_freq =3D 500, }; =20 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data =3D { @@ -469,6 +484,9 @@ static const struct samsung_dsim_driver_data imx8mm_dsi= _driver_data =3D { */ .pll_p_offset =3D 14, .reg_values =3D imx8mm_dsim_reg_values, + .m_min =3D 64, + .m_max =3D 1023, + .min_freq =3D 1050, }; =20 static const struct samsung_dsim_driver_data * @@ -547,12 +565,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct= samsung_dsim *dsi, tmp =3D (u64)fout * (_p << _s); do_div(tmp, fin); _m =3D tmp; - if (_m < 41 || _m > 125) + if (_m < driver_data->m_min || _m > driver_data->m_max) continue; =20 tmp =3D (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < driver_data->min_freq * MHZ || tmp > driver_data->max_freq * MHZ) continue; =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index ba5484de2b30..a1a5b2b89a7a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -54,11 +54,14 @@ struct samsung_dsim_driver_data { unsigned int has_freqband:1; unsigned int has_clklane_stop:1; unsigned int num_clks; + unsigned int min_freq; unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + u16 m_min; + u16 m_max; }; =20 struct samsung_dsim_host_ops { --=20 2.39.2 From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4133DC77B7D for ; Thu, 18 May 2023 23:07:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231229AbjERXG7 (ORCPT ); Thu, 18 May 2023 19:06:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231196AbjERXGu (ORCPT ); Thu, 18 May 2023 19:06:50 -0400 Received: from mail-io1-xd2a.google.com (mail-io1-xd2a.google.com [IPv6:2607:f8b0:4864:20::d2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BFAE10C6 for ; Thu, 18 May 2023 16:06:43 -0700 (PDT) Received: by mail-io1-xd2a.google.com with SMTP id ca18e2360f4ac-76fd7c2aa67so201574039f.0 for ; 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charset="utf-8" Make the pll-clock-frequency optional. If it's present, use it to maintain backwards compatibility with existing hardware. If it is absent, read clock rate of "sclk_mipi" to determine the rate. Since it can be optional, change the message from an error to dev_info. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index bf4b33d2de76..6f012016068a 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1712,11 +1712,11 @@ static const struct mipi_dsi_host_ops samsung_dsim_= ops =3D { }; =20 static int samsung_dsim_of_read_u32(const struct device_node *np, - const char *propname, u32 *out_value) + const char *propname, u32 *out_value, bool optional) { int ret =3D of_property_read_u32(np, propname, out_value); =20 - if (ret < 0) + if (ret < 0 && !optional) pr_err("%pOF: failed to get '%s' property\n", np, propname); =20 return ret; @@ -1726,20 +1726,29 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) { struct device *dev =3D dsi->dev; struct device_node *node =3D dev->of_node; + struct clk *pll_clk; int ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", - &dsi->pll_clk_rate); - if (ret < 0) - return ret; + &dsi->pll_clk_rate, 1); + + /* If it doesn't exist, read it from the clock instead of failing */ + if (ret < 0) { + dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); + pll_clk =3D devm_clk_get(dev, "sclk_mipi"); + if (!IS_ERR(pll_clk)) + dsi->pll_clk_rate =3D clk_get_rate(pll_clk); + else + return PTR_ERR(pll_clk); + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate); + &dsi->burst_clk_rate, 0); if (ret < 0) return ret; =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", - &dsi->esc_clk_rate); + &dsi->esc_clk_rate, 0); if (ret < 0) return ret; =20 --=20 2.39.2 From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86FC5C77B73 for ; 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Thu, 18 May 2023 16:06:44 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:56b8:635c:4c7a:15b1]) by smtp.gmail.com with ESMTPSA id z12-20020a92cd0c000000b003317ebbc426sm635897iln.47.2023.05.18.16.06.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 16:06:44 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Frieder Schrempf , Chen-Yu Tsai , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Jagan Teki , Marek Szyprowski , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V7 4/6] drm: bridge: samsung-dsim: Select GENERIC_PHY_MIPI_DPHY Date: Thu, 18 May 2023 18:06:24 -0500 Message-Id: <20230518230626.404068-5-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518230626.404068-1-aford173@gmail.com> References: <20230518230626.404068-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support variable DPHY timings, it's necessary to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config can be used to determine the nominal values for a given resolution and refresh rate. Signed-off-by: Adam Ford Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Chen-Yu Tsai --- drivers/gpu/drm/bridge/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index f076a09afac0..82c68b042444 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -227,6 +227,7 @@ config DRM_SAMSUNG_DSIM select DRM_KMS_HELPER select DRM_MIPI_DSI select DRM_PANEL_BRIDGE + select GENERIC_PHY_MIPI_DPHY help The Samsung MIPI DSIM bridge controller driver. This MIPI DSIM bridge can be found it on Exynos SoCs and --=20 2.39.2 From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED60CC77B7D for ; Thu, 18 May 2023 23:07:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231244AbjERXHF (ORCPT ); Thu, 18 May 2023 19:07:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231175AbjERXGv (ORCPT ); Thu, 18 May 2023 19:06:51 -0400 Received: from mail-il1-x12e.google.com (mail-il1-x12e.google.com [IPv6:2607:f8b0:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F8891AB for ; Thu, 18 May 2023 16:06:47 -0700 (PDT) Received: by mail-il1-x12e.google.com with SMTP id e9e14a558f8ab-331ad4cd4fdso6081775ab.1 for ; Thu, 18 May 2023 16:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684451206; x=1687043206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yt5KFw+xtdIb6VItu3DPNGmoCpleoJEIyPuwXXhva2M=; b=ZcATbFkprZeFTNuSJqhxSUZTj8gzDbNC/xotilvBhiqsd7QSqMSDRlsOucCBzqXZyI XYouvbGfy4ahQndKyeE3b4McfpFsCkVne6kX591hEGmbntrkFhdAVjCmhbokhuWzV6Qb anxwWcjMkXR4e51VGHvVXIHkOzVOyAtFr3pGDTBEmEQR/MtlznidBh0F+I34vf4J1Qm6 Nncs08OSkIf5QPK2hFekbTNfMI+9kaRRcjiztdhB7bKKdRB2YhxblcBs7dq+9Z/N13f2 Caxw69r1Z4ec5gN6TN+eFIxmzt01LxDa4B25itUC9/dOkGKbIpAkmpscavvVIq29yNiO ksuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684451206; x=1687043206; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yt5KFw+xtdIb6VItu3DPNGmoCpleoJEIyPuwXXhva2M=; b=Eul/Lo9BRIZZd4YQ7KxTJpTa/cFtwqGPwDhEuF15/hrdWZ27KGaHHniSr9O131r2fa ev9vTWaDmnodmEjrZ5EHc3inWzJoGXWwFo57YjTa7XPy02ej53WvkwGB4pNZJLHyVN3S qCM2Mr12xq/91T+RPTw26yq5h2C6OQuFK9Kj42e0dGprqXudjYhQrL4Ri7oGWZ2P02bq R1iMwukNbsqbEfUYvYb+oQu0lUPRfQk9ZCYGh30Jr8Ec9PMdiLvvSsTHYaX6XH+fWOTN Kk8KD6PygZfoAtPi0oNSx9alTQBjTQi/3NoP+9SuIhn8SToukME6FssUvaKSkCSMGOzX hDLA== X-Gm-Message-State: AC+VfDy38vwrUK4ZoZMOhEPkpqPmx4iJM6fFF7upfbJa55Q8LxjXYjZc VK+Ef8WDbNLZswltIKMUc5s= X-Google-Smtp-Source: ACHHUZ5NbInxQjiFLvVmnfh4z2rBRQlHrQv7f27IaNSKoLF9oRFxNaXcgXpzysKjyTOVjwElBGURAw== X-Received: by 2002:a92:d90c:0:b0:338:98a9:3898 with SMTP id s12-20020a92d90c000000b0033898a93898mr91909iln.21.1684451206258; Thu, 18 May 2023 16:06:46 -0700 (PDT) Received: from aford-B741.lan ([2601:447:d001:897f:56b8:635c:4c7a:15b1]) by smtp.gmail.com with ESMTPSA id z12-20020a92cd0c000000b003317ebbc426sm635897iln.47.2023.05.18.16.06.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 16:06:45 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Lucas Stach , Chen-Yu Tsai , Frieder Schrempf , Michael Walle , Marek Szyprowski , Jagan Teki , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , Marek Vasut , linux-kernel@vger.kernel.org Subject: [PATCH V7 5/6] drm: bridge: samsung-dsim: Dynamically configure DPHY timing Date: Thu, 18 May 2023 18:06:25 -0500 Message-Id: <20230518230626.404068-6-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518230626.404068-1-aford173@gmail.com> References: <20230518230626.404068-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The DPHY timings are currently hard coded. Since the input clock can be variable, the phy timings need to be variable too. To facilitate this, we need to cache the hs_clock based on what is generated from the PLL. The phy_mipi_dphy_get_default_config_for_hsclk function configures the DPHY timings in pico-seconds, and a small macro converts those timings into clock cycles based on the hs_clk. Signed-off-by: Adam Ford Signed-off-by: Lucas Stach Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Michael Walle Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 58 +++++++++++++++++++++++---- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 52 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index 6f012016068a..e67e501c9d49 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -218,6 +218,8 @@ =20 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" =20 +#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000= 000000ULL) + static const char *const clk_names[5] =3D { "bus_clk", "sclk_mipi", @@ -651,6 +653,8 @@ static unsigned long samsung_dsim_set_pll(struct samsun= g_dsim *dsi, reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) =3D=3D 0); =20 + dsi->hs_clock =3D fout; + return fout; } =20 @@ -698,13 +702,47 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) const struct samsung_dsim_driver_data *driver_data =3D dsi->driver_data; const unsigned int *reg_values =3D driver_data->reg_values; u32 reg; + struct phy_configure_opts_mipi_dphy cfg; + int clk_prepare, lpx, clk_zero, clk_post, clk_trail; + int hs_exit, hs_prepare, hs_zero, hs_trail; + unsigned long long byte_clock =3D dsi->hs_clock / 8; =20 if (driver_data->has_freqband) return; =20 + phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, + dsi->lanes, &cfg); + + /* + * TODO: + * The tech Applications Processor manuals for i.MX8M Mini, Nano, + * and Plus don't state what the definition of the PHYTIMING + * bits are beyond their address and bit position. + * After reviewing NXP's downstream code, it appears + * that the various PHYTIMING registers take the number + * of cycles and use various dividers on them. This + * calculation does not result in an exact match to the + * downstream code, but it is very close to the values + * generated by their lookup table, and it appears + * to sync at a variety of resolutions. If someone + * can get a more accurate mathematical equation needed + * for these registers, this should be updated. + */ + + lpx =3D PS_TO_CYCLE(cfg.lpx, byte_clock); + hs_exit =3D PS_TO_CYCLE(cfg.hs_exit, byte_clock); + clk_prepare =3D PS_TO_CYCLE(cfg.clk_prepare, byte_clock); + clk_zero =3D PS_TO_CYCLE(cfg.clk_zero, byte_clock); + clk_post =3D PS_TO_CYCLE(cfg.clk_post, byte_clock); + clk_trail =3D PS_TO_CYCLE(cfg.clk_trail, byte_clock); + hs_prepare =3D PS_TO_CYCLE(cfg.hs_prepare, byte_clock); + hs_zero =3D PS_TO_CYCLE(cfg.hs_zero, byte_clock); + hs_trail =3D PS_TO_CYCLE(cfg.hs_trail, byte_clock); + /* B D-PHY: D-PHY Master & Slave Analog Block control */ reg =3D reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | reg_values[PHYCTRL_SLEW_UP]; + samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); =20 /* @@ -712,7 +750,9 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_ds= im *dsi) * T HS-EXIT: Time that the transmitter drives LP-11 following a HS * burst */ - reg =3D reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; + + reg =3D DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); + samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); =20 /* @@ -728,10 +768,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_= dsim *dsi) * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after * the last payload clock bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_CLK_PREPARE] | - reg_values[PHYTIMING_CLK_ZERO] | - reg_values[PHYTIMING_CLK_POST] | - reg_values[PHYTIMING_CLK_TRAIL]; + + reg =3D DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | + DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | + DSIM_PHYTIMING1_CLK_POST(clk_post) | + DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); =20 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); =20 @@ -744,8 +785,11 @@ static void samsung_dsim_set_phy_ctrl(struct samsung_d= sim *dsi) * T HS-TRAIL: Time that the transmitter drives the flipped differential * state after last payload data bit of a HS transmission burst */ - reg =3D reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | - reg_values[PHYTIMING_HS_TRAIL]; + + reg =3D DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | + DSIM_PHYTIMING2_HS_ZERO(hs_zero) | + DSIM_PHYTIMING2_HS_TRAIL(hs_trail); + samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); } =20 diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung= -dsim.h index a1a5b2b89a7a..d9d431e3b65a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -93,6 +93,7 @@ struct samsung_dsim { =20 u32 pll_clk_rate; u32 burst_clk_rate; + u32 hs_clock; u32 esc_clk_rate; u32 lanes; u32 mode_flags; --=20 2.39.2 From nobody Mon Feb 9 12:08:21 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAADBC77B7D for ; Thu, 18 May 2023 23:07:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231256AbjERXHK (ORCPT ); Thu, 18 May 2023 19:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231189AbjERXGw (ORCPT ); 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Thu, 18 May 2023 16:06:47 -0700 (PDT) From: Adam Ford To: dri-devel@lists.freedesktop.org Cc: aford@beaconembedded.com, Adam Ford , Chen-Yu Tsai , Frieder Schrempf , Marek Szyprowski , Jagan Teki , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Inki Dae , linux-kernel@vger.kernel.org Subject: [PATCH V7 6/6] drm: bridge: samsung-dsim: Support non-burst mode Date: Thu, 18 May 2023 18:06:26 -0500 Message-Id: <20230518230626.404068-7-aford173@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230518230626.404068-1-aford173@gmail.com> References: <20230518230626.404068-1-aford173@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The high-speed clock is hard-coded to the burst-clock frequency specified in the device tree. However, when using devices like certain bridge chips without burst mode and varying resolutions and refresh rates, it may be necessary to set the high-speed clock dynamically based on the desired pixel clock for the connected device. This also removes the need to set a clock speed from the device tree for non-burst mode operation, since the pixel clock rate is the rate requested from the attached device like a bridge chip. This should have no impact for people using burst-mode and setting the burst clock rate is still required for those users. If the burst clock is not present, change the error message to dev_info indicating the clock use the pixel clock. Signed-off-by: Adam Ford Tested-by: Chen-Yu Tsai Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Tested-by: Marek Szyprowski Reviewed-by: Jagan Teki Tested-by: Jagan Teki # imx8mm-icore --- drivers/gpu/drm/bridge/samsung-dsim.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge= /samsung-dsim.c index e67e501c9d49..9eda8ecc4151 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -660,11 +660,21 @@ static unsigned long samsung_dsim_set_pll(struct sams= ung_dsim *dsi, =20 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) { - unsigned long hs_clk, byte_clk, esc_clk; + unsigned long hs_clk, byte_clk, esc_clk, pix_clk; unsigned long esc_div; u32 reg; + struct drm_display_mode *m =3D &dsi->mode; + int bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + /* m->clock is in KHz */ + pix_clk =3D m->clock * 1000; + + /* Use burst_clk_rate if available, otherwise use the pix_clk */ + if (dsi->burst_clk_rate) + hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); + else + hs_clk =3D samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->la= nes)); =20 - hs_clk =3D samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); if (!hs_clk) { dev_err(dsi->dev, "failed to configure DSI PLL\n"); return -EFAULT; @@ -936,7 +946,7 @@ static void samsung_dsim_set_display_mode(struct samsun= g_dsim *dsi) u32 reg; =20 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8; + int byte_clk_khz =3D dsi->hs_clock / 1000 / 8; int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; @@ -1786,10 +1796,13 @@ static int samsung_dsim_parse_dt(struct samsung_dsi= m *dsi) return PTR_ERR(pll_clk); } =20 + /* If it doesn't exist, use pixel clock instead of failing */ ret =3D samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", - &dsi->burst_clk_rate, 0); - if (ret < 0) - return ret; + &dsi->burst_clk_rate, 1); + if (ret < 0) { + dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); + dsi->burst_clk_rate =3D 0; + } =20 ret =3D samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", &dsi->esc_clk_rate, 0); --=20 2.39.2