From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBA28C7EE25 for ; Thu, 18 May 2023 18:57:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230102AbjERS47 (ORCPT ); Thu, 18 May 2023 14:56:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230095AbjERS45 (ORCPT ); Thu, 18 May 2023 14:56:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FA48E51; Thu, 18 May 2023 11:56:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 90D7964FCD; Thu, 18 May 2023 18:56:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 371ABC433A1; Thu, 18 May 2023 18:56:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436215; bh=hH6Or+D9CJEmJbCMZBOXhGK6nn9vuBMRv9LnXKOB0J4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qLyl0D4TopzJyU9z00h+qUgzbvSNep9xMKXs82tfn2tXobCqsXKxFun0hWCXKKrhi 2Y5YBJez9Iy550P/WzkKhFWjRzuD0CVk16r1eeG9+odRnAsKUJk01JdR3EdedXAMU9 d36D2huVwKnUyJwx4bG5FWdfEcNnHM4zGBwbFkMuAu13QYHNDKThVG2kPvL3xq9wNg FtFoCZftuQ55acPYFUfjcjynVMBJ1f/g3BYPBgmK/EZ0ypIkai4uxt10EE3LqHC2wl t9nh4q7/ZE0TQ0lgu8RVDA+4ndCAbYzakt9Zz4zqh37fHXrOYuDghWLNL+s5eyWijr wSFfn/LWmPsSw== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 1/9] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Date: Fri, 19 May 2023 02:45:33 +0800 Message-Id: <20230518184541.2627-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for T-HEAD TH1520 plic. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley Reviewed-by: Guo Ren --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index f75736a061af..0fa9b862e4a5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - thead,th1520-plic - const: thead,c900-plic - items: - const: sifive,plic-1.0.0 --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9246BC7EE23 for ; Thu, 18 May 2023 18:57:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230121AbjERS5D (ORCPT ); Thu, 18 May 2023 14:57:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230095AbjERS5A (ORCPT ); Thu, 18 May 2023 14:57:00 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F5B2E51; Thu, 18 May 2023 11:56:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C9E77651B2; Thu, 18 May 2023 18:56:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 66F9BC433A0; Thu, 18 May 2023 18:56:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436218; bh=KmkRRVkb2zPg16/+5SP/TqktZEzO+CbiEGfvCZls0Vs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EDdT7AyS81YPAnffSgoZvef1gPV9a5EzUleOkNdMKnOCnVW6oLa9L+jqaWFy1y6DM UNlmgX+OumKc4rqRDnunVnrjm2OM17/479A7ed75G1/7a1sZ1vFLoXuWSXO+Y+XcEl XpJbGdD2AxW6wM37rBW0ZdW59dydpuNwrglrUXdgk4N02oYas/6fKzdrsPoNnJNc5L YqNDGzEtWzCPv3b16VqmBOwnOTZkg9jVlBY7bl+v22GWuHTcj1vfmNzOmPG6LDv9wN 7kOJAfN2ZztrUtISdoGBSD4x8QcMKKkdPxllRGE+tiJGb51EmK3trcDlt/5dHrG8cn XI6D2GSmacMsg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 2/9] dt-bindings: timer: Add T-HEAD TH1520 clint Date: Fri, 19 May 2023 02:45:34 +0800 Message-Id: <20230518184541.2627-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for the T-HEAD TH1520 clint. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 94bef9424df1..388d3385d7eb 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - thead,th1520-clint - const: thead,c900-clint - items: - const: sifive,clint0 --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67D35C77B7A for ; Thu, 18 May 2023 18:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbjERS5G (ORCPT ); Thu, 18 May 2023 14:57:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbjERS5D (ORCPT ); Thu, 18 May 2023 14:57:03 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C015E52; Thu, 18 May 2023 11:57:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F3A8C614CA; Thu, 18 May 2023 18:57:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9743AC4339E; Thu, 18 May 2023 18:56:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436221; bh=ayCUu7VWTParlzqlhysZ/3yMoFf8bKiG9G6ke1+jMJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bk41F/OJXLE+OA+bkypJqEMkcA4OcdwSmKYtN4q6m6SVlGG9YWXwH7FfaQClnLhwB SFOmC8XoQ9wUmaOsHiPreGL8eUEYVNmUDPijwPOJDy9Lczx3zXZ+KohWgdUDBZ4zZk 8FkVWqpsiaSsT9jHknJmsTvhZa3tg0RaZpNyohe4c+4Rnf1e6SSL0lec9vcPauXmmX YKEOmhM0edn3+YfkOFjNOoWeoov0Qa1ibfk0ks3ghjYgozf9W2xzpFuRYlHov6Jz0Y Bx9zzwPWh+SjoaMPSedIZNonW1Q1tT7ZxdszhpyWbxR5RjtUSYbTlGEeKoC/21I0Ku JvW03+ywiDL1A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 3/9] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Date: Fri, 19 May 2023 02:45:35 +0800 Message-Id: <20230518184541.2627-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Several SoMs and boards are available that feature the T-HEAD TH1520 SoC. Document the compatible strings. Signed-off-by: Jisheng Zhang --- .../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documenta= tion/devicetree/bindings/riscv/thead.yaml new file mode 100644 index 000000000000..e62f6821372e --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD SoC-based boards + +maintainers: + - Jisheng Zhang + +description: + T-HEAD SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Modul= e 4A + items: + - enum: + - sipeed,lichee-pi-4a + - const: sipeed,lichee-module-4a + - const: thead,th1520 + +additionalProperties: true + +... --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 911BDC77B7A for ; Thu, 18 May 2023 18:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230148AbjERS5S (ORCPT ); Thu, 18 May 2023 14:57:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230142AbjERS5M (ORCPT ); Thu, 18 May 2023 14:57:12 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3458E7D; Thu, 18 May 2023 11:57:05 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3375861B56; Thu, 18 May 2023 18:57:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C7685C4339B; Thu, 18 May 2023 18:57:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436224; bh=Nt5XnCpe1ezvh1ILRVySirsoVP1f3952Ou9DF76XFOQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hVM9QbkTan5hxlgEYa3QeGODzjLKHMp6w/OAt9LlH6FCGSltcldDO0BUtI3oF8UFm taDbaDlW+RNfTO7NitSBmHqK2wkbjgvosrUL1y3C2jB7u1ilVrMoRLixfBR2hnO2Mp /mUC6OVpYa0Me9zmuh9bT+2tVSe8JWiMesvZdVwv26q6K2m+xstiPeQtherWnNU8h2 UoMncU6IRtgNfNJRqm4X+y2uhNhcNneHsN6Ya4WY+HCICFGs45E3zI2alqvhHfG7DJ +b/6CWh6Sa6bZGjzNx3rySyjUjIh8UabaISQkizjpxFtTNv4MOtzlNLLAYoSqg+eMC puwni+5V6oMyQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 4/9] dt-binding: riscv: add T-HEAD CPU reset Date: Fri, 19 May 2023 02:45:36 +0800 Message-Id: <20230518184541.2627-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The secondary CPUs in T-HEAD SMP capable platforms need some special handling. The first one is to write the warm reset entry to entry register. The second one is write a SoC specific control value to a SoC specific control reg. The last one is to clone some CSRs for secondary CPUs to ensure these CSRs' values are the same as the main boot CPU. This DT node is mainly used by opensbi firmware. Signed-off-by: Jisheng Zhang --- .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset= .yaml diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b= /Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml new file mode 100644 index 000000000000..ba8c87583b6b --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD cpu reset controller + +maintainers: + - Jisheng Zhang + +description: | + The secondary CPUs in T-HEAD SMP capable platforms need some special + handling. The first one is to write the warm reset entry to entry + register. The second one is write a SoC specific control value to + a SoC specific control reg. The last one is to clone some CSRs for + secondary CPUs to ensure these CSRs' values are the same as the + main boot CPU. + +properties: + $nodename: + pattern: "^cpurst" + + compatible: + oneOf: + - description: CPU reset on T-HEAD TH1520 SoC + items: + - const: thead,reset-th1520 + + entry-reg: + $ref: /schemas/types.yaml#/definitions/uint64 + description: | + The entry reg address. + + entry-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The entry reg count. + + control-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The control reg address. + + control-val: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The value to be set into the control reg. + + csr-copy: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + The CSR registers to be cloned during CPU warm reset. + +required: + - compatible + +additionalProperties: false + +examples: + - | + cpurst: cpurst@ffff019050 { + compatible =3D "thead,reset-th1520"; + entry-reg =3D <0xff 0xff019050>; + entry-cnt =3D <4>; + control-reg =3D <0xff 0xff015004>; + control-val =3D <0x1c>; + csr-copy =3D <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0497C77B7A for ; Thu, 18 May 2023 18:57:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230142AbjERS50 (ORCPT ); Thu, 18 May 2023 14:57:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229454AbjERS5Q (ORCPT ); Thu, 18 May 2023 14:57:16 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2CC81702; Thu, 18 May 2023 11:57:08 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 6270164FCD; Thu, 18 May 2023 18:57:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03542C4331E; Thu, 18 May 2023 18:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436227; bh=Hxt77XTd4sJ4iSsW4a+tGjggeRmSDhhjr46ffLnz1is=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ozM0GDlhAZV8HvMUYO9tXWmKQKFJ9BVbHZS3eBKkSx/LEFwoXPchpJCjWLpb4zp5K exANsNP2OcsiyOaErwuldCtwi97q3hKqXFUXC5e9rXiiX/u5WFwp9KD2rc0tTv6eWP o9GzOQYbCiH2x4EGtMDkWy0hd1hUMHiI9bDqfGu2E5w9njF9Q90a+FpJED1rUXLWGx ICt8X8CP4RQxC00MmpdH/7bWShTEqX2d9XcEJJ2zo267E7fJgybAKWTsLKNhcmyEXq RFPVyuLF7YlNMHb7rB7hjWivqCR5d/pMnh9ES2G0fMqXPQw9ikRg9PzpGwWVklQwak jh/dLVW4bHlug== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 5/9] riscv: Add the T-HEAD SoC family Kconfig option Date: Fri, 19 May 2023 02:45:37 +0800 Message-Id: <20230518184541.2627-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD C910 cores. Signed-off-by: Jisheng Zhang Reviewed-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 1cf69f958f10..ce10a38dff37 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -41,6 +41,12 @@ config ARCH_SUNXI This enables support for Allwinner sun20i platform hardware, including boards based on the D1 and D1s SoCs. =20 +config ARCH_THEAD + bool "T-HEAD RISC-V SoCs" + select ERRATA_THEAD + help + This enables support for the RISC-V based T-HEAD SoCs. + config ARCH_VIRT def_bool SOC_VIRT =20 --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA23FC77B7A for ; Thu, 18 May 2023 18:57:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230162AbjERS5g (ORCPT ); Thu, 18 May 2023 14:57:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230150AbjERS51 (ORCPT ); Thu, 18 May 2023 14:57:27 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B308CE53; Thu, 18 May 2023 11:57:12 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 922E0651B3; Thu, 18 May 2023 18:57:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3488EC4339B; Thu, 18 May 2023 18:57:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436231; bh=2rqP/5lp09dAs7KjFgn+qsNlAk61u7AjjbQzzAEXDO4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mgzU+3JvEg3f3/WI7IahDByEXfCY/IMaC31gfTa1PEtYadTOkA/BYLXfGxGdCP5W+ vep3pxz6tSfoQHV4tj296b++HH/77rQMO1wUNxBk9nB5zVMUFKFjHXdj1phymwUSsv TZO1m06sIiCyGWwFvd3Dhaq8q0cBoZm1mdxsqu8yU3ivymoSqVfu7xFR+xZrQeZwm9 mD/kGG6uM6iG428MohooytX0efxznEv4Ti3PVN8tpBJjOGRiFrlxi6gUoMEszQr/oR Cygog7u24I2O1p0A+6fFxQ9WljciQpALcVWtcKEHcmpI7vCA4sgPEaeE7lfKmJxVaG QyPAatJ8HaJ2A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 6/9] riscv: dts: add initial T-HEAD TH1520 SoC device tree Date: Fri, 19 May 2023 02:45:38 +0800 Message-Id: <20230518184541.2627-7-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++ 1 file changed, 451 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi new file mode 100644 index 000000000000..60754d7c6319 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Alibaba Group Holding Limited. + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible =3D "thead,th1520"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <3000000>; + + c910_0: cpu@0 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_1: cpu@1 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_2: cpu@2 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + c910_3: cpu@3 { + compatible =3D "thead,c910", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&c910_0>; + }; + + core1 { + cpu =3D <&c910_1>; + }; + + core2 { + cpu =3D <&c910_2>; + }; + + core3 { + cpu =3D <&c910_3>; + }; + }; + }; + + l2_cache: l2-cache { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; + + osc: oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_24m"; + #clock-cells =3D <0>; + }; + + osc_32k: 32k-oscillator { + compatible =3D "fixed-clock"; + clock-output-names =3D "osc_32k"; + #clock-cells =3D <0>; + }; + + apb_clk: apb-clk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "apb_clk"; + #clock-cells =3D <0>; + }; + + uart_sclk: uart-sclk-clock { + compatible =3D "fixed-clock"; + clock-output-names =3D "uart_sclk"; + #clock-cells =3D <0>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + cpurst: cpurst { + compatible =3D "thead,reset-th1520"; + entry-reg =3D <0xff 0xff019050>; + entry-cnt =3D <4>; + control-reg =3D <0xff 0xff015004>; + control-val =3D <0x1c>; + csr-copy =3D <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>; + }; + + plic: interrupt-controller@ffd8000000 { + compatible =3D "thead,th1520-plic", "thead,c900-plic"; + reg =3D <0xff 0xd8000000 0x0 0x01000000>; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + riscv,ndev =3D <240>; + }; + + clint: timer@ffdc000000 { + compatible =3D "thead,th1520-clint", "thead,c900-clint"; + reg =3D <0xff 0xdc000000 0x0 0x00010000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>; + }; + + uart0: serial@ffe7014000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7014000 0x0 0x4000>; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart1: serial@ffe7f00000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f00000 0x0 0x4000>; + interrupts =3D <37 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart3: serial@ffe7f04000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xe7f04000 0x0 0x4000>; + interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + gpio2: gpio@ffe7f34000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f34000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portc: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <58 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@ffe7f38000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xe7f38000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portd: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <59 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio0: gpio@ffec005000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec005000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porta: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <56 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffec006000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xec006000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portb: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <57 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + uart2: serial@ffec010000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xec010000 0x0 0x4000>; + interrupts =3D <38 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + dmac0: dma-controller@ffefc00000 { + compatible =3D "snps,axi-dma-1.01a"; + reg =3D <0xff 0xefc00000 0x0 0x1000>; + interrupts =3D <27 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&apb_clk>, <&apb_clk>; + clock-names =3D "core-clk", "cfgr-clk"; + #dma-cells =3D <1>; + dma-channels =3D <4>; + snps,block-size =3D <65536 65536 65536 65536>; + snps,priority =3D <0 1 2 3>; + snps,dma-masters =3D <1>; + snps,data-width =3D <4>; + snps,axi-max-burst-len =3D <16>; + status =3D "disabled"; + }; + + timer0: timer@ffefc32000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer1: timer@ffefc32014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer2: timer@ffefc32028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc32028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <18 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer3: timer@ffefc3203c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xefc3203c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + uart4: serial@fff7f08000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f08000 0x0 0x4000>; + interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + uart5: serial@fff7f0c000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0xff 0xf7f0c000 0x0 0x4000>; + interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&uart_sclk>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + + timer4: timer@ffffc33000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33000 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer5: timer@ffffc33014 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33014 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer6: timer@ffffc33028 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc33028 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <22 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + timer7: timer@ffffc3303c { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xff 0xffc3303c 0x0 0x14>; + clocks =3D <&apb_clk>; + clock-names =3D "timer"; + interrupts =3D <23 IRQ_TYPE_LEVEL_HIGH>; + status =3D "disabled"; + }; + + ao_gpio0: gpio@fffff41000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff41000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + porte: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <76 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ao_gpio1: gpio@fffff52000 { + compatible =3D "snps,dw-apb-gpio"; + reg =3D <0xff 0xfff52000 0x0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + portf: gpio-controller@0 { + compatible =3D "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells =3D <2>; + ngpios =3D <32>; + reg =3D <0>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D <55 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13498C7EE25 for ; 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s=k20201202; t=1684436234; bh=SPhHXPcnyMrXjaiP7DOxwbB5VjmdUJq9U0kUEmDjQ0w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kahOTcxTy32CFM9eHd/MHg6lpg/GXB3H9L5itF0hjkwIgLWkXf14++KVJUXdJsHhx 2hSOWca+EOez7Tsd73O5z396YvhAC2TJwFiUIm51230K1jbg0ts8DXU2EML0wimE7y CCuZT5F6PT1KeRQdFIssnO0sC42+p5sG0mCB/Zir3xQvV724B35dt74iEMtLs5x0dP Ftg/9JWwfTIpc+GWix2ZSbBX9iA5zYgE7Zk7wmNH5Zdlfp2l2PRENKUKXIsYRjGcng FuSLVOCLPMoNgR/FHr5IXiEUe96qyaIzc5zGp2gh3FN+/23CozongCD3Wy2P9YiEnx L35M74T2aOEYA== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 7/9] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree Date: Fri, 19 May 2023 02:45:39 +0800 Message-Id: <20230518184541.2627-8-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/thead/Makefile | 2 + .../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++ .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/riscv/boot/dts/thead/Makefile create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f0d9f89054f8..1e884868ccba 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -2,6 +2,7 @@ subdir-y +=3D allwinner subdir-y +=3D sifive subdir-y +=3D starfive +subdir-y +=3D thead subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead= /Makefile new file mode 100644 index 000000000000..e311fc9a5939 --- /dev/null +++ b/arch/riscv/boot/dts/thead/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_THEAD) +=3D th1520-lichee-pi-4a.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/= riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi new file mode 100644 index 000000000000..4b0249ac710f --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model =3D "Sipeed Lichee Module 4A"; + compatible =3D "sipeed,lichee-module-4a", "thead,th1520"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x0 0x00000000 0x2 0x00000000>; + }; +}; + +&osc { + clock-frequency =3D <24000000>; +}; + +&osc_32k { + clock-frequency =3D <32768>; +}; + +&apb_clk { + clock-frequency =3D <62500000>; +}; + +&uart_sclk { + clock-frequency =3D <100000000>; +}; + +&dmac0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts new file mode 100644 index 000000000000..a1248b2ee3a3 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include "th1520-lichee-module-4a.dtsi" + +/ { + model =3D "Sipeed Lichee Pi 4A"; + compatible =3D "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,t= h1520"; + + aliases { + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + gpio2 =3D &gpio2; + gpio3 =3D &gpio3; + serial0 =3D &uart0; + serial1 =3D &uart1; + serial2 =3D &uart2; + serial3 =3D &uart3; + serial4 =3D &uart4; + serial5 =3D &uart5; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75C81C7EE23 for ; Thu, 18 May 2023 18:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230062AbjERS5r (ORCPT ); Thu, 18 May 2023 14:57:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230176AbjERS5l (ORCPT ); Thu, 18 May 2023 14:57:41 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1E7A10C3; Thu, 18 May 2023 11:57:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 067DD651B9; Thu, 18 May 2023 18:57:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9DC6AC433A0; Thu, 18 May 2023 18:57:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436237; bh=vxBYR6LtHdTWo59agyMO2DjmnNEXIpF3f4ssS0Pr5DU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Km1I+KHyYtnUN0pmY1DDp07p0EmyV4uwgUlqNQjv0THFIX/Z+sDhlyrED7Snmr5wG EBwNATQzc89st4HbSJmDYMmrm3w5yciXzJkyjUc+sHSRI2QyKKTCULLkts4umpWAPE p4BxzkN2XkbTv1TzN86ZSgOUu6hTmJk3+/q4/QMDejKNDiIUzJYtXfm2+2RY0/bv0D UkhQ4NdCtw5rhpLhGbdcsmSM9lmdgliu5oHuN4yitls/IWMiqrzlzN7B8GFzYRiIar fvM366GxuOHSbd2dOom/rA2HjSkRZegJ5yQrRcbVnbJWK+qeAac5OuPgLLE5MR42l2 Uw2Bj7cE/XPlQ== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 8/9] MAINTAINERS: add entry for T-HEAD RISC-V SoC Date: Fri, 19 May 2023 02:45:40 +0800 Message-Id: <20230518184541.2627-9-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, I would like to maintain the T-HEAD RISC-V SoC support. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e0ad886d3163..6df20c65798a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18162,6 +18162,12 @@ F: drivers/perf/riscv_pmu.c F: drivers/perf/riscv_pmu_legacy.c F: drivers/perf/riscv_pmu_sbi.c =20 +RISC-V THEAD SoC SUPPORT +M: Jisheng Zhang +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/thead/ + RNBD BLOCK DRIVERS M: Md. Haris Iqbal M: Jack Wang --=20 2.40.0 From nobody Sun Dec 14 03:24:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8007C77B7A for ; Thu, 18 May 2023 18:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbjERS55 (ORCPT ); Thu, 18 May 2023 14:57:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230133AbjERS5p (ORCPT ); Thu, 18 May 2023 14:57:45 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC17910E9; Thu, 18 May 2023 11:57:22 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3CB4C64FCD; Thu, 18 May 2023 18:57:21 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE1CDC4339B; Thu, 18 May 2023 18:57:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684436240; bh=+8gBhUykoZM8TrvHxezwEoqx6vcc9txPAEKaZGcJ4uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZfU52L68DqN1YEclN4xauwvlvDjt1TExLclICt6uv1q20JIejrXEOSecNLjbfZqz7 JJQ+6OMTx6RM13fMAta6Iuy5IdDry0ywDr6F6d59rPIKbgFmHvXHVvFT1OxXgXEoHX nkIDH5iXcHMbI2hhQg9j+8iNBjOpS4tBHXxm66FjoMCKw0liH8kyALT0X62UFJ3wFE VWpEA7TfQb79Vae3ejwi0fhTTCiooz2bgyEbWKar20iS3LJu6dvxWvavBUys/djyFi 8CpqtjNAOU1D1zoTmrNPTCt2hOWang2hhmG/IYk4q8gMfeTpksG/mXoNvxHUrh9qS9 QZZns6KoH2r9A== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Guo Ren Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Yangtao Li , Wei Fu , Icenowy Zheng Subject: [PATCH v2 9/9] riscv: defconfig: enable T-HEAD SoC Date: Fri, 19 May 2023 02:45:41 +0800 Message-Id: <20230518184541.2627-10-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230518184541.2627-1-jszhang@kernel.org> References: <20230518184541.2627-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable T-HEAD SoC config in defconfig to allow the default upstream kernel to boot on Sipeed Lichee Pi 4A board. Signed-off-by: Jisheng Zhang Acked-by: Guo Ren Acked-by: Palmer Dabbelt Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..109e4b5b003c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -27,6 +27,7 @@ CONFIG_EXPERT=3Dy CONFIG_PROFILING=3Dy CONFIG_SOC_MICROCHIP_POLARFIRE=3Dy CONFIG_ARCH_RENESAS=3Dy +CONFIG_ARCH_THEAD=3Dy CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy CONFIG_ARCH_SUNXI=3Dy --=20 2.40.0