From nobody Mon Feb 9 17:06:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8842CC7EE23 for ; Thu, 18 May 2023 11:40:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231360AbjERLkk (ORCPT ); Thu, 18 May 2023 07:40:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231332AbjERLkh (ORCPT ); Thu, 18 May 2023 07:40:37 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3140810C6 for ; Thu, 18 May 2023 04:40:14 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-306dbad5182so1268880f8f.1 for ; Thu, 18 May 2023 04:40:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684409993; x=1687001993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2LcnYqoHcZvLzA6Z3GL7iXhdSd41fT2YfxCPjhoX5Gg=; b=J19eqrqYxAX/RlpALBD7A4d7onhmQpGgddCk9FD0mP0a2jtRYbLlSFbRBMa4avh0go AvrsPn+q5UYMxVnW6o0UoRxPhM0kEUICgtxpkaj8hpaMBSBluDyyer1pveBy/4orbVat RvzlMKBxmO95vsCnEnvkF6Z8KWYbtMlTdqUR2Kzvoh9Zx5ghSBBr80ehtnSyftgh2WuJ 0NCza6BNQHgEnGG6yZVk5H+2R+8mZRbh4TI+hOo+juzLnnn+JoW9zyQh+Jnov3snIT9A BX1fUTjYRgRtWyQoXTCfXHNsJoaTH/UWCRvj38ms2DfZ5b4APBvuAdxp8x5hWpaE70WP vP9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684409993; x=1687001993; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2LcnYqoHcZvLzA6Z3GL7iXhdSd41fT2YfxCPjhoX5Gg=; b=L8t9iRYmGMLfMj3F1Zpo66+lmfrHcfLxdZExXDdIsMFWCYUnNSasZlxnCyeV9FQ4yb J3umorSmiwxtVLEAvZhyRi8yTmrFMfL5ozLl9z/kT6v75gcSITNAtuze680GjUPER+t4 9MZmA6OQ4ZE/rOTr46jz80wU85h9H5EPy3f1BvO4HOHYkLqnu2elYIoXnXp/JaPNfAjy BAqeqIJzDaRYmTbuvosTNzDhKWlqrzTNoZHuwLZTtbUYYCs70a6BkKrEPJXIEgejE9AD fazgpb+dglsXE0LBG8blG2MiLiGqWPkLI5EiwREvy0K1zuZ5wDjd5yb+Fn83rw8X9Oiy 4ICg== X-Gm-Message-State: AC+VfDzHC5m5TnErzzsFCfd8RorqoS0r0qMZOu90YlCBoaKCvM0Fgc6M g9K3oH8VpDlUjyxDCoVfuCvZRA== X-Google-Smtp-Source: ACHHUZ5ioBYKk2HoOTJ7/GOsCLfIkRsICz8W5l4WVwP7qy21i4PiTpTnZnCzG8rRg4T4CoVmr2rsEg== X-Received: by 2002:adf:cd0e:0:b0:2f5:8e8b:572c with SMTP id w14-20020adfcd0e000000b002f58e8b572cmr1637884wrm.49.1684409992852; Thu, 18 May 2023 04:39:52 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id f14-20020a5d568e000000b003047d5b8817sm1897135wrv.80.2023.05.18.04.39.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:52 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 1/5] dt-bindings: clock: Add YAML schemas for LPASSCC and reset on SC8280XP Date: Thu, 18 May 2023 12:37:56 +0100 Message-Id: <20230518113800.339158-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LPASS(Low Power Audio Subsystem) clock provider provides reset controller support when is driven by the Q6DSP. This patch adds support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 57 +++++++++++++++++++ .../dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 12 ++++ 2 files changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8280xp-l= passcc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.= yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml new file mode 100644 index 000000000000..7c30614a0af9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP + +maintainers: + - Srinivas Kandagatla + +description: | + Qualcomm LPASS core and audio clock control module provides the clocks, + reset and power domains on SC8280XP. + + See also:: + include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h + +properties: + reg: true + + compatible: + enum: + - qcom,sc8280xp-lpasscc + + '#reset-cells': + const: 1 + + '#clock-cells': + const: 1 + + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + peripheral loader. + type: boolean + +required: + - compatible + - reg + - qcom,adsp-pil-mode + - '#reset-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + lpasscc: clock-controller@3900000 { + compatible =3D "qcom,sc8280xp-lpasscc"; + reg =3D <0x033e0000 0x12000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + qcom,adsp-pil-mode; + }; +... diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt= -bindings/clock/qcom,lpasscc-sc8280xp.h new file mode 100644 index 000000000000..df800ea2741c --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H + +/* LPASS TCSR */ +#define LPASS_AUDIO_SWR_TX_CGCR 0 + +#endif --=20 2.25.1 From nobody Mon Feb 9 17:06:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5054FC77B7A for ; Thu, 18 May 2023 11:40:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231405AbjERLko (ORCPT ); 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Thu, 18 May 2023 04:39:53 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/5] dt-bindings: clock: Add YAML schemas for LPASS AUDIOCC and reset on SC8280XP Date: Thu, 18 May 2023 12:37:57 +0100 Message-Id: <20230518113800.339158-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LPASS(Low Power Audio Subsystem) Audio clock provider provides reset controller support when is driven by the Q6DSP. This patch adds support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.= yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 7c30614a0af9..394833819ba3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - qcom,sc8280xp-lpasscc + - qcom,sc8280xp-lpassaudiocc =20 '#reset-cells': const: 1 @@ -45,6 +46,16 @@ required: additionalProperties: false =20 examples: + - | + #include + lpass_audiocc: clock-controller@3300000 { + compatible =3D "qcom,sc8280xp-lpassaudiocc"; + reg =3D <0x32a9000 0x1000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + qcom,adsp-pil-mode; + }; + - | #include lpasscc: clock-controller@3900000 { diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt= -bindings/clock/qcom,lpasscc-sc8280xp.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H =20 +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 =20 --=20 2.25.1 From nobody Mon Feb 9 17:06:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E001C7EE24 for ; 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Thu, 18 May 2023 04:39:55 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id f14-20020a5d568e000000b003047d5b8817sm1897135wrv.80.2023.05.18.04.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:55 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 3/5] clk: qcom: Add lpass clock controller driver for SC8280XP Date: Thu, 18 May 2023 12:37:58 +0100 Message-Id: <20230518113800.339158-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the lpass clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/Kconfig | 8 ++++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscc-sc8280xp.c | 71 +++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 drivers/clk/qcom/lpasscc-sc8280xp.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 12be3e2371b3..8188f4dedf40 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -514,6 +514,14 @@ config SC_GPUCC_8280XP Say Y if you want to support graphics controller devices and functionality such as 3D graphics. =20 +config SC_LPASSCC_8280XP + tristate "SC8280 Low Power Audio Subsystem (LPASS) Clock Controller" + select SC_GCC_8280XP + help + Support for the LPASS clock controller on SC8280XP devices. + Say Y if you want to use the LPASS branch clocks of the LPASS clock + controller to reset the LPASS subsystem. + config SC_LPASSCC_7280 tristate "SC7280 Low Power Audio Subsystem (LPASS) Clock Controller" select SC_GCC_7280 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 9ff4c373ad95..dce2dd639524 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SC_CAMCC_7280) +=3D camcc-sc7280.o obj-$(CONFIG_SC_DISPCC_7180) +=3D dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) +=3D dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) +=3D dispcc-sc8280xp.o +obj-$(CONFIG_SC_LPASSCC_8280XP) +=3D lpasscc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) +=3D gcc-sa8775p.o obj-$(CONFIG_SA_GPUCC_8775P) +=3D gpucc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) +=3D gcc-sc7180.o diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc= -sc8280xp.c new file mode 100644 index 000000000000..118320f8ee40 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "reset.h" + +static const struct qcom_reset_map lpass_tcsr_sc8280xp_resets[] =3D { + [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xc010, 1 }, +}; + +static struct regmap_config lpass_tcsr_sc8280xp_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-tcsr", + .max_register =3D 0x12000, +}; + +static const struct qcom_cc_desc lpass_tcsr_reset_sc8280xp_desc =3D { + .config =3D &lpass_tcsr_sc8280xp_regmap_config, + .resets =3D lpass_tcsr_sc8280xp_resets, + .num_resets =3D ARRAY_SIZE(lpass_tcsr_sc8280xp_resets), +}; + +static const struct of_device_id lpasscc_sc8280xp_match_table[] =3D { + { + .compatible =3D "qcom,sc8280xp-lpasscc", + .data =3D &lpass_tcsr_reset_sc8280xp_desc, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpasscc_sc8280xp_match_table); + +static int lpasscc_sc8280xp_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc =3D of_device_get_match_data(&pdev->dev); + + return qcom_cc_probe_by_index(pdev, 0, desc); +} + +static struct platform_driver lpasscc_sc8280xp_driver =3D { + .probe =3D lpasscc_sc8280xp_probe, + .driver =3D { + .name =3D "lpasscc-sc8280xp", + .of_match_table =3D lpasscc_sc8280xp_match_table, + }, +}; + +static int __init lpasscc_sc8280xp_init(void) +{ + return platform_driver_register(&lpasscc_sc8280xp_driver); +} +subsys_initcall(lpasscc_sc8280xp_init); + +static void __exit lpasscc_sc8280xp_exit(void) +{ + platform_driver_unregister(&lpasscc_sc8280xp_driver); +} +module_exit(lpasscc_sc8280xp_exit); + +MODULE_DESCRIPTION("QTI LPASSCC SC8280XP Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon Feb 9 17:06:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4F15C77B7A for ; Thu, 18 May 2023 11:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230311AbjERLlB (ORCPT ); Thu, 18 May 2023 07:41:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231276AbjERLku (ORCPT ); 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Thu, 18 May 2023 04:39:56 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 4/5] clk: qcom: Add lpass audio clock controller driver for SC8280XP Date: Thu, 18 May 2023 12:37:59 +0100 Message-Id: <20230518113800.339158-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/lpasscc-sc8280xp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc= -sc8280xp.c index 118320f8ee40..e221ae2d40ae 100644 --- a/drivers/clk/qcom/lpasscc-sc8280xp.c +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -13,6 +13,26 @@ #include "common.h" #include "reset.h" =20 +static const struct qcom_reset_map lpass_audio_csr_sc8280xp_resets[] =3D { + [LPASS_AUDIO_SWR_RX_CGCR] =3D { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] =3D { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] =3D { 0xd8, 1 }, +}; + +static struct regmap_config lpass_audio_csr_sc8280xp_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .name =3D "lpass-audio-csr", + .max_register =3D 0x1000, +}; + +static const struct qcom_cc_desc lpass_audio_csr_reset_sc8280xp_desc =3D { + .config =3D &lpass_audio_csr_sc8280xp_regmap_config, + .resets =3D lpass_audio_csr_sc8280xp_resets, + .num_resets =3D ARRAY_SIZE(lpass_audio_csr_sc8280xp_resets), +}; + static const struct qcom_reset_map lpass_tcsr_sc8280xp_resets[] =3D { [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xc010, 1 }, }; @@ -33,6 +53,9 @@ static const struct qcom_cc_desc lpass_tcsr_reset_sc8280x= p_desc =3D { =20 static const struct of_device_id lpasscc_sc8280xp_match_table[] =3D { { + .compatible =3D "qcom,sc8280xp-lpassaudiocc", + .data =3D &lpass_audio_csr_reset_sc8280xp_desc, + }, { .compatible =3D "qcom,sc8280xp-lpasscc", .data =3D &lpass_tcsr_reset_sc8280xp_desc, }, --=20 2.25.1 From nobody Mon Feb 9 17:06:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AE79C77B7A for ; Thu, 18 May 2023 11:40:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230464AbjERLk6 (ORCPT ); Thu, 18 May 2023 07:40:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231431AbjERLkv (ORCPT ); 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Thu, 18 May 2023 04:39:57 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 5/5] arm64: dts: qcom: sc8280xp: add resets for soundwire controllers Date: Thu, 18 May 2023 12:38:00 +0100 Message-Id: <20230518113800.339158-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Soundwire controllers on sc8280xp needs an explicit reset, this patch adds support for this. Signed-off-by: Srinivas Kandagatla --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index d2a2224d138a..a2d0f8abe23d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -2548,6 +2549,8 @@ rxmacro: rxmacro@3200000 { swr1: soundwire-controller@3210000 { compatible =3D "qcom,soundwire-v1.6.0"; reg =3D <0 0x03210000 0 0x2000>; + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names =3D "swr_audio_cgcr"; interrupts =3D ; clocks =3D <&rxmacro>; clock-names =3D "iface"; @@ -2647,6 +2650,13 @@ swr0: soundwire-controller@3250000 { status =3D "disabled"; }; =20 + lpass_audiocc: clock-controller@3300000 { + compatible =3D "qcom,sc8280xp-lpassaudiocc"; + reg =3D <0 0x032a9000 0 0x1000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + }; + swr2: soundwire-controller@3330000 { compatible =3D "qcom,soundwire-v1.6.0"; reg =3D <0 0x03330000 0 0x2000>; @@ -2654,6 +2664,8 @@ swr2: soundwire-controller@3330000 { ; interrupt-names =3D "core", "wakeup"; =20 + resets =3D <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names =3D "swr_audio_cgcr"; clocks =3D <&txmacro>; clock-names =3D "iface"; label =3D "TX"; @@ -2849,6 +2861,13 @@ data-pins { }; }; =20 + lpasscc: clock-controller@33e0000 { + compatible =3D "qcom,sc8280xp-lpasscc"; + reg =3D <0 0x033e0000 0 0x21000>; + #reset-cells =3D <1>; + #clock-cells =3D <1>; + }; + usb_0_qmpphy: phy@88eb000 { compatible =3D "qcom,sc8280xp-qmp-usb43dp-phy"; reg =3D <0 0x088eb000 0 0x4000>; --=20 2.25.1