From nobody Wed Dec 17 13:21:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4F11C7EE2E for ; Thu, 18 May 2023 11:28:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231304AbjERL2i (ORCPT ); Thu, 18 May 2023 07:28:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230434AbjERL2G (ORCPT ); Thu, 18 May 2023 07:28:06 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F89F199F; Thu, 18 May 2023 04:28:01 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 9324724E266; Thu, 18 May 2023 19:27:59 +0800 (CST) Received: from EXMBX171.cuchost.com (172.16.6.91) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 18 May 2023 19:27:59 +0800 Received: from ubuntu.localdomain (113.72.146.100) by EXMBX171.cuchost.com (172.16.6.91) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 18 May 2023 19:27:58 +0800 From: Minda Chen To: Emil Renner Berthing , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Pawel Laszczak , Greg Kroah-Hartman , Peter Chen , Roger Quadros , Philipp Zabel CC: , , , , , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Minda Chen" , Mason Huo Subject: [PATCH v6 7/7] riscv: dts: starfive: Add USB dts configuration for JH7110 Date: Thu, 18 May 2023 19:27:50 +0800 Message-ID: <20230518112750.57924-8-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230518112750.57924-1-minda.chen@starfivetech.com> References: <20230518112750.57924-1-minda.chen@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.146.100] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX171.cuchost.com (172.16.6.91) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. USB controller connect to PHY, The PHY dts configuration are also added. Signed-off-by: Minda Chen --- .../jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 53 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1155b97b593d..934453bc80d5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -221,3 +221,8 @@ pinctrl-0 =3D <&uart0_pins>; status =3D "okay"; }; + +&usb0 { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 71a8e9acbe55..b65f06c5b1b7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -366,6 +366,59 @@ status =3D "disabled"; }; =20 + usb0: usb@10100000 { + compatible =3D "starfive,jh7110-usb"; + ranges =3D <0x0 0x0 0x10100000 0x100000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + starfive,stg-syscon =3D <&stg_syscon 0x4>; + clocks =3D <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names =3D "lpm", "stb", "apb", "axi", "utmi_apb"; + resets =3D <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names =3D "pwrup", "apb", "axi", "utmi_apb"; + status =3D "disabled"; + + usb_cdns3: usb@0 { + compatible =3D "cdns,usb3"; + reg =3D <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names =3D "otg", "xhci", "dev"; + interrupts =3D <100>, <108>, <110>; + interrupt-names =3D "host", "peripheral", "otg"; + phys =3D <&usbphy0>; + phy-names =3D "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible =3D "starfive,jh7110-usb-phy"; + reg =3D <0x0 0x10200000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names =3D "125m", "app_125m"; + #phy-cells =3D <0>; + }; + + pciephy0: phy@10210000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x0 0x10210000 0x0 0x10000>; + #phy-cells =3D <0>; + }; + + pciephy1: phy@10220000 { + compatible =3D "starfive,jh7110-pcie-phy"; + reg =3D <0x0 0x10220000 0x0 0x10000>; + #phy-cells =3D <0>; + }; + stgcrg: clock-controller@10230000 { compatible =3D "starfive,jh7110-stgcrg"; reg =3D <0x0 0x10230000 0x0 0x10000>; --=20 2.17.1