From nobody Fri Sep 20 20:24:12 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ED01C77B7D for ; Thu, 18 May 2023 10:49:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230429AbjERKtl (ORCPT ); Thu, 18 May 2023 06:49:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbjERKtM (ORCPT ); Thu, 18 May 2023 06:49:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F76AE66 for ; Thu, 18 May 2023 03:49:11 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (unknown [IPv6:2001:b07:2ed:14ed:a962:cd4d:a84:1eab]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7343B6605962; Thu, 18 May 2023 11:49:09 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1684406950; bh=OnHuldXzfYYw/KXyKRAqozHtJCb863QWBQWMJdHX3xI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M78pdpAadPl4k2DIX+Oej/unHvgFSXgb0ub8u0stnGqVj0EHE9VuyjsJyHzWPhROz s3DE9hnQ9dwYg3iBLFuthiWBTm8EodYKFjp8/JyIE7L2sTekebrg+P+NEZbUbdZcG+ p8i4fqHsAV8xSdV9S7lNKPv29NZxkjNzCP+szo5dwWX8rXxAAtC8qh2dZzX234nCII Np9VmutoYVBLykqphv3t4y5r+6bRuYRBNPU+6rMCFjtt85oEkdY7nNF1IifjZnMVhC hzCH93WsLGYJvs7hu86qhFSnxW1cvDWbNgjRTCK5lfH4Y6pcQygKHkV6In9yYY3fVk M8EONVw3mHjtg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, "Jason-JH . Lin" Subject: [PATCH v4 09/11] drm/mediatek: gamma: Add support for 12-bit LUT and MT8195 Date: Thu, 18 May 2023 12:48:55 +0200 Message-Id: <20230518104857.124265-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230518104857.124265-1-angelogioacchino.delregno@collabora.com> References: <20230518104857.124265-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for 12-bit gamma lookup tables and introduce the first user for it: MT8195. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 61 ++++++++++++++++++----- 1 file changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index a05c445367ee..9ae08a2d7da2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -27,12 +27,20 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 =20 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) =20 +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + #define LUT_10BIT_MASK 0x03ff #define LUT_BITS_DEFAULT 10 #define LUT_SIZE_DEFAULT 512 /* for setting gamma lut from AAL */ @@ -83,14 +91,15 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct d= rm_crtc_state *state) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); - unsigned int i; + void __iomem *lut0_base =3D regs + DISP_GAMMA_LUT; + void __iomem *lut1_base =3D regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; + int cur_bank, num_lut_banks; + u16 lut_bank_size, lut_size; struct drm_color_lut *lut; - void __iomem *lut_base; + unsigned int i; bool lut_diff; - u16 lut_bank_size, lut_size; u8 lut_bits; - u32 cfg_val, lbank_val, word; - int cur_bank, num_lut_banks; =20 /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -114,14 +123,17 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt num_lut_banks =3D 1; =20 cfg_val =3D readl(regs + DISP_GAMMA_CFG); - lut_base =3D regs + DISP_GAMMA_LUT; lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 + /* Switch to 12 bits data mode if supported */ + data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits =3D=3D 12= )); + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { =20 /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val =3D FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |=3D data_mode; writel(lbank_val, regs + DISP_GAMMA_BANK); } =20 @@ -134,9 +146,15 @@ void mtk_gamma_set_common(struct device *dev, void __i= omem *regs, struct drm_crt hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); =20 if (!lut_diff || (i % 2 =3D=3D 0)) { - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red =3D lut[n].red - lut[n - 1].red; diff.red =3D drm_color_lut_extract(diff.red, lut_bits); @@ -147,11 +165,19 @@ void mtk_gamma_set_common(struct device *dev, void __= iomem *regs, struct drm_crt diff.blue =3D lut[n].blue - lut[n - 1].blue; diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 - word =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + if (lut_bits =3D=3D 12) { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] =3D FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] =3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, (lut_base + i * 4)); + writel(word[0], (lut0_base + i * 4)); + if (lut_bits =3D=3D 12) + writel(word[1], (lut1_base + i * 4)); } } =20 @@ -275,11 +301,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_= driver_data =3D { .lut_size =3D 512, }; =20 +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data =3D { + .lut_bank_size =3D 256, + .lut_bits =3D 12, + .lut_diff =3D true, + .lut_size =3D 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] =3D { { .compatible =3D "mediatek,mt8173-disp-gamma", .data =3D &mt8173_gamma_driver_data}, { .compatible =3D "mediatek,mt8183-disp-gamma", .data =3D &mt8183_gamma_driver_data}, + { .compatible =3D "mediatek,mt8195-disp-gamma", + .data =3D &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); --=20 2.40.1