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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT080.mail.protection.outlook.com (10.13.174.99) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.17 via Frontend Transport; Wed, 17 May 2023 17:23:47 +0000 Received: from BLR5CG134614W.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 17 May 2023 12:23:40 -0500 From: K Prateek Nayak To: , , , , , , , , CC: , , , , , , Subject: [PATCH v4 1/5] perf: Extract building cache level for a CPU into separate function Date: Wed, 17 May 2023 22:57:41 +0530 Message-ID: <20230517172745.5833-2-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517172745.5833-1-kprateek.nayak@amd.com> References: <20230517172745.5833-1-kprateek.nayak@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT080:EE_|BY5PR12MB4131:EE_ X-MS-Office365-Filtering-Correlation-Id: a53fb641-9b2e-423c-2b88-08db56fb7919 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 17:23:47.0123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a53fb641-9b2e-423c-2b88-08db56fb7919 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT080.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4131 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" build_caches() builds the complete cache topology of the system by iterating over all CPU, building and comparing cache levels of each CPU, keeping only the unique ones at the end. Extract the unit that build the cache levels for a single CPU into a separate function. Expose this function, and the MAX_CACHE_LVL value to be used elsewhere in perf too. Signed-off-by: K Prateek Nayak Acked-by: Ian Rogers --- Changelog: o v3->v4: - No changes --- tools/perf/util/header.c | 62 +++++++++++++++++++++++++--------------- tools/perf/util/header.h | 4 +++ 2 files changed, 43 insertions(+), 23 deletions(-) diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 276870221ce0..560871736764 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -1213,38 +1213,54 @@ static void cpu_cache_level__fprintf(FILE *out, str= uct cpu_cache_level *c) fprintf(out, "L%d %-15s %8s [%s]\n", c->level, c->type, c->size, c->map); } =20 -#define MAX_CACHE_LVL 4 - -static int build_caches(struct cpu_cache_level caches[], u32 *cntp) +/* + * Build caches levels for a particular CPU from the data in + * /sys/devices/system/cpu/cpu/cache/ + * The cache level data is stored in caches[] from index at + * *cntp. + */ +int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cn= tp) { - u32 i, cnt =3D 0; - u32 nr, cpu; u16 level; =20 - nr =3D cpu__max_cpu().cpu; + for (level =3D 0; level < MAX_CACHE_LVL; level++) { + struct cpu_cache_level c; + int err; + u32 i; =20 - for (cpu =3D 0; cpu < nr; cpu++) { - for (level =3D 0; level < MAX_CACHE_LVL; level++) { - struct cpu_cache_level c; - int err; + err =3D cpu_cache_level__read(&c, cpu, level); + if (err < 0) + return err; =20 - err =3D cpu_cache_level__read(&c, cpu, level); - if (err < 0) - return err; + if (err =3D=3D 1) + break; =20 - if (err =3D=3D 1) + for (i =3D 0; i < *cntp; i++) { + if (cpu_cache_level__cmp(&c, &caches[i])) break; + } =20 - for (i =3D 0; i < cnt; i++) { - if (cpu_cache_level__cmp(&c, &caches[i])) - break; - } + if (i =3D=3D *cntp) { + caches[*cntp] =3D c; + *cntp =3D *cntp + 1; + } else + cpu_cache_level__free(&c); + } =20 - if (i =3D=3D cnt) - caches[cnt++] =3D c; - else - cpu_cache_level__free(&c); - } + return 0; +} + +static int build_caches(struct cpu_cache_level caches[], u32 *cntp) +{ + u32 nr, cpu, cnt =3D 0; + + nr =3D cpu__max_cpu().cpu; + + for (cpu =3D 0; cpu < nr; cpu++) { + int ret =3D build_caches_for_cpu(cpu, caches, &cnt); + + if (ret) + return ret; } *cntp =3D cnt; return 0; diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h index 59eeb4a32ac5..7c16a250e738 100644 --- a/tools/perf/util/header.h +++ b/tools/perf/util/header.h @@ -179,7 +179,11 @@ int do_write(struct feat_fd *fd, const void *buf, size= _t size); int write_padded(struct feat_fd *fd, const void *bf, size_t count, size_t count_aligned); =20 +#define MAX_CACHE_LVL 4 + int is_cpu_online(unsigned int cpu); +int build_caches_for_cpu(u32 cpu, struct cpu_cache_level caches[], u32 *cn= tp); + /* * arch specific callback */ --=20 2.25.1 From nobody Sun Feb 8 08:20:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 165D9C77B7F for ; Wed, 17 May 2023 17:25:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229590AbjEQRY7 (ORCPT ); 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Wed, 17 May 2023 12:24:14 -0500 From: K Prateek Nayak To: , , , , , , , , CC: , , , , , , Subject: [PATCH v4 2/5] perf stat: Setup the foundation to allow aggregation based on cache topology Date: Wed, 17 May 2023 22:57:42 +0530 Message-ID: <20230517172745.5833-3-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517172745.5833-1-kprateek.nayak@amd.com> References: <20230517172745.5833-1-kprateek.nayak@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT015:EE_|DM6PR12MB4877:EE_ X-MS-Office365-Filtering-Correlation-Id: c18790eb-63c0-4316-5c3c-08db56fb8d78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x/+I9gaCsfTN2SubwQtCIcteL4pe4Uygs5fo5rdYwa+n6YAOsH98UKoHM6SOTge7Je960UdvAjqlo+1VlR65xXSUR1Q296g5j8UexqbKyKbEBQ9zdVEEUUs6E6ilWc7kOgGGErU7zAS/m9MoLFyD0J5JZfHHiFdfjKrAfq77bK3MDuhFcFGwjXLyrnxg0/pHtKqHz9w/HV83qzn2znKX8DzOfOhtB7NrrxQQtXpUdaNVF1/T0BAB1oQqvCzGbjg7nnox7eCHgH5qXWrdkasJQGnAhM8qPR0wx6bOb+6z0LN4od4mec0KHJXsK69l8d5kk4W7K6OqrivBWslIIFInntodQsg2HgvQFo4+HSDe9lNSg+SViVZAYCzk62+cm8F+S2jNXb5DlcmMbsNcuYE/pOUOFB1PPCK7NQYNRrSbYs7ndNvD2jSy/sNYdUMWBduHeDjqd01G1W6mFt5+nMOXHhP02NT1vlrYNkuSWNCMuinLTRK8BwWPxMB8h6bwir8+o9p/gsgeSvGvLRyBqJUF4n1/XflksuXTzvun8J3dKQ8nHTf8/HYZT69XZZGzLrad9x/G9/QRl5mDS/TtYAEUzFk8NGuSAb90n8EsT5G7Y2QjhivC1YY9e0g30K2CFgK4RxyiwsicytmzriXqivcThZI7upWMntcgyFhMhzdrvEMDo0eG9zpHXrq+gUCI0H31/MhVSTUvZTOAUnYPetsvQPFsDzefnr743UyuqQuQw5vv9iFXt8/U5k6SjswPGk5mJG/TDzGZ/rOcBTshtB7J/kTZG2qQq48qrr23039P3JA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(376002)(346002)(396003)(39860400002)(451199021)(36840700001)(40470700004)(46966006)(54906003)(70586007)(478600001)(7696005)(36756003)(70206006)(6666004)(110136005)(86362001)(40460700003)(316002)(4326008)(82310400005)(47076005)(426003)(40480700001)(336012)(186003)(107886003)(36860700001)(2616005)(356005)(82740400003)(81166007)(1076003)(7416002)(5660300002)(2906002)(41300700001)(30864003)(8936002)(8676002)(16526019)(83380400001)(26005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 17:24:21.1750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c18790eb-63c0-4316-5c3c-08db56fb8d78 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4877 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Processors based on chiplet architecture, such as AMD EPYC and Hygon do not expose the chiplet details in the sysfs CPU topology information. However, this information can be derived from the per CPU cache level information from the sysfs. perf stat has already supported aggregation based on topology information using core ID, socket ID, etc. It'll be useful to aggregate based on the cache topology to detect problems like imbalance and cache-to-cache sharing at various cache levels. This patch lays the foundation for aggregating data in perf stat based on the processor's cache topology. The cmdline option to aggregate data based on the cache topology is added in Patch 4 of the series while this patch sets up all the necessary functions and variables required to support the new aggregation option. The patch also adds support to display per-cache aggregation, or save it as a JSON or CSV, as splitting it into a separate patch would break builds when compiling with "-Werror=3Dswitch-enum" where the compiler will complain about the lack of handling for the AGGR_CACHE case in the output functions. Suggested-by: Gautham R. Shenoy Signed-off-by: K Prateek Nayak Acked-by: Ian Rogers --- Changelog: o v3->v4: - Some parts of the previous Patch 2 have been put into subsequent smaller patches (while being careful not to introduce any build errors in case someone were to bisect through the series) - Fixed comments. --- tools/lib/perf/include/perf/cpumap.h | 5 ++ tools/perf/builtin-stat.c | 88 +++++++++++++++++++- tools/perf/util/cpumap.c | 119 +++++++++++++++++++++++++++ tools/perf/util/cpumap.h | 28 +++++++ tools/perf/util/stat-display.c | 17 ++++ tools/perf/util/stat.h | 2 + 6 files changed, 257 insertions(+), 2 deletions(-) diff --git a/tools/lib/perf/include/perf/cpumap.h b/tools/lib/perf/include/= perf/cpumap.h index 3f43f770cdac..8724dde79342 100644 --- a/tools/lib/perf/include/perf/cpumap.h +++ b/tools/lib/perf/include/perf/cpumap.h @@ -11,6 +11,11 @@ struct perf_cpu { int cpu; }; =20 +struct perf_cache { + int cache_lvl; + int cache; +}; + struct perf_cpu_map; =20 LIBPERF_API struct perf_cpu_map *perf_cpu_map__dummy_new(void); diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index b9ad32f21e57..7923940edef7 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -138,6 +138,7 @@ struct perf_stat { struct perf_cpu_map *cpus; struct perf_thread_map *threads; enum aggr_mode aggr_mode; + u32 aggr_level; }; =20 static struct perf_stat perf_stat; @@ -145,8 +146,9 @@ static struct perf_stat perf_stat; =20 static volatile sig_atomic_t done =3D 0; =20 -static struct perf_stat_config stat_config =3D { +struct perf_stat_config stat_config =3D { .aggr_mode =3D AGGR_GLOBAL, + .aggr_level =3D MAX_CACHE_LVL + 1, .scale =3D true, .unit_width =3D 4, /* strlen("unit") */ .run_count =3D 1, @@ -1245,6 +1247,7 @@ static struct option stat_options[] =3D { =20 static const char *const aggr_mode__string[] =3D { [AGGR_CORE] =3D "core", + [AGGR_CACHE] =3D "cache", [AGGR_DIE] =3D "die", [AGGR_GLOBAL] =3D "global", [AGGR_NODE] =3D "node", @@ -1266,6 +1269,12 @@ static struct aggr_cpu_id perf_stat__get_die(struct = perf_stat_config *config __m return aggr_cpu_id__die(cpu, /*data=3D*/NULL); } =20 +static struct aggr_cpu_id perf_stat__get_cache_id(struct perf_stat_config = *config __maybe_unused, + struct perf_cpu cpu) +{ + return aggr_cpu_id__cache(cpu, /*data=3D*/NULL); +} + static struct aggr_cpu_id perf_stat__get_core(struct perf_stat_config *con= fig __maybe_unused, struct perf_cpu cpu) { @@ -1318,6 +1327,12 @@ static struct aggr_cpu_id perf_stat__get_die_cached(= struct perf_stat_config *con return perf_stat__get_aggr(config, perf_stat__get_die, cpu); } =20 +static struct aggr_cpu_id perf_stat__get_cache_id_cached(struct perf_stat_= config *config, + struct perf_cpu cpu) +{ + return perf_stat__get_aggr(config, perf_stat__get_cache_id, cpu); +} + static struct aggr_cpu_id perf_stat__get_core_cached(struct perf_stat_conf= ig *config, struct perf_cpu cpu) { @@ -1349,6 +1364,8 @@ static aggr_cpu_id_get_t aggr_mode__get_aggr(enum agg= r_mode aggr_mode) return aggr_cpu_id__socket; case AGGR_DIE: return aggr_cpu_id__die; + case AGGR_CACHE: + return aggr_cpu_id__cache; case AGGR_CORE: return aggr_cpu_id__core; case AGGR_NODE: @@ -1372,6 +1389,8 @@ static aggr_get_id_t aggr_mode__get_id(enum aggr_mode= aggr_mode) return perf_stat__get_socket_cached; case AGGR_DIE: return perf_stat__get_die_cached; + case AGGR_CACHE: + return perf_stat__get_cache_id_cached; case AGGR_CORE: return perf_stat__get_core_cached; case AGGR_NODE: @@ -1484,6 +1503,60 @@ static struct aggr_cpu_id perf_env__get_die_aggr_by_= cpu(struct perf_cpu cpu, voi return id; } =20 +static void perf_env__get_cache_id_for_cpu(struct perf_cpu cpu, struct per= f_env *env, + u32 cache_level, struct aggr_cpu_id *id) +{ + int i; + int caches_cnt =3D env->caches_cnt; + struct cpu_cache_level *caches =3D env->caches; + + id->cache_lvl =3D (cache_level > MAX_CACHE_LVL) ? 0 : cache_level; + id->cache =3D -1; + + if (!caches_cnt) + return; + + for (i =3D caches_cnt - 1; i > -1; --i) { + struct perf_cpu_map *cpu_map; + int map_contains_cpu; + + /* + * If user has not specified a level, find the fist level with + * the cpu in the map. Since building the map is expensive, do + * this only if levels match. + */ + if (cache_level <=3D MAX_CACHE_LVL && caches[i].level !=3D cache_level) + continue; + + cpu_map =3D perf_cpu_map__new(caches[i].map); + map_contains_cpu =3D perf_cpu_map__idx(cpu_map, cpu); + perf_cpu_map__put(cpu_map); + + if (map_contains_cpu !=3D -1) { + id->cache_lvl =3D caches[i].level; + id->cache =3D cpu__get_cache_id_from_map(cpu, caches[i].map); + return; + } + } +} + +static struct aggr_cpu_id perf_env__get_cache_aggr_by_cpu(struct perf_cpu = cpu, + void *data) +{ + struct perf_env *env =3D data; + struct aggr_cpu_id id =3D aggr_cpu_id__empty(); + + if (cpu.cpu !=3D -1) { + u32 cache_level =3D (perf_stat.aggr_level) ?: stat_config.aggr_level; + + id.socket =3D env->cpu[cpu.cpu].socket_id; + id.die =3D env->cpu[cpu.cpu].die_id; + perf_env__get_cache_id_for_cpu(cpu, env, cache_level, &id); + } + + return id; +} + static struct aggr_cpu_id perf_env__get_core_aggr_by_cpu(struct perf_cpu c= pu, void *data) { struct perf_env *env =3D data; @@ -1552,6 +1625,12 @@ static struct aggr_cpu_id perf_stat__get_die_file(st= ruct perf_stat_config *confi return perf_env__get_die_aggr_by_cpu(cpu, &perf_stat.session->header.env); } =20 +static struct aggr_cpu_id perf_stat__get_cache_file(struct perf_stat_confi= g *config __maybe_unused, + struct perf_cpu cpu) +{ + return perf_env__get_cache_aggr_by_cpu(cpu, &perf_stat.session->header.en= v); +} + static struct aggr_cpu_id perf_stat__get_core_file(struct perf_stat_config= *config __maybe_unused, struct perf_cpu cpu) { @@ -1583,6 +1662,8 @@ static aggr_cpu_id_get_t aggr_mode__get_aggr_file(enu= m aggr_mode aggr_mode) return perf_env__get_socket_aggr_by_cpu; case AGGR_DIE: return perf_env__get_die_aggr_by_cpu; + case AGGR_CACHE: + return perf_env__get_cache_aggr_by_cpu; case AGGR_CORE: return perf_env__get_core_aggr_by_cpu; case AGGR_NODE: @@ -1606,6 +1687,8 @@ static aggr_get_id_t aggr_mode__get_id_file(enum aggr= _mode aggr_mode) return perf_stat__get_socket_file; case AGGR_DIE: return perf_stat__get_die_file; + case AGGR_CACHE: + return perf_stat__get_cache_file; case AGGR_CORE: return perf_stat__get_core_file; case AGGR_NODE: @@ -2124,7 +2207,8 @@ static struct perf_stat perf_stat =3D { .stat =3D perf_event__process_stat_event, .stat_round =3D process_stat_round_event, }, - .aggr_mode =3D AGGR_UNSET, + .aggr_mode =3D AGGR_UNSET, + .aggr_level =3D 0, }; =20 static int __cmd_report(int argc, const char **argv) diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 75d9c73e0184..88d387200745 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -3,6 +3,8 @@ #include "cpumap.h" #include "debug.h" #include "event.h" +#include "header.h" +#include "stat.h" #include #include #include @@ -222,6 +224,10 @@ static int aggr_cpu_id__cmp(const void *a_pointer, con= st void *b_pointer) return a->socket - b->socket; else if (a->die !=3D b->die) return a->die - b->die; + else if (a->cache_lvl !=3D b->cache_lvl) + return a->cache_lvl - b->cache_lvl; + else if (a->cache !=3D b->cache) + return a->cache - b->cache; else if (a->core !=3D b->core) return a->core - b->core; else @@ -305,6 +311,113 @@ struct aggr_cpu_id aggr_cpu_id__die(struct perf_cpu c= pu, void *data) return id; } =20 +extern struct perf_stat_config stat_config; + +int cpu__get_cache_id_from_map(struct perf_cpu cpu, char *map) +{ + int id; + struct perf_cpu_map *cpu_map =3D perf_cpu_map__new(map); + + /* + * If the map contains no CPU, consider the current CPU to + * be the first online CPU in the cache domain else use the + * first online CPU of the cache domain as the ID. + */ + if (perf_cpu_map__empty(cpu_map)) + id =3D cpu.cpu; + else + id =3D perf_cpu_map__cpu(cpu_map, 0).cpu; + + /* Free the perf_cpu_map used to find the cache ID */ + perf_cpu_map__put(cpu_map); + + return id; +} + +int cpu__get_cache_details(struct perf_cpu cpu, struct perf_cache *cache) +{ + int ret =3D 0; + struct cpu_cache_level caches[MAX_CACHE_LVL]; + u32 cache_level =3D stat_config.aggr_level; + u32 i =3D 0, caches_cnt =3D 0; + + cache->cache_lvl =3D (cache_level > MAX_CACHE_LVL) ? 0 : cache_level; + cache->cache =3D -1; + + ret =3D build_caches_for_cpu(cpu.cpu, caches, &caches_cnt); + if (ret) { + /* + * If caches_cnt is not 0, cpu_cache_level data + * was allocated when building the topology. + * Free the allocated data before returning. + */ + if (caches_cnt) + goto free_caches; + + return ret; + } + + if (!caches_cnt) + return -1; + + /* + * Save the data for the highest level if no + * level was specified by the user. + */ + if (cache_level > MAX_CACHE_LVL) { + int max_level_index =3D 0; + + for (i =3D 1; i < caches_cnt; ++i) { + if (caches[i].level > caches[max_level_index].level) + max_level_index =3D i; + } + + cache->cache_lvl =3D caches[max_level_index].level; + cache->cache =3D cpu__get_cache_id_from_map(cpu, caches[max_level_index]= .map); + + /* Reset i to 0 to free entire caches[] */ + i =3D 0; + goto free_caches; + } + + for (i =3D 0; i < caches_cnt; ++i) { + if (caches[i].level =3D=3D cache_level) { + cache->cache_lvl =3D cache_level; + cache->cache =3D cpu__get_cache_id_from_map(cpu, caches[i].map); + } + + cpu_cache_level__free(&caches[i]); + } + +free_caches: + /* + * Free all the allocated cpu_cache_level data. + */ + while (i < caches_cnt) + cpu_cache_level__free(&caches[i++]); + + return ret; +} + +struct aggr_cpu_id aggr_cpu_id__cache(struct perf_cpu cpu, void *data) +{ + int ret; + struct aggr_cpu_id id; + struct perf_cache cache; + + id =3D aggr_cpu_id__die(cpu, data); + if (aggr_cpu_id__is_empty(&id)) + return id; + + ret =3D cpu__get_cache_details(cpu, &cache); + if (ret) + return id; + + id.cache_lvl =3D cache.cache_lvl; + id.cache =3D cache.cache; + return id; +} + int cpu__get_core_id(struct perf_cpu cpu) { int value, ret =3D cpu__get_topology_int(cpu.cpu, "core_id", &value); @@ -679,6 +792,8 @@ bool aggr_cpu_id__equal(const struct aggr_cpu_id *a, co= nst struct aggr_cpu_id *b a->node =3D=3D b->node && a->socket =3D=3D b->socket && a->die =3D=3D b->die && + a->cache_lvl =3D=3D b->cache_lvl && + a->cache =3D=3D b->cache && a->core =3D=3D b->core && a->cpu.cpu =3D=3D b->cpu.cpu; } @@ -689,6 +804,8 @@ bool aggr_cpu_id__is_empty(const struct aggr_cpu_id *a) a->node =3D=3D -1 && a->socket =3D=3D -1 && a->die =3D=3D -1 && + a->cache_lvl =3D=3D -1 && + a->cache =3D=3D -1 && a->core =3D=3D -1 && a->cpu.cpu =3D=3D -1; } @@ -700,6 +817,8 @@ struct aggr_cpu_id aggr_cpu_id__empty(void) .node =3D -1, .socket =3D -1, .die =3D -1, + .cache_lvl =3D -1, + .cache =3D -1, .core =3D -1, .cpu =3D (struct perf_cpu){ .cpu =3D -1 }, }; diff --git a/tools/perf/util/cpumap.h b/tools/perf/util/cpumap.h index e3426541e0aa..1212b4ab1938 100644 --- a/tools/perf/util/cpumap.h +++ b/tools/perf/util/cpumap.h @@ -20,6 +20,13 @@ struct aggr_cpu_id { int socket; /** The die id as read from /sys/devices/system/cpu/cpuX/topology/die_id.= */ int die; + /** The cache level as read from /sys/devices/system/cpu/cpuX/cache/index= Y/level */ + int cache_lvl; + /** + * The cache instance ID, which is the first CPU in the + * /sys/devices/system/cpu/cpuX/cache/indexY/shared_cpu_list + */ + int cache; /** The core id as read from /sys/devices/system/cpu/cpuX/topology/core_i= d. */ int core; /** CPU aggregation, note there is one CPU for each SMT thread. */ @@ -79,6 +86,20 @@ int cpu__get_socket_id(struct perf_cpu cpu); * /sys/devices/system/cpu/cpuX/topology/die_id for the given CPU. */ int cpu__get_die_id(struct perf_cpu cpu); +/** + * Calculate the cache instance ID from the map in + * /sys/devices/system/cpu/cpuX/cache/indexY/shared_cpu_list + * Cache instance ID is the first CPU reported in the shared_cpu_list file. + */ +int cpu__get_cache_id_from_map(struct perf_cpu cpu, char *map); +/** + * cpu__get_cache_id - Returns 0 if successful in populating the + * cache level and cache id. Cache level is read from + * /sys/devices/system/cpu/cpuX/cache/indexY/level where as cache instance= ID + * is the first CPU reported by + * /sys/devices/system/cpu/cpuX/cache/indexY/shared_cpu_list + */ +int cpu__get_cache_details(struct perf_cpu cpu, struct perf_cache *cache); /** * cpu__get_core_id - Returns the core id as read from * /sys/devices/system/cpu/cpuX/topology/core_id for the given CPU. @@ -119,6 +140,13 @@ struct aggr_cpu_id aggr_cpu_id__socket(struct perf_cpu= cpu, void *data); * aggr_cpu_id_get_t. */ struct aggr_cpu_id aggr_cpu_id__die(struct perf_cpu cpu, void *data); +/** + * aggr_cpu_id__cache - Create an aggr_cpu_id with cache instache ID, cache + * level, die and socket populated with the cache instache ID, cache level, + * die and socket for cpu. The function signature is compatible with + * aggr_cpu_id_get_t. + */ +struct aggr_cpu_id aggr_cpu_id__cache(struct perf_cpu cpu, void *data); /** * aggr_cpu_id__core - Create an aggr_cpu_id with the core, die and socket * populated with the core, die and socket for cpu. The function signature= is diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index bf5a6c14dfcd..319f456f0673 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -36,6 +36,7 @@ =20 static int aggr_header_lens[] =3D { [AGGR_CORE] =3D 18, + [AGGR_CACHE] =3D 22, [AGGR_DIE] =3D 12, [AGGR_SOCKET] =3D 6, [AGGR_NODE] =3D 6, @@ -46,6 +47,7 @@ static int aggr_header_lens[] =3D { =20 static const char *aggr_header_csv[] =3D { [AGGR_CORE] =3D "core,cpus,", + [AGGR_CACHE] =3D "cache,cpus,", [AGGR_DIE] =3D "die,cpus,", [AGGR_SOCKET] =3D "socket,cpus,", [AGGR_NONE] =3D "cpu,", @@ -56,6 +58,7 @@ static const char *aggr_header_csv[] =3D { =20 static const char *aggr_header_std[] =3D { [AGGR_CORE] =3D "core", + [AGGR_CACHE] =3D "cache", [AGGR_DIE] =3D "die", [AGGR_SOCKET] =3D "socket", [AGGR_NONE] =3D "cpu", @@ -193,6 +196,10 @@ static void print_aggr_id_std(struct perf_stat_config = *config, case AGGR_CORE: snprintf(buf, sizeof(buf), "S%d-D%d-C%d", id.socket, id.die, id.core); break; + case AGGR_CACHE: + snprintf(buf, sizeof(buf), "S%d-D%d-L%d-ID%d", + id.socket, id.die, id.cache_lvl, id.cache); + break; case AGGR_DIE: snprintf(buf, sizeof(buf), "S%d-D%d", id.socket, id.die); break; @@ -239,6 +246,10 @@ static void print_aggr_id_csv(struct perf_stat_config = *config, fprintf(output, "S%d-D%d-C%d%s%d%s", id.socket, id.die, id.core, sep, aggr_nr, sep); break; + case AGGR_CACHE: + fprintf(config->output, "S%d-D%d-L%d-ID%d%s%d%s", + id.socket, id.die, id.cache_lvl, id.cache, sep, aggr_nr, sep); + break; case AGGR_DIE: fprintf(output, "S%d-D%d%s%d%s", id.socket, id.die, sep, aggr_nr, sep); @@ -284,6 +295,10 @@ static void print_aggr_id_json(struct perf_stat_config= *config, fprintf(output, "\"core\" : \"S%d-D%d-C%d\", \"aggregate-number\" : %d, = ", id.socket, id.die, id.core, aggr_nr); break; + case AGGR_CACHE: + fprintf(output, "\"cache\" : \"S%d-D%d-L%d-ID%d\", \"aggregate-number\" = : %d, ", + id.socket, id.die, id.cache_lvl, id.cache, aggr_nr); + break; case AGGR_DIE: fprintf(output, "\"die\" : \"S%d-D%d\", \"aggregate-number\" : %d, ", id.socket, id.die, aggr_nr); @@ -1125,6 +1140,7 @@ static void print_header_interval_std(struct perf_sta= t_config *config, case AGGR_NODE: case AGGR_SOCKET: case AGGR_DIE: + case AGGR_CACHE: case AGGR_CORE: fprintf(output, "#%*s %-*s cpus", INTERVAL_LEN - 1, "time", @@ -1425,6 +1441,7 @@ void evlist__print_counters(struct evlist *evlist, st= ruct perf_stat_config *conf =20 switch (config->aggr_mode) { case AGGR_CORE: + case AGGR_CACHE: case AGGR_DIE: case AGGR_SOCKET: case AGGR_NODE: diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index e35e188237c8..7abff7cbb5a1 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -48,6 +48,7 @@ enum aggr_mode { AGGR_GLOBAL, AGGR_SOCKET, AGGR_DIE, + AGGR_CACHE, AGGR_CORE, AGGR_THREAD, AGGR_UNSET, @@ -64,6 +65,7 @@ typedef struct aggr_cpu_id (*aggr_get_id_t)(struct perf_s= tat_config *config, str =20 struct perf_stat_config { enum aggr_mode aggr_mode; + u32 aggr_level; bool scale; bool no_inherit; bool identifier; --=20 2.34.1 From nobody Sun Feb 8 08:20:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF45C77B75 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT114.mail.protection.outlook.com (10.13.174.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.18 via Frontend Transport; Wed, 17 May 2023 17:24:59 +0000 Received: from BLR5CG134614W.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 17 May 2023 12:24:49 -0500 From: K Prateek Nayak To: , , , , , , , , CC: , , , , , , Subject: [PATCH v4 3/5] perf stat: Save cache level information when running perf stat record Date: Wed, 17 May 2023 22:57:43 +0530 Message-ID: <20230517172745.5833-4-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517172745.5833-1-kprateek.nayak@amd.com> References: <20230517172745.5833-1-kprateek.nayak@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT114:EE_|SA3PR12MB7974:EE_ X-MS-Office365-Filtering-Correlation-Id: 662edcb3-bc31-4eb9-4066-08db56fba45e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 17:24:59.6071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 662edcb3-bc31-4eb9-4066-08db56fba45e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7974 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When aggregating based on cache-topology, in addition to the aggregation mode, knowing the cache level at which data is aggregated is necessary to ensure consistency when running perf stat record and later perf stat report. Save the cache level for aggregation as a part of the env data that can be later retrieved when running perf stat report. Suggested-by: Gautham R. Shenoy Signed-off-by: K Prateek Nayak Acked-by: Ian Rogers --- Changelog: o v3->v4: - Previously part of Patch 2. --- tools/lib/perf/include/perf/event.h | 3 ++- tools/perf/util/event.c | 7 ++++--- tools/perf/util/synthetic-events.c | 1 + 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/tools/lib/perf/include/perf/event.h b/tools/lib/perf/include/p= erf/event.h index 51b9338f4c11..ba2dcf64f4e6 100644 --- a/tools/lib/perf/include/perf/event.h +++ b/tools/lib/perf/include/perf/event.h @@ -380,7 +380,8 @@ enum { PERF_STAT_CONFIG_TERM__AGGR_MODE =3D 0, PERF_STAT_CONFIG_TERM__INTERVAL =3D 1, PERF_STAT_CONFIG_TERM__SCALE =3D 2, - PERF_STAT_CONFIG_TERM__MAX =3D 3, + PERF_STAT_CONFIG_TERM__AGGR_LEVEL =3D 3, + PERF_STAT_CONFIG_TERM__MAX =3D 4, }; =20 struct perf_record_stat_config_entry { diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index 8ae742e32e3c..e8b0666d913c 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -135,9 +135,10 @@ void perf_event__read_stat_config(struct perf_stat_con= fig *config, config->__val =3D event->data[i].val; \ break; =20 - CASE(AGGR_MODE, aggr_mode) - CASE(SCALE, scale) - CASE(INTERVAL, interval) + CASE(AGGR_MODE, aggr_mode) + CASE(SCALE, scale) + CASE(INTERVAL, interval) + CASE(AGGR_LEVEL, aggr_level) #undef CASE default: pr_warning("unknown stat config term %" PRI_lu64 "\n", diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic= -events.c index b2e4afa5efa1..45714a2785fd 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -1375,6 +1375,7 @@ int perf_event__synthesize_stat_config(struct perf_to= ol *tool, ADD(AGGR_MODE, config->aggr_mode) ADD(INTERVAL, config->interval) ADD(SCALE, config->scale) + ADD(AGGR_LEVEL, config->aggr_level) =20 WARN_ONCE(i !=3D PERF_STAT_CONFIG_TERM__MAX, "stat config terms unbalanced\n"); --=20 2.25.1 From nobody Sun Feb 8 08:20:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7199BC77B7F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 17:25:47.4024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7229a8ed-6cf8-4827-3e5c-08db56fbc0db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5869 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds support for "--per-cache" option for aggregation at a particular cache level and documents the same. Following is the output of perf stat with aggregation at L3 for the event "ls_dmnd_fills_from_sys.ext_cache_remote" on a dual socket 3rd Generation EPYC Processor (2 x 64C/128T - 16 LLCs) when running hackbench pinned to 4 LLCs: $ sudo perf stat --per-cache=3DL3 -a -e ls_dmnd_fills_from_sys.ext_cache_= remote -- \ taskset -c 0-15,64-79,128-143,192-207 \ perf bench sched messaging -p -t -l 100000 -g 8 ... Performance counter stats for 'system wide': =20 S0-D0-L3-ID0 16 9,500,803 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID8 16 6,338,099 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID16 16 355,005 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID24 16 22,067 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID32 16 16,321 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID40 16 11,619 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID48 16 4,238 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID56 16 31,158 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID64 16 28,242,452 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID72 16 22,906,973 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID80 16 72,898 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID88 16 56,907 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID96 16 20,456 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID104 16 40,913 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID112 16 78,113 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID120 16 37,897 ls_dmnd_fills_from_sy= s.ext_cache_remote Also support perf stat record and perf stat report with the ability to specify a different cache level to aggregate data at when running perf stat report. $ sudo perf stat record --per-cache=3DL2 -a -e ls_dmnd_fills_from_sys.ext= _cache_remote -- \ taskset -c 0-15,64-79,128-143,192-207 \ perf bench sched messaging -p -t -l 100000 -g 8 ... Performance counter stats for 'system wide': =20 S0-D0-L2-ID0 2 1,442,061 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID1 2 1,548,994 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID2 2 1,553,557 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID3 2 1,420,122 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID4 2 1,465,461 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID5 2 1,455,153 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID6 2 1,595,237 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID7 2 1,499,321 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L2-ID8 2 1,919,025 ls_dmnd_fills_from_sy= s.ext_cache_remote ... S1-D1-L2-ID127 2 21,295 ls_dmnd_fills_from_sy= s.ext_cache_remote $ sudo perf stat report --per-cache=3DL3 Performance counter stats for 'perf stat record --per-cache=3DL2 -a -e l= s_dmnd_fills_from_sys.ext_cache_remote --\ taskset -c 0-15,64-79,128-143,192-207 \ perf bench sched messaging -p -t -l 10000= 0 -g 8': =20 S0-D0-L3-ID0 16 11,979,906 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID8 16 14,257,202 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID16 16 377,484 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID24 16 27,224 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID32 16 26,816 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID40 16 14,461 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID48 16 10,499 ls_dmnd_fills_from_sy= s.ext_cache_remote S0-D0-L3-ID56 16 53,817 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID64 16 27,361,987 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID72 16 37,299,024 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID80 16 84,125 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID88 16 64,561 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID96 16 13,403 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID104 16 20,138 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID112 16 93,220 ls_dmnd_fills_from_sy= s.ext_cache_remote S1-D1-L3-ID120 16 35,465 ls_dmnd_fills_from_sy= s.ext_cache_remote On the above system, the domain covered by S0-D0-L3-ID0 contains S0-D0-L2-ID0 to S0-D0-L2-ID7, the corresponding count for L3-ID0 is equal to the sum of counts for L2-ID0 to L2-ID7. Add documentation for the newly introduced "--per-cache" option. Suggested-by: Gautham R. Shenoy Signed-off-by: K Prateek Nayak Acked-by: Ian Rogers --- Changelog: o v3->v4: - Previously part of Patch 2. - Fixed errors in documentation. --- tools/perf/Documentation/perf-stat.txt | 16 ++++++++ tools/perf/builtin-stat.c | 56 ++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentat= ion/perf-stat.txt index 29bdcfa93f04..785f0e2bcfac 100644 --- a/tools/perf/Documentation/perf-stat.txt +++ b/tools/perf/Documentation/perf-stat.txt @@ -308,6 +308,14 @@ use --per-die in addition to -a. (system-wide). The o= utput includes the die number and the number of online processors on that die. This is useful to gauge the amount of aggregation. =20 +--per-cache:: +Aggregate counts per cache instance for system-wide mode measurements. By +default, the aggregation happens for the cache level at the highest index +in the system. To specify a particular level, mention the cache level +alongside the option in the format [Ll][1-9][0-9]*. For example: +Using option "--per-cache=3Dl3" or "--per-cache=3DL3" will aggregate the +information at the boundary of the level 3 cache in the system. + --per-core:: Aggregate counts per physical processor for system-wide mode measurements.= This is a useful mode to detect imbalance between physical cores. To enable th= is mode, @@ -379,6 +387,14 @@ Aggregate counts per processor socket for system-wide = mode measurements. --per-die:: Aggregate counts per processor die for system-wide mode measurements. =20 +--per-cache:: +Aggregate counts per cache instance for system-wide mode measurements. By +default, the aggregation happens for the cache level at the highest index +in the system. To specify a particular level, mention the cache level +alongside the option in the format [Ll][1-9][0-9]*. For example: Using +option "--per-cache=3Dl3" or "--per-cache=3DL3" will aggregate the +information at the boundary of the level 3 cache in the system. + --per-core:: Aggregate counts per physical processor for system-wide mode measurements. =20 diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index b072c4160fe1..7aafea5c7e6c 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1100,6 +1100,55 @@ static int parse_hybrid_type(const struct option *op= t, return 0; } =20 +static int parse_cache_level(const struct option *opt, + const char *str, + int unset __maybe_unused) +{ + int level; + u32 *aggr_mode =3D (u32 *)opt->value; + u32 *aggr_level =3D (u32 *)opt->data; + + /* + * If no string is specified, aggregate based on the topology of + * Last Level Cache (LLC). Since the LLC level can change from + * architecture to architecture, set level greater than + * MAX_CACHE_LVL which will be interpreted as LLC. + */ + if (str =3D=3D NULL) { + level =3D MAX_CACHE_LVL + 1; + goto out; + } + + /* + * The format to specify cache level is LX or lX where X is the + * cache level. + */ + if (strlen(str) !=3D 2 || (str[0] !=3D 'l' && str[0] !=3D 'L')) { + pr_err("Cache level must be of form L[1-%d], or l[1-%d]\n", + MAX_CACHE_LVL, + MAX_CACHE_LVL); + return -EINVAL; + } + + level =3D atoi(&str[1]); + if (level < 1) { + pr_err("Cache level must be of form L[1-%d], or l[1-%d]\n", + MAX_CACHE_LVL, + MAX_CACHE_LVL); + return -EINVAL; + } + + if (level > MAX_CACHE_LVL) { + pr_err("perf only supports max cache level of %d.\n" + "Consider increasing MAX_CACHE_LVL\n", MAX_CACHE_LVL); + return -EINVAL; + } +out: + *aggr_mode =3D AGGR_CACHE; + *aggr_level =3D level; + return 0; +} + static struct option stat_options[] =3D { OPT_BOOLEAN('T', "transaction", &transaction_run, "hardware transaction statistics"), @@ -1177,6 +1226,9 @@ static struct option stat_options[] =3D { "aggregate counts per processor socket", AGGR_SOCKET), OPT_SET_UINT(0, "per-die", &stat_config.aggr_mode, "aggregate counts per processor die", AGGR_DIE), + OPT_CALLBACK_OPTARG(0, "per-cache", &stat_config.aggr_mode, &stat_config.= aggr_level, + "cache level", "aggregate count at this cache level (Default: LLC)", + parse_cache_level), OPT_SET_UINT(0, "per-core", &stat_config.aggr_mode, "aggregate counts per physical processor core", AGGR_CORE), OPT_SET_UINT(0, "per-thread", &stat_config.aggr_mode, @@ -2200,6 +2252,10 @@ static int __cmd_report(int argc, const char **argv) "aggregate counts per processor socket", AGGR_SOCKET), OPT_SET_UINT(0, "per-die", &perf_stat.aggr_mode, "aggregate counts per processor die", AGGR_DIE), + OPT_CALLBACK_OPTARG(0, "per-cache", &perf_stat.aggr_mode, &perf_stat.aggr= _level, + "cache level", + "aggregate count at this cache level (Default: LLC)", + parse_cache_level), OPT_SET_UINT(0, "per-core", &perf_stat.aggr_mode, "aggregate counts per physical processor core", AGGR_CORE), OPT_SET_UINT(0, "per-node", &perf_stat.aggr_mode, --=20 2.25.1 From nobody Sun Feb 8 08:20:47 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F852C77B75 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2023 17:26:55.3602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d02e8411-b380-46e9-2a09-08db56fbe95f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT087.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8768 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add tests for the new "--per-cache" option in perf stat for CSV and JSON generation as well as for the JSON linting. Suggested-by: Gautham R. Shenoy Signed-off-by: K Prateek Nayak Acked-by: Ian Rogers --- Changelog: o v3->v4: - Previously part of Patch 2. --- .../perf/tests/shell/lib/perf_json_output_lint.py | 4 +++- tools/perf/tests/shell/stat+csv_output.sh | 14 ++++++++++++++ tools/perf/tests/shell/stat+json_output.sh | 13 +++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/lib/perf_json_output_lint.py b/tools/pe= rf/tests/shell/lib/perf_json_output_lint.py index 61f3059ca54b..4acaaed5560d 100644 --- a/tools/perf/tests/shell/lib/perf_json_output_lint.py +++ b/tools/perf/tests/shell/lib/perf_json_output_lint.py @@ -14,6 +14,7 @@ ap.add_argument('--system-wide', action=3D'store_true') ap.add_argument('--event', action=3D'store_true') ap.add_argument('--per-core', action=3D'store_true') ap.add_argument('--per-thread', action=3D'store_true') +ap.add_argument('--per-cache', action=3D'store_true') ap.add_argument('--per-die', action=3D'store_true') ap.add_argument('--per-node', action=3D'store_true') ap.add_argument('--per-socket', action=3D'store_true') @@ -47,6 +48,7 @@ def check_json_output(expected_items): 'counter-value': lambda x: is_counter_value(x), 'cgroup': lambda x: True, 'cpu': lambda x: isint(x), + 'cache': lambda x: True, 'die': lambda x: True, 'event': lambda x: True, 'event-runtime': lambda x: isfloat(x), @@ -83,7 +85,7 @@ try: expected_items =3D 7 elif args.interval or args.per_thread or args.system_wide_no_aggr: expected_items =3D 8 - elif args.per_core or args.per_socket or args.per_node or args.per_die: + elif args.per_core or args.per_socket or args.per_node or args.per_die o= r args.per_cache_instance: expected_items =3D 9 else: # If no option is specified, don't check the number of items. diff --git a/tools/perf/tests/shell/stat+csv_output.sh b/tools/perf/tests/s= hell/stat+csv_output.sh index fb78b6251a4e..a1969f236a0a 100755 --- a/tools/perf/tests/shell/stat+csv_output.sh +++ b/tools/perf/tests/shell/stat+csv_output.sh @@ -40,6 +40,7 @@ function commachecker() ;; "--per-socket") exp=3D8 ;; "--per-node") exp=3D8 ;; "--per-die") exp=3D8 + ;; "--per-cache") exp=3D8 esac =20 while read line @@ -145,6 +146,18 @@ check_per_thread() echo "[Success]" } =20 +check_per_cache_instance() +{ + echo -n "Checking CSV output: per cache instance " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoid and not root" + return + fi + perf stat -x$csv_sep --per-cache -a true 2>&1 | commachecker --per-cache + echo "[Success]" +} + check_per_die() { echo -n "Checking CSV output: per die " @@ -222,6 +235,7 @@ if [ $skip_test -ne 1 ] then check_system_wide_no_aggr check_per_core + check_per_cache_instance check_per_die check_per_socket else diff --git a/tools/perf/tests/shell/stat+json_output.sh b/tools/perf/tests/= shell/stat+json_output.sh index f3e4967cc72e..c282afa6217c 100755 --- a/tools/perf/tests/shell/stat+json_output.sh +++ b/tools/perf/tests/shell/stat+json_output.sh @@ -120,6 +120,18 @@ check_per_thread() echo "[Success]" } =20 +check_per_cache_instance() +{ + echo -n "Checking json output: per cache_instance " + if ParanoidAndNotRoot 0 + then + echo "[Skip] paranoia and not root" + return + fi + perf stat -j --per-cache -a true 2>&1 | $PYTHON $pythonchecker --per-cache + echo "[Success]" +} + check_per_die() { echo -n "Checking json output: per die " @@ -197,6 +209,7 @@ if [ $skip_test -ne 1 ] then check_system_wide_no_aggr check_per_core + check_per_cache_instance check_per_die check_per_socket else --=20 2.25.1