From nobody Fri Sep 19 03:52:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F17C7EE23 for ; Wed, 17 May 2023 11:46:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231292AbjEQLqw (ORCPT ); Wed, 17 May 2023 07:46:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229921AbjEQLqt (ORCPT ); Wed, 17 May 2023 07:46:49 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6FBF30C1 for ; Wed, 17 May 2023 04:46:48 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-24e5d5782edso786830a91.0 for ; Wed, 17 May 2023 04:46:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684324008; x=1686916008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RwNQCA9ozgCFKqQivomJuANGu4rucg7HtzAq9d/gM0o=; b=z3+Ugw4k7EP8q1WKGKC5FCv+BJdDqyFA7a+iyE7kIv60S8X4NnTL1Wo4zmHQ/dGUwG TBWUWU5jKvFKU5DmR+vGOBtGJe9qBeGnJ2g6Ce94WiTplmmHuj/ifJLa5xmJ5u7ivgbJ 3nFXw2G8RwvmuSTyPx3PlwEXpkkoCA4Q0e+wI+yx9EZeWLweViqZ68PPtDH8fFchEuai V2uDi3SsrX5bTmaCj+eX5hLHlzxSJ5E9Xuvy1P0i0jkvTogyi7DosRcGQFHAg4+MSAiO H/0Nm6oqYo5HKLExVW5ekrChA7JT+AwuqwTXeEB5r6+GzfFyMC0P9Jdu4kB58FoYASKD LJjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684324008; x=1686916008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RwNQCA9ozgCFKqQivomJuANGu4rucg7HtzAq9d/gM0o=; b=Ykl/uikIu5eQ90B5WFpGEIUdvH0AyL+WfEp2tFak4Ww9DS9VnJ3SftvyHlTAXY4Xaq Bh6F7Bqo0IwWGFICgl3L3DuGXs32U9KwK8wUVwaZAZzcE6Rt/H8clgHuT2mnPijMNJIr s5lwiFzZdSBIkwboxIUC5XaQtu+rkpMRRKzhP5eWa8qL1bi+W9AQsQ1MOSs601ssoCuA Rko5xbWbTpPoN//3PhEu3pd+tgJ4AHeCoElS5A0JV39pcSe0hg8O+YSRQ1mpnfkONhwV PZy4DLwPlBwPh2k+++fvAhphBnMiIkC95HTPE3GDAEX1g8KEeeCj9ujI4K0vwnTY3ehQ lNlw== X-Gm-Message-State: AC+VfDz7jF2yViLf8fmJge1RCdvzmQpL1gxefuY2PnPDiNhJMO1pLfbb +QWM39g/xJSY/OwBp5Wa3gAt X-Google-Smtp-Source: ACHHUZ5EYEW/ICrZAuG6MA7oFcdnFAe59sZovawyPXM++2NcP0NFH11weDO7HnaNwSy6kGXljjWi6g== X-Received: by 2002:a17:90b:33c7:b0:250:69c7:a95e with SMTP id lk7-20020a17090b33c700b0025069c7a95emr33058167pjb.48.1684324008246; Wed, 17 May 2023 04:46:48 -0700 (PDT) Received: from localhost.localdomain ([117.207.26.28]) by smtp.gmail.com with ESMTPSA id s12-20020a17090aba0c00b0025289bc1ce4sm1366971pjr.17.2023.05.17.04.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 04:46:47 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v8 1/2] EDAC/qcom: Remove superfluous return variable assignment in qcom_llcc_core_setup() Date: Wed, 17 May 2023 17:16:34 +0530 Message-Id: <20230517114635.76358-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517114635.76358-1-manivannan.sadhasivam@linaro.org> References: <20230517114635.76358-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" "ret" variable will be assigned on both success and failure cases. So there is no need to initialize it during start of qcom_llcc_core_setup(). Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 265e0fb39bc7..6140001f21c4 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -170,7 +170,7 @@ static int qcom_llcc_core_setup(struct regmap *llcc_bca= st_regmap) static int qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv) { - int ret =3D 0; + int ret; =20 switch (err_type) { case LLCC_DRAM_CE: --=20 2.25.1 From nobody Fri Sep 19 03:52:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56723C7EE23 for ; Wed, 17 May 2023 11:47:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229921AbjEQLq6 (ORCPT ); Wed, 17 May 2023 07:46:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbjEQLqz (ORCPT ); Wed, 17 May 2023 07:46:55 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37EF74688 for ; Wed, 17 May 2023 04:46:53 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1ae4e49727eso8028475ad.1 for ; Wed, 17 May 2023 04:46:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684324012; x=1686916012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w4TT/BMksx54mCC9/VfF7c6kITEjgm9D+5k2o9fOKfE=; b=hpwkBxsb7uBVHAelyayYZkj2bDII2OVUiLqqzX8mgKwO69le5VpB5+efstjXefGvTo wa8AneTX10/lxjIloJoI9+78R0fp5P1xR7E558k32/xSerIgx9KFCby/Xvot72WHRyqS lkPjiQm/4QRX4adMmOWg/C5/wuAeHsyheqL0biepDqyxnNs4vYwyeDHy90VOv3kC+s9A 6W+qksuBtCSrQZgVwX/fp9KgVUmw1Cf1vMwmylg9LL6Mph429ABkAznz7V+0sPHCl496 kEL1YUYlDtrhAJZT2Y8UoY0BUY4BxmfQw/doGKaIYjRCun95ReWL8AcVF1ryULt4F0xH xsDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684324012; x=1686916012; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w4TT/BMksx54mCC9/VfF7c6kITEjgm9D+5k2o9fOKfE=; b=TsgcQQrY3f2+REM7+ZmcdjMqEDdKZXLS5uG9Uqa4SVL649jKbfw0cUIGt5iy/xANlE RbQAW6vS0aOLjyoVgax8QXmRzRO9xZ1ep+WAv6CrWOB2D/g0Udaetoo1DvL6MBk2dmBC jxU543+j2v4ZtHfJdbcR7M8osToqK/2D/S15aXXwTTYXTglfzdXXzY4ZjNKm7QM4qXnY iTaweZt35dsbYsdHd3DrNbPkzyEgldhDYKJsvTtEEDR9++3uQUfY320MijXEwj4W6r2O gvk7rNiG2bf8GptFCPRMbxrTfAr2vyiwfpXU5lew1rucE6XB6y5jxn2PlOHQZy1DiIjE QY6A== X-Gm-Message-State: AC+VfDzZEm27LmEqFKNI6gM+TYGWxnjIqkhMIqsILKHoQ9AGx8BDLqTd JrahLoCC0/LQgO66XWIPCaR7 X-Google-Smtp-Source: ACHHUZ4oqr91CLRgt9TjP5dL4wajLtQsJCf+57ZAsLWzhI3zUkUMu21KeMTJBcYLnPJbEbC6yR0D2Q== X-Received: by 2002:a17:902:b70f:b0:1a1:b3bb:cd5b with SMTP id d15-20020a170902b70f00b001a1b3bbcd5bmr40785658pls.62.1684324012593; Wed, 17 May 2023 04:46:52 -0700 (PDT) Received: from localhost.localdomain ([117.207.26.28]) by smtp.gmail.com with ESMTPSA id s12-20020a17090aba0c00b0025289bc1ce4sm1366971pjr.17.2023.05.17.04.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 May 2023 04:46:52 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, bp@alien8.de, mchehab@kernel.org Cc: james.morse@arm.com, rric@kernel.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v8 2/2] EDAC/qcom: Get rid of hardcoded register offsets Date: Wed, 17 May 2023 17:16:35 +0530 Message-Id: <20230517114635.76358-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230517114635.76358-1-manivannan.sadhasivam@linaro.org> References: <20230517114635.76358-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The LLCC EDAC register offsets varies between each SoC. Hardcoding the register offsets won't work and will often result in crash due to accessing the wrong locations. Hence, get the register offsets from the LLCC driver matching the individual SoCs. Cc: # 6.0: 5365cea199c7 ("soc: qcom: llcc: Rename = reg_offset structs to reflect LLCC version") Cc: # 6.0: c13d7d261e36 ("soc: qcom: llcc: Pass LL= CC version based register offsets to EDAC driver") Cc: # 6.0 Fixes: a6e9d7ef252c ("soc: qcom: llcc: Add configuration data for SM8450 So= C") Acked-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 116 ++++++++++++++--------------- include/linux/soc/qcom/llcc-qcom.h | 6 -- 2 files changed, 58 insertions(+), 64 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 6140001f21c4..b2db545c6810 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -21,30 +21,9 @@ #define TRP_SYN_REG_CNT 6 #define DRP_SYN_REG_CNT 8 =20 -#define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 =20 -/* Single & double bit syndrome register offsets */ -#define TRP_ECC_SB_ERR_SYN0 0x0002304c -#define TRP_ECC_DB_ERR_SYN0 0x00020370 -#define DRP_ECC_SB_ERR_SYN0 0x0004204c -#define DRP_ECC_DB_ERR_SYN0 0x00042070 - -/* Error register offsets */ -#define TRP_ECC_ERROR_STATUS1 0x00020348 -#define TRP_ECC_ERROR_STATUS0 0x00020344 -#define DRP_ECC_ERROR_STATUS1 0x00042048 -#define DRP_ECC_ERROR_STATUS0 0x00042044 - -/* TRP, DRP interrupt register offsets */ -#define DRP_INTERRUPT_STATUS 0x00041000 -#define TRP_INTERRUPT_0_STATUS 0x00020480 -#define DRP_INTERRUPT_CLEAR 0x00041008 -#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 -#define TRP_INTERRUPT_0_CLEAR 0x00020484 -#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 - /* Mask and shift macros */ #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) @@ -60,15 +39,6 @@ #define DRP_TRP_INT_CLEAR GENMASK(1, 0) #define DRP_TRP_CNT_CLEAR GENMASK(1, 0) =20 -/* Config registers offsets*/ -#define DRP_ECC_ERROR_CFG 0x00040000 - -/* Tag RAM, Data RAM interrupt register offsets */ -#define CMN_INTERRUPT_0_ENABLE 0x0003001c -#define CMN_INTERRUPT_2_ENABLE 0x0003003c -#define TRP_INTERRUPT_0_ENABLE 0x00020488 -#define DRP_INTERRUPT_ENABLE 0x0004100c - #define SB_ERROR_THRESHOLD 0x1 #define SB_ERROR_THRESHOLD_SHIFT 24 #define SB_DB_TRP_INTERRUPT_ENABLE 0x3 @@ -88,9 +58,6 @@ enum { static const struct llcc_edac_reg_data edac_reg_data[] =3D { [LLCC_DRAM_CE] =3D { .name =3D "DRAM Single-bit", - .synd_reg =3D DRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -98,9 +65,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_DRAM_UE] =3D { .name =3D "DRAM Double-bit", - .synd_reg =3D DRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D DRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D DRP_ECC_ERROR_STATUS0, .reg_cnt =3D DRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -108,9 +72,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_CE] =3D { .name =3D "TRAM Single-bit", - .synd_reg =3D TRP_ECC_SB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_SB_ERR_COUNT_MASK, .ways_mask =3D ECC_SB_ERR_WAYS_MASK, @@ -118,9 +79,6 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, [LLCC_TRAM_UE] =3D { .name =3D "TRAM Double-bit", - .synd_reg =3D TRP_ECC_DB_ERR_SYN0, - .count_status_reg =3D TRP_ECC_ERROR_STATUS1, - .ways_status_reg =3D TRP_ECC_ERROR_STATUS0, .reg_cnt =3D TRP_SYN_REG_CNT, .count_mask =3D ECC_DB_ERR_COUNT_MASK, .ways_mask =3D ECC_DB_ERR_WAYS_MASK, @@ -128,7 +86,7 @@ static const struct llcc_edac_reg_data edac_reg_data[] = =3D { }, }; =20 -static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap) +static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *= llcc_bcast_regmap) { u32 sb_err_threshold; int ret; @@ -137,31 +95,31 @@ static int qcom_llcc_core_setup(struct regmap *llcc_bc= ast_regmap) * Configure interrupt enable registers such that Tag, Data RAM related * interrupts are propagated to interrupt controller for servicing */ - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_i= nterrupt_2_enable, TRP0_INTERRUPT_ENABLE, TRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->trp_i= nterrupt_0_enable, SB_DB_TRP_INTERRUPT_ENABLE, SB_DB_TRP_INTERRUPT_ENABLE); if (ret) return ret; =20 sb_err_threshold =3D (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT); - ret =3D regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_ecc_err= or_cfg, sb_err_threshold); if (ret) return ret; =20 - ret =3D regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE, + ret =3D regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_i= nterrupt_2_enable, DRP0_INTERRUPT_ENABLE, DRP0_INTERRUPT_ENABLE); if (ret) return ret; =20 - ret =3D regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE, + ret =3D regmap_write(llcc_bcast_regmap, drv->edac_reg_offset->drp_interru= pt_enable, SB_DB_DRP_INTERRUPT_ENABLE); return ret; } @@ -175,24 +133,28 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) switch (err_type) { case LLCC_DRAM_CE: case LLCC_DRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->drp_interrupt_clear, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->drp_ecc_error_cntr_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; break; case LLCC_TRAM_CE: case LLCC_TRAM_UE: - ret =3D regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->trp_interrupt_0_clear, DRP_TRP_INT_CLEAR); if (ret) return ret; =20 - ret =3D regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR, + ret =3D regmap_write(drv->bcast_regmap, + drv->edac_reg_offset->trp_ecc_error_cntr_clear, DRP_TRP_CNT_CLEAR); if (ret) return ret; @@ -205,16 +167,54 @@ qcom_llcc_clear_error_status(int err_type, struct llc= c_drv_data *drv) return ret; } =20 +struct qcom_llcc_syn_regs { + u32 synd_reg; + u32 count_status_reg; + u32 ways_status_reg; +}; + +static void get_reg_offsets(struct llcc_drv_data *drv, int err_type, + struct qcom_llcc_syn_regs *syn_regs) +{ + const struct llcc_edac_reg_offset *edac_reg_offset =3D drv->edac_reg_offs= et; + + switch (err_type) { + case LLCC_DRAM_CE: + syn_regs->synd_reg =3D edac_reg_offset->drp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->drp_ecc_error_status0; + break; + case LLCC_DRAM_UE: + syn_regs->synd_reg =3D edac_reg_offset->drp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->drp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->drp_ecc_error_status0; + break; + case LLCC_TRAM_CE: + syn_regs->synd_reg =3D edac_reg_offset->trp_ecc_sb_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->trp_ecc_error_status0; + break; + case LLCC_TRAM_UE: + syn_regs->synd_reg =3D edac_reg_offset->trp_ecc_db_err_syn0; + syn_regs->count_status_reg =3D edac_reg_offset->trp_ecc_error_status1; + syn_regs->ways_status_reg =3D edac_reg_offset->trp_ecc_error_status0; + break; + } +} + /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/ static int dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) { struct llcc_edac_reg_data reg_data =3D edac_reg_data[err_type]; + struct qcom_llcc_syn_regs regs =3D { }; int err_cnt, err_ways, ret, i; u32 synd_reg, synd_val; =20 + get_reg_offsets(drv, err_type, ®s); + for (i =3D 0; i < reg_data.reg_cnt; i++) { - synd_reg =3D reg_data.synd_reg + (i * 4); + synd_reg =3D regs.synd_reg + (i * 4); ret =3D regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) @@ -224,7 +224,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) reg_data.name, i, synd_val); } =20 - ret =3D regmap_read(drv->regmaps[bank], reg_data.count_status_reg, + ret =3D regmap_read(drv->regmaps[bank], regs.count_status_reg, &err_cnt); if (ret) goto clear; @@ -234,7 +234,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank= , int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); =20 - ret =3D regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, + ret =3D regmap_read(drv->regmaps[bank], regs.ways_status_reg, &err_ways); if (ret) goto clear; @@ -295,7 +295,7 @@ static irqreturn_t llcc_ecc_irq_handler(int irq, void *= edev_ctl) =20 /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i =3D 0; i < drv->num_banks; i++) { - ret =3D regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, + ret =3D regmap_read(drv->regmaps[i], drv->edac_reg_offset->drp_interrupt= _status, &drp_error); =20 if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -310,7 +310,7 @@ static irqreturn_t llcc_ecc_irq_handler(int irq, void *= edev_ctl) if (!ret) irq_rc =3D IRQ_HANDLED; =20 - ret =3D regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, + ret =3D regmap_read(drv->regmaps[i], drv->edac_reg_offset->trp_interrupt= _0_status, &trp_error); =20 if (!ret && (trp_error & SB_ECC_ERROR)) { @@ -342,7 +342,7 @@ static int qcom_llcc_edac_probe(struct platform_device = *pdev) int ecc_irq; int rc; =20 - rc =3D qcom_llcc_core_setup(llcc_driv_data->bcast_regmap); + rc =3D qcom_llcc_core_setup(llcc_driv_data, llcc_driv_data->bcast_regmap); if (rc) return rc; =20 diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/ll= cc-qcom.h index 423220e66026..93417ba1ead4 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -69,9 +69,6 @@ struct llcc_slice_desc { /** * struct llcc_edac_reg_data - llcc edac registers data for each error type * @name: Name of the error - * @synd_reg: Syndrome register address - * @count_status_reg: Status register address to read the error count - * @ways_status_reg: Status register address to read the error ways * @reg_cnt: Number of registers * @count_mask: Mask value to get the error count * @ways_mask: Mask value to get the error ways @@ -80,9 +77,6 @@ struct llcc_slice_desc { */ struct llcc_edac_reg_data { char *name; - u64 synd_reg; - u64 count_status_reg; - u64 ways_status_reg; u32 reg_cnt; u32 count_mask; u32 ways_mask; --=20 2.25.1