From nobody Sun Feb 8 06:00:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC29EC77B7F for ; Tue, 16 May 2023 08:30:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231428AbjEPIad (ORCPT ); Tue, 16 May 2023 04:30:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231490AbjEPIa2 (ORCPT ); Tue, 16 May 2023 04:30:28 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E1C041BFD for ; Tue, 16 May 2023 01:30:26 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 355C22F4; Tue, 16 May 2023 01:31:11 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.70.134]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 99DE63F7BD; Tue, 16 May 2023 01:30:23 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org Subject: [PATCH V3] arm64: Disable EL2 traps for BRBE instructions executed in EL1 Date: Tue, 16 May 2023 14:00:15 +0530 Message-Id: <20230516083015.569248-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This disables EL2 traps for BRBE instructions executed in EL1. This would enable BRBE to be configured and used successfully in the guest kernel. While here, this updates Documentation/arm64/booting.rst as well. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Acked-by: Marc Zyngier --- This patch applies on v6.4-rc2 Changes in V3: - Updated with RMW pattern as per Marc Changes in V2: https://lore.kernel.org/all/20230515105328.239204-1-anshuman.khandual@arm.c= om/ - Updated Documentation/arm64/booting.rst Changes in V1: https://lore.kernel.org/all/20230324055127.2228330-1-anshuman.khandual@arm.= com/ Documentation/arm64/booting.rst | 8 ++++++++ arch/arm64/include/asm/el2_setup.h | 10 ++++++++++ 2 files changed, 18 insertions(+) diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.= rst index ffeccdd6bdac..cb9e151f6928 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -379,6 +379,14 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. =20 + For CPUs with the Branch Record Buffer Extension (FEAT_BRBE): + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1. + + - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 037724b19c5c..bfaf41ad9c4e 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,6 +161,16 @@ msr_s SYS_HFGWTR_EL2, x0 msr_s SYS_HFGITR_EL2, xzr =20 + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 + cbz x1, .Lskip_brbe_\@ + + mrs_s x0, SYS_HFGITR_EL2 + orr x0, x0, #HFGITR_EL2_nBRBIALL + orr x0, x0, #HFGITR_EL2_nBRBINJ + msr_s SYS_HFGITR_EL2, x0 + +.Lskip_brbe_\@: mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 cbz x1, .Lskip_fgt_\@ --=20 2.25.1